1 /** 2 ****************************************************************************** 3 * @file uart_reg.h 4 * @version V1.0 5 * @date 2022-06-10 6 * @brief This file is the description of.IP register 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2> 11 * 12 * Redistribution and use in source and binary forms, with or without modification, 13 * are permitted provided that the following conditions are met: 14 * 1. Redistributions of source code must retain the above copyright notice, 15 * this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright notice, 17 * this list of conditions and the following disclaimer in the documentation 18 * and/or other materials provided with the distribution. 19 * 3. Neither the name of Bouffalo Lab nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 30 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 ****************************************************************************** 35 */ 36 #ifndef __HARDWARE_UART_H__ 37 #define __HARDWARE_UART_H__ 38 39 /**************************************************************************** 40 * Pre-processor Definitions 41 ****************************************************************************/ 42 43 /* Register offsets *********************************************************/ 44 45 #define UART_UTX_CONFIG_OFFSET (0x0) /* utx_config */ 46 #define UART_URX_CONFIG_OFFSET (0x4) /* urx_config */ 47 #define UART_BIT_PRD_OFFSET (0x8) /* uart_bit_prd */ 48 #define UART_DATA_CONFIG_OFFSET (0xC) /* data_config */ 49 #if !defined(BL702L) 50 #define UART_UTX_IR_POSITION_OFFSET (0x10) /* utx_ir_position */ 51 #define UART_URX_IR_POSITION_OFFSET (0x14) /* urx_ir_position */ 52 #endif 53 #define UART_URX_RTO_TIMER_OFFSET (0x18) /* urx_rto_timer */ 54 #if !defined(BL602) 55 #define UART_SW_MODE_OFFSET (0x1C) /* uart_sw_mode */ 56 #endif 57 #define UART_INT_STS_OFFSET (0x20) /* UART interrupt status */ 58 #define UART_INT_MASK_OFFSET (0x24) /* UART interrupt mask */ 59 #define UART_INT_CLEAR_OFFSET (0x28) /* UART interrupt clear */ 60 #define UART_INT_EN_OFFSET (0x2C) /* UART interrupt enable */ 61 #define UART_STATUS_OFFSET (0x30) /* uart_status */ 62 #define UART_STS_URX_ABR_PRD_OFFSET (0x34) /* sts_urx_abr_prd */ 63 #if !defined(BL602) && !defined(BL702) 64 #define UART_URX_ABR_PRD_B01_OFFSET (0x38) /* urx_abr_prd_b01 */ 65 #define UART_URX_ABR_PRD_B23_OFFSET (0x3C) /* urx_abr_prd_b23 */ 66 #define UART_URX_ABR_PRD_B45_OFFSET (0x40) /* urx_abr_prd_b45 */ 67 #define UART_URX_ABR_PRD_B67_OFFSET (0x44) /* urx_abr_prd_b67 */ 68 #define UART_URX_ABR_PW_TOL_OFFSET (0x48) /* urx_abr_pw_tol */ 69 #define UART_URX_BCR_INT_CFG_OFFSET (0x50) /* urx_bcr_int_cfg */ 70 #define UART_UTX_RS485_CFG_OFFSET (0x54) /* utx_rs485_cfg */ 71 #endif 72 #define UART_FIFO_CONFIG_0_OFFSET (0x80) /* uart_fifo_config_0 */ 73 #define UART_FIFO_CONFIG_1_OFFSET (0x84) /* uart_fifo_config_1 */ 74 #define UART_FIFO_WDATA_OFFSET (0x88) /* uart_fifo_wdata */ 75 #define UART_FIFO_RDATA_OFFSET (0x8C) /* uart_fifo_rdata */ 76 77 /* Register Bitfield definitions *****************************************************/ 78 79 /* 0x0 : utx_config */ 80 #define UART_CR_UTX_EN (1 << 0U) 81 #define UART_CR_UTX_CTS_EN (1 << 1U) 82 #define UART_CR_UTX_FRM_EN (1 << 2U) 83 #if !defined(BL602) 84 #define UART_CR_UTX_LIN_EN (1 << 3U) 85 #endif 86 #define UART_CR_UTX_PRT_EN (1 << 4U) 87 #define UART_CR_UTX_PRT_SEL (1 << 5U) 88 #if !defined(BL702L) 89 #define UART_CR_UTX_IR_EN (1 << 6U) 90 #define UART_CR_UTX_IR_INV (1 << 7U) 91 #endif 92 #define UART_CR_UTX_BIT_CNT_D_SHIFT (8U) 93 #define UART_CR_UTX_BIT_CNT_D_MASK (0x7 << UART_CR_UTX_BIT_CNT_D_SHIFT) 94 #if defined(BL602) 95 #define UART_CR_UTX_BIT_CNT_P_SHIFT (12U) 96 #else 97 #define UART_CR_UTX_BIT_CNT_P_SHIFT (11U) 98 #endif 99 #define UART_CR_UTX_BIT_CNT_P_MASK (0x3 << UART_CR_UTX_BIT_CNT_P_SHIFT) 100 #if !defined(BL602) 101 #define UART_CR_UTX_BIT_CNT_B_SHIFT (13U) 102 #define UART_CR_UTX_BIT_CNT_B_MASK (0x7 << UART_CR_UTX_BIT_CNT_B_SHIFT) 103 #endif 104 #define UART_CR_UTX_LEN_SHIFT (16U) 105 #define UART_CR_UTX_LEN_MASK (0xffff << UART_CR_UTX_LEN_SHIFT) 106 107 /* 0x4 : urx_config */ 108 #define UART_CR_URX_EN (1 << 0U) 109 #if defined(BL602) 110 #define UART_CR_URX_RTS_SW_MODE (1 << 1U) 111 #define UART_CR_URX_RTS_SW_VAL (1 << 2U) 112 #define UART_CR_URX_ABR_EN (1 << 3U) 113 #else 114 #define UART_CR_URX_ABR_EN (1 << 1U) 115 #define UART_CR_URX_LIN_EN (1 << 3U) 116 #endif 117 #define UART_CR_URX_PRT_EN (1 << 4U) 118 #define UART_CR_URX_PRT_SEL (1 << 5U) 119 #if !defined(BL702L) 120 #define UART_CR_URX_IR_EN (1 << 6U) 121 #define UART_CR_URX_IR_INV (1 << 7U) 122 #endif 123 #define UART_CR_URX_BIT_CNT_D_SHIFT (8U) 124 #define UART_CR_URX_BIT_CNT_D_MASK (0x7 << UART_CR_URX_BIT_CNT_D_SHIFT) 125 #define UART_CR_URX_DEG_EN (1 << 11U) 126 #define UART_CR_URX_DEG_CNT_SHIFT (12U) 127 #define UART_CR_URX_DEG_CNT_MASK (0xf << UART_CR_URX_DEG_CNT_SHIFT) 128 #define UART_CR_URX_LEN_SHIFT (16U) 129 #define UART_CR_URX_LEN_MASK (0xffff << UART_CR_URX_LEN_SHIFT) 130 131 /* 0x8 : uart_bit_prd */ 132 #define UART_CR_UTX_BIT_PRD_SHIFT (0U) 133 #define UART_CR_UTX_BIT_PRD_MASK (0xffff << UART_CR_UTX_BIT_PRD_SHIFT) 134 #define UART_CR_URX_BIT_PRD_SHIFT (16U) 135 #define UART_CR_URX_BIT_PRD_MASK (0xffff << UART_CR_URX_BIT_PRD_SHIFT) 136 137 /* 0xC : data_config */ 138 #define UART_CR_UART_BIT_INV (1 << 0U) 139 140 #if !defined(BL702L) 141 /* 0x10 : utx_ir_position */ 142 #define UART_CR_UTX_IR_POS_S_SHIFT (0U) 143 #define UART_CR_UTX_IR_POS_S_MASK (0xffff << UART_CR_UTX_IR_POS_S_SHIFT) 144 #define UART_CR_UTX_IR_POS_P_SHIFT (16U) 145 #define UART_CR_UTX_IR_POS_P_MASK (0xffff << UART_CR_UTX_IR_POS_P_SHIFT) 146 147 /* 0x14 : urx_ir_position */ 148 #define UART_CR_URX_IR_POS_S_SHIFT (0U) 149 #define UART_CR_URX_IR_POS_S_MASK (0xffff << UART_CR_URX_IR_POS_S_SHIFT) 150 #endif 151 152 /* 0x18 : urx_rto_timer */ 153 #define UART_CR_URX_RTO_VALUE_SHIFT (0U) 154 #define UART_CR_URX_RTO_VALUE_MASK (0xff << UART_CR_URX_RTO_VALUE_SHIFT) 155 156 #if !defined(BL602) 157 /* 0x1C : uart_sw_mode */ 158 #define UART_CR_UTX_TXD_SW_MODE (1 << 0U) 159 #define UART_CR_UTX_TXD_SW_VAL (1 << 1U) 160 #define UART_CR_URX_RTS_SW_MODE (1 << 2U) 161 #define UART_CR_URX_RTS_SW_VAL (1 << 3U) 162 #endif 163 164 /* 0x20 : UART interrupt status */ 165 #define UART_UTX_END_INT (1 << 0U) 166 #define UART_URX_END_INT (1 << 1U) 167 #define UART_UTX_FIFO_INT (1 << 2U) 168 #define UART_URX_FIFO_INT (1 << 3U) 169 #define UART_URX_RTO_INT (1 << 4U) 170 #define UART_URX_PCE_INT (1 << 5U) 171 #define UART_UTX_FER_INT (1 << 6U) 172 #define UART_URX_FER_INT (1 << 7U) 173 #if !defined(BL602) 174 #define UART_URX_LSE_INT (1 << 8U) 175 #endif 176 #if !defined(BL602) && !defined(BL702) 177 #define UART_URX_BCR_INT (1 << 9U) 178 #define UART_URX_ADS_INT (1 << 10U) 179 #define UART_URX_AD5_INT (1 << 11U) 180 #endif 181 182 /* 0x24 : UART interrupt mask */ 183 #define UART_CR_UTX_END_MASK (1 << 0U) 184 #define UART_CR_URX_END_MASK (1 << 1U) 185 #define UART_CR_UTX_FIFO_MASK (1 << 2U) 186 #define UART_CR_URX_FIFO_MASK (1 << 3U) 187 #define UART_CR_URX_RTO_MASK (1 << 4U) 188 #define UART_CR_URX_PCE_MASK (1 << 5U) 189 #define UART_CR_UTX_FER_MASK (1 << 6U) 190 #define UART_CR_URX_FER_MASK (1 << 7U) 191 #if !defined(BL602) 192 #define UART_CR_URX_LSE_MASK (1 << 8U) 193 #endif 194 #if !defined(BL602) && !defined(BL702) 195 #define UART_CR_URX_BCR_MASK (1 << 9U) 196 #define UART_CR_URX_ADS_MASK (1 << 10U) 197 #define UART_CR_URX_AD5_MASK (1 << 11U) 198 #endif 199 200 /* 0x28 : UART interrupt clear */ 201 #define UART_CR_UTX_END_CLR (1 << 0U) 202 #define UART_CR_URX_END_CLR (1 << 1U) 203 #define UART_CR_URX_RTO_CLR (1 << 4U) 204 #define UART_CR_URX_PCE_CLR (1 << 5U) 205 #if !defined(BL602) 206 #define UART_CR_URX_LSE_CLR (1 << 8U) 207 #endif 208 #if !defined(BL602) && !defined(BL702) 209 #define UART_CR_URX_BCR_CLR (1 << 9U) 210 #define UART_CR_URX_ADS_CLR (1 << 10U) 211 #define UART_CR_URX_AD5_CLR (1 << 11U) 212 #endif 213 214 /* 0x2C : UART interrupt enable */ 215 #define UART_CR_UTX_END_EN (1 << 0U) 216 #define UART_CR_URX_END_EN (1 << 1U) 217 #define UART_CR_UTX_FIFO_EN (1 << 2U) 218 #define UART_CR_URX_FIFO_EN (1 << 3U) 219 #define UART_CR_URX_RTO_EN (1 << 4U) 220 #define UART_CR_URX_PCE_EN (1 << 5U) 221 #define UART_CR_UTX_FER_EN (1 << 6U) 222 #define UART_CR_URX_FER_EN (1 << 7U) 223 #if !defined(BL602) 224 #define UART_CR_URX_LSE_EN (1 << 8U) 225 #endif 226 #if !defined(BL602) && !defined(BL702) 227 #define UART_CR_URX_BCR_EN (1 << 9U) 228 #define UART_CR_URX_ADS_EN (1 << 10U) 229 #define UART_CR_URX_AD5_EN (1 << 11U) 230 #endif 231 232 /* 0x30 : uart_status */ 233 #define UART_STS_UTX_BUS_BUSY (1 << 0U) 234 #define UART_STS_URX_BUS_BUSY (1 << 1U) 235 236 /* 0x34 : sts_urx_abr_prd */ 237 #define UART_STS_URX_ABR_PRD_START_SHIFT (0U) 238 #define UART_STS_URX_ABR_PRD_START_MASK (0xffff << UART_STS_URX_ABR_PRD_START_SHIFT) 239 #define UART_STS_URX_ABR_PRD_0X55_SHIFT (16U) 240 #if defined(BL702L) 241 #define UART_STS_URX_ABR_PRD_0X55_MASK (0x3ff << UART_STS_URX_ABR_PRD_0X55_SHIFT) 242 #else 243 #define UART_STS_URX_ABR_PRD_0X55_MASK (0xffff << UART_STS_URX_ABR_PRD_0X55_SHIFT) 244 #endif 245 246 #if !defined(BL602) && !defined(BL702) 247 /* 0x38 : urx_abr_prd_b01 */ 248 #define UART_STS_URX_ABR_PRD_BIT0_SHIFT (0U) 249 #if defined(BL702L) 250 #define UART_STS_URX_ABR_PRD_BIT0_MASK (0x3ff << UART_STS_URX_ABR_PRD_BIT0_SHIFT) 251 #else 252 #define UART_STS_URX_ABR_PRD_BIT0_MASK (0xffff << UART_STS_URX_ABR_PRD_BIT0_SHIFT) 253 #endif 254 #define UART_STS_URX_ABR_PRD_BIT1_SHIFT (16U) 255 #if defined(BL702L) 256 #define UART_STS_URX_ABR_PRD_BIT1_MASK (0x3ff << UART_STS_URX_ABR_PRD_BIT1_SHIFT) 257 #else 258 #define UART_STS_URX_ABR_PRD_BIT1_MASK (0xffff << UART_STS_URX_ABR_PRD_BIT1_SHIFT) 259 #endif 260 261 /* 0x3C : urx_abr_prd_b23 */ 262 #define UART_STS_URX_ABR_PRD_BIT2_SHIFT (0U) 263 #if defined(BL702L) 264 #define UART_STS_URX_ABR_PRD_BIT2_MASK (0x3ff << UART_STS_URX_ABR_PRD_BIT2_SHIFT) 265 #else 266 #define UART_STS_URX_ABR_PRD_BIT2_MASK (0xffff << UART_STS_URX_ABR_PRD_BIT2_SHIFT) 267 #endif 268 #define UART_STS_URX_ABR_PRD_BIT3_SHIFT (16U) 269 #if defined(BL702L) 270 #define UART_STS_URX_ABR_PRD_BIT3_MASK (0x3ff << UART_STS_URX_ABR_PRD_BIT3_SHIFT) 271 #else 272 #define UART_STS_URX_ABR_PRD_BIT3_MASK (0xffff << UART_STS_URX_ABR_PRD_BIT3_SHIFT) 273 #endif 274 275 /* 0x40 : urx_abr_prd_b45 */ 276 #define UART_STS_URX_ABR_PRD_BIT4_SHIFT (0U) 277 #if defined(BL702L) 278 #define UART_STS_URX_ABR_PRD_BIT4_MASK (0x3ff << UART_STS_URX_ABR_PRD_BIT4_SHIFT) 279 #else 280 #define UART_STS_URX_ABR_PRD_BIT4_MASK (0xffff << UART_STS_URX_ABR_PRD_BIT4_SHIFT) 281 #endif 282 #define UART_STS_URX_ABR_PRD_BIT5_SHIFT (16U) 283 #if defined(BL702L) 284 #define UART_STS_URX_ABR_PRD_BIT5_MASK (0x3ff << UART_STS_URX_ABR_PRD_BIT5_SHIFT) 285 #else 286 #define UART_STS_URX_ABR_PRD_BIT5_MASK (0xffff << UART_STS_URX_ABR_PRD_BIT5_SHIFT) 287 #endif 288 289 /* 0x44 : urx_abr_prd_b67 */ 290 #define UART_STS_URX_ABR_PRD_BIT6_SHIFT (0U) 291 #if defined(BL702L) 292 #define UART_STS_URX_ABR_PRD_BIT6_MASK (0x3ff << UART_STS_URX_ABR_PRD_BIT6_SHIFT) 293 #else 294 #define UART_STS_URX_ABR_PRD_BIT6_MASK (0xffff << UART_STS_URX_ABR_PRD_BIT6_SHIFT) 295 #endif 296 #define UART_STS_URX_ABR_PRD_BIT7_SHIFT (16U) 297 #if defined(BL702L) 298 #define UART_STS_URX_ABR_PRD_BIT7_MASK (0x3ff << UART_STS_URX_ABR_PRD_BIT7_SHIFT) 299 #else 300 #define UART_STS_URX_ABR_PRD_BIT7_MASK (0xffff << UART_STS_URX_ABR_PRD_BIT7_SHIFT) 301 #endif 302 303 /* 0x48 : urx_abr_pw_tol */ 304 #define UART_CR_URX_ABR_PW_TOL_SHIFT (0U) 305 #define UART_CR_URX_ABR_PW_TOL_MASK (0xff << UART_CR_URX_ABR_PW_TOL_SHIFT) 306 307 /* 0x50 : urx_bcr_int_cfg */ 308 #define UART_CR_URX_BCR_VALUE_SHIFT (0U) 309 #define UART_CR_URX_BCR_VALUE_MASK (0xffff << UART_CR_URX_BCR_VALUE_SHIFT) 310 #define UART_STS_URX_BCR_COUNT_SHIFT (16U) 311 #define UART_STS_URX_BCR_COUNT_MASK (0xffff << UART_STS_URX_BCR_COUNT_SHIFT) 312 313 /* 0x54 : utx_rs485_cfg */ 314 #define UART_CR_UTX_RS485_EN (1 << 0U) 315 #define UART_CR_UTX_RS485_POL (1 << 1U) 316 #endif 317 318 /* 0x80 : uart_fifo_config_0 */ 319 #define UART_DMA_TX_EN (1 << 0U) 320 #define UART_DMA_RX_EN (1 << 1U) 321 #define UART_TX_FIFO_CLR (1 << 2U) 322 #define UART_RX_FIFO_CLR (1 << 3U) 323 #define UART_TX_FIFO_OVERFLOW (1 << 4U) 324 #define UART_TX_FIFO_UNDERFLOW (1 << 5U) 325 #define UART_RX_FIFO_OVERFLOW (1 << 6U) 326 #define UART_RX_FIFO_UNDERFLOW (1 << 7U) 327 328 /* 0x84 : uart_fifo_config_1 */ 329 #define UART_TX_FIFO_CNT_SHIFT (0U) 330 #if defined(BL702) 331 #define UART_TX_FIFO_CNT_MASK (0xff << UART_TX_FIFO_CNT_SHIFT) 332 #elif defined(BL702L) 333 #define UART_TX_FIFO_CNT_MASK (0x1f << UART_TX_FIFO_CNT_SHIFT) 334 #else 335 #define UART_TX_FIFO_CNT_MASK (0x3f << UART_TX_FIFO_CNT_SHIFT) 336 #endif 337 #define UART_RX_FIFO_CNT_SHIFT (8U) 338 #if defined(BL702) 339 #define UART_RX_FIFO_CNT_MASK (0xff << UART_RX_FIFO_CNT_SHIFT) 340 #elif defined(BL702L) 341 #define UART_RX_FIFO_CNT_MASK (0x1f << UART_RX_FIFO_CNT_SHIFT) 342 #else 343 #define UART_RX_FIFO_CNT_MASK (0x3f << UART_RX_FIFO_CNT_SHIFT) 344 #endif 345 #define UART_TX_FIFO_TH_SHIFT (16U) 346 #if defined(BL702) 347 #define UART_TX_FIFO_TH_MASK (0x7f << UART_TX_FIFO_TH_SHIFT) 348 #elif defined(BL702L) 349 #define UART_TX_FIFO_TH_MASK (0xf << UART_TX_FIFO_TH_SHIFT) 350 #else 351 #define UART_TX_FIFO_TH_MASK (0x1f << UART_TX_FIFO_TH_SHIFT) 352 #endif 353 #define UART_RX_FIFO_TH_SHIFT (24U) 354 #if defined(BL702) 355 #define UART_RX_FIFO_TH_MASK (0x7f << UART_RX_FIFO_TH_SHIFT) 356 #elif defined(BL702L) 357 #define UART_RX_FIFO_TH_MASK (0xf << UART_RX_FIFO_TH_SHIFT) 358 #else 359 #define UART_RX_FIFO_TH_MASK (0x1f << UART_RX_FIFO_TH_SHIFT) 360 #endif 361 362 /* 0x88 : uart_fifo_wdata */ 363 #define UART_FIFO_WDATA_SHIFT (0U) 364 #define UART_FIFO_WDATA_MASK (0xff << UART_FIFO_WDATA_SHIFT) 365 366 /* 0x8C : uart_fifo_rdata */ 367 #define UART_FIFO_RDATA_SHIFT (0U) 368 #define UART_FIFO_RDATA_MASK (0xff << UART_FIFO_RDATA_SHIFT) 369 370 #endif /* __HARDWARE_UART_H__ */ 371