1 /*
2 * This is a generated file
3 *
4 * Copyright 2021 QuickLogic
5 *
6 * Licensed under the Apache License, Version 2.0 (the "License");
7 * you may not use this file except in compliance with the License.
8 * You may obtain a copy of the License at
9 *
10 * http://www.apache.org/licenses/LICENSE-2.0
11 *
12 * Unless required by applicable law or agreed to in writing, software
13 * distributed under the License is distributed on an "AS IS" BASIS,
14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 * See the License for the specific language governing permissions and
16 * limitations under the License.
17 *
18 * SPDX-License-Identifier: Apache-2.0
19 */
20
21 #ifndef __UDMA_I2CM_H_
22 #define __UDMA_I2CM_H_
23
24 //---------------------------------//
25 //
26 // Module: UDMA_I2CM
27 //
28 //---------------------------------//
29
30 #ifndef __IO
31 #define __IO volatile
32 #endif
33
34 #ifndef __I
35 #define __I volatile
36 #endif
37
38 #ifndef __O
39 #define __O volatile
40 #endif
41
42 #include "stdint.h"
43
44 typedef struct {
45
46 // Offset = 0x0000
47 union {
48 __IO uint32_t rx_saddr;
49 struct {
50 __IO uint32_t saddr : 12;
51 } rx_saddr_b;
52 };
53
54 // Offset = 0x0004
55 union {
56 __IO uint32_t rx_size;
57 struct {
58 __IO uint32_t size : 16;
59 } rx_size_b;
60 };
61
62 // Offset = 0x0008
63 union {
64 __IO uint32_t rx_cfg;
65 struct {
66 __IO uint32_t continuous : 1;
67 __IO uint32_t : 3;
68 __IO uint32_t en : 1;
69 __IO uint32_t pending : 1;
70 __IO uint32_t clr : 1;
71 } rx_cfg_b;
72 };
73 __I uint32_t unused0[1];
74
75 // Offset = 0x0010
76 union {
77 __IO uint32_t tx_saddr;
78 struct {
79 __IO uint32_t saddr : 12;
80 } tx_saddr_b;
81 };
82
83 // Offset = 0x0014
84 union {
85 __IO uint32_t tx_size;
86 struct {
87 __IO uint32_t size : 16;
88 } tx_size_b;
89 };
90
91 // Offset = 0x0018
92 union {
93 __IO uint32_t tx_cfg;
94 struct {
95 __IO uint32_t continuous : 1;
96 __IO uint32_t : 3;
97 __IO uint32_t en : 1;
98 __IO uint32_t pending : 1;
99 __IO uint32_t clr : 1;
100 } tx_cfg_b;
101 };
102 __I uint32_t unused1[1];
103
104 // Offset = 0x0020
105 union {
106 __IO uint32_t status;
107 struct {
108 __IO uint32_t busy : 1;
109 __IO uint32_t al : 1;
110 } status_b;
111 };
112
113 // Offset = 0x0024
114 union {
115 __IO uint32_t setup;
116 struct {
117 __IO uint32_t reset : 1;
118 } setup_b;
119 };
120 } UdmaI2cm_t;
121
122
123 #define REG_RX_SADDR 0x00
124 #define REG_RX_SADDR_SADDR_LSB 0
125 #define REG_RX_SADDR_SADDR_MASK 0xfff
126 #define REG_RX_SIZE 0x04
127 #define REG_RX_SIZE_SIZE_LSB 0
128 #define REG_RX_SIZE_SIZE_MASK 0xffff
129 #define REG_RX_CFG 0x08
130 #define REG_RX_CFG_CLR_LSB 6
131 #define REG_RX_CFG_CLR_MASK 0x1
132 #define REG_RX_CFG_PENDING_LSB 5
133 #define REG_RX_CFG_PENDING_MASK 0x1
134 #define REG_RX_CFG_EN_LSB 4
135 #define REG_RX_CFG_EN_MASK 0x1
136 #define REG_RX_CFG_CONTINUOUS_LSB 0
137 #define REG_RX_CFG_CONTINUOUS_MASK 0x1
138 #define REG_TX_SADDR 0x10
139 #define REG_TX_SADDR_SADDR_LSB 0
140 #define REG_TX_SADDR_SADDR_MASK 0xfff
141 #define REG_TX_SIZE 0x14
142 #define REG_TX_SIZE_SIZE_LSB 0
143 #define REG_TX_SIZE_SIZE_MASK 0xffff
144 #define REG_TX_CFG 0x18
145 #define REG_TX_CFG_CLR_LSB 6
146 #define REG_TX_CFG_CLR_MASK 0x1
147 #define REG_TX_CFG_PENDING_LSB 5
148 #define REG_TX_CFG_PENDING_MASK 0x1
149 #define REG_TX_CFG_EN_LSB 4
150 #define REG_TX_CFG_EN_MASK 0x1
151 #define REG_TX_CFG_CONTINUOUS_LSB 0
152 #define REG_TX_CFG_CONTINUOUS_MASK 0x1
153 #define REG_STATUS 0x20
154 #define REG_STATUS_AL_LSB 1
155 #define REG_STATUS_AL_MASK 0x1
156 #define REG_STATUS_BUSY_LSB 0
157 #define REG_STATUS_BUSY_MASK 0x1
158 #define REG_SETUP 0x24
159 #define REG_SETUP_RESET_LSB 0
160 #define REG_SETUP_RESET_MASK 0x1
161
162 #ifndef __REGFIELD_OPS_
163 #define __REGFIELD_OPS_
regfield_read(uint32_t reg,uint32_t mask,uint32_t lsb)164 static inline uint32_t regfield_read(uint32_t reg, uint32_t mask, uint32_t lsb) {
165 return (reg >> lsb) & mask;
166 }
regfield_write(uint32_t reg,uint32_t mask,uint32_t lsb,uint32_t value)167 static inline uint32_t regfield_write(uint32_t reg, uint32_t mask, uint32_t lsb, uint32_t value) {
168 reg &= ~(mask << lsb);
169 reg |= (value & mask) << lsb;
170 return reg;
171 }
172 #endif // __REGFIELD_OPS_
173
174 #endif // __UDMA_I2CM_H_
175