1 /* 2 * Copyright (c) 2006-2022, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2022-10-10 RT-Thread the first version, 9 * compatible to riscv-v-spec-1.0 10 */ 11 12 #ifndef __VECTOR_ENCODING_1_0_H__ 13 #define __VECTOR_ENCODING_1_0_H__ 14 15 /* mstatus/sstatus */ 16 #define MSTATUS_VS 0x00000600 17 #define SSTATUS_VS 0x00000600 /* Vector Status */ 18 #define SSTATUS_VS_INITIAL 0x00000200 19 #define SSTATUS_VS_CLEAN 0x00000400 20 #define SSTATUS_VS_DIRTY 0x00000600 21 22 #ifdef __ASSEMBLY__ 23 24 /** 25 * assembler names used for vset{i}vli vtypei immediate 26 */ 27 28 #define VEC_IMM_SEW_8 e8 29 #define VEC_IMM_SEW_16 e16 30 #define VEC_IMM_SEW_32 e32 31 #define VEC_IMM_SEW_64 e64 32 /* group setting, encoding by multiplier */ 33 #define VEC_IMM_LMUL_F8 mf8 34 #define VEC_IMM_LMUL_F4 mf4 35 #define VEC_IMM_LMUL_F2 mf2 36 #define VEC_IMM_LMUL_1 m1 37 #define VEC_IMM_LMUL_2 m2 38 #define VEC_IMM_LMUL_4 m4 39 #define VEC_IMM_LMUL_8 m8 40 /* TAIL & MASK agnostic bits */ 41 #define VEC_IMM_TAIL_AGNOSTIC ta 42 #define VEC_IMM_MASK_AGNOSTIC ma 43 #define VEC_IMM_TAMA VEC_IMM_TAIL_AGNOSTIC, VEC_IMM_MASK_AGNOSTIC 44 #define VEC_IMM_TAMU VEC_IMM_TAIL_AGNOSTIC 45 #define VEC_IMM_TUMA VEC_IMM_MASK_AGNOSTIC 46 47 /** 48 * configuration setting instruction 49 */ 50 #define VEC_CONFIG_SETVLI(xVl, xAvl, vtype...) vsetvli xVl, xAvl, ##vtype 51 #define VEC_CONFIG_SET_VL_VTYPE(xVl, xVtype) vsetvl x0, xVl, xVtype 52 53 #endif 54 55 #endif /* __VECTOR_ENCODING_H__ */ 56