1 //########################################################################### 2 // 3 // FILE: F2837xD_mcbsp.h 4 // 5 // TITLE: MCBSP Register Definitions. 6 // 7 //########################################################################### 8 // $TI Release: F2837xD Support Library v3.05.00.00 $ 9 // $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ 10 // $Copyright: 11 // Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ 12 // 13 // Redistribution and use in source and binary forms, with or without 14 // modification, are permitted provided that the following conditions 15 // are met: 16 // 17 // Redistributions of source code must retain the above copyright 18 // notice, this list of conditions and the following disclaimer. 19 // 20 // Redistributions in binary form must reproduce the above copyright 21 // notice, this list of conditions and the following disclaimer in the 22 // documentation and/or other materials provided with the 23 // distribution. 24 // 25 // Neither the name of Texas Instruments Incorporated nor the names of 26 // its contributors may be used to endorse or promote products derived 27 // from this software without specific prior written permission. 28 // 29 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 // $ 41 //########################################################################### 42 43 #ifndef __F2837xD_MCBSP_H__ 44 #define __F2837xD_MCBSP_H__ 45 46 #ifdef __cplusplus 47 extern "C" { 48 #endif 49 50 51 //--------------------------------------------------------------------------- 52 // MCBSP Individual Register Bit Definitions: 53 54 struct DRR2_BITS { // bits description 55 Uint16 HWLB:8; // 7:0 High word low byte 56 Uint16 HWHB:8; // 15:8 High word high byte 57 }; 58 59 union DRR2_REG { 60 Uint16 all; 61 struct DRR2_BITS bit; 62 }; 63 64 struct DRR1_BITS { // bits description 65 Uint16 LWLB:8; // 7:0 Low word low byte 66 Uint16 LWHB:8; // 15:8 Low word high byte 67 }; 68 69 union DRR1_REG { 70 Uint16 all; 71 struct DRR1_BITS bit; 72 }; 73 74 struct DXR2_BITS { // bits description 75 Uint16 HWLB:8; // 7:0 High word low byte 76 Uint16 HWHB:8; // 15:8 High word high byte 77 }; 78 79 union DXR2_REG { 80 Uint16 all; 81 struct DXR2_BITS bit; 82 }; 83 84 struct DXR1_BITS { // bits description 85 Uint16 LWLB:8; // 7:0 Low word low byte 86 Uint16 LWHB:8; // 15:8 Low word high byte 87 }; 88 89 union DXR1_REG { 90 Uint16 all; 91 struct DXR1_BITS bit; 92 }; 93 94 struct SPCR2_BITS { // bits description 95 Uint16 XRST:1; // 0 Transmitter reset 96 Uint16 XRDY:1; // 1 Transmitter ready 97 Uint16 XEMPTY:1; // 2 Transmitter empty 98 Uint16 XSYNCERR:1; // 3 Transmit sync error INT flag 99 Uint16 XINTM:2; // 5:4 Transmit Interupt mode bits 100 Uint16 GRST:1; // 6 Sample rate generator reset 101 Uint16 FRST:1; // 7 Frame sync logic reset 102 Uint16 SOFT:1; // 8 SOFT bit 103 Uint16 FREE:1; // 9 FREE bit 104 Uint16 rsvd1:6; // 15:10 Reserved 105 }; 106 107 union SPCR2_REG { 108 Uint16 all; 109 struct SPCR2_BITS bit; 110 }; 111 112 struct SPCR1_BITS { // bits description 113 Uint16 RRST:1; // 0 Receiver reset 114 Uint16 RRDY:1; // 1 Receiver ready 115 Uint16 RFULL:1; // 2 Receiver full 116 Uint16 RSYNCERR:1; // 3 Receive sync error INT flag 117 Uint16 RINTM:2; // 5:4 Receive Interupt mode bits 118 Uint16 rsvd1:1; // 6 Reserved 119 Uint16 DXENA:1; // 7 DX delay enable 120 Uint16 rsvd2:3; // 10:8 Reserved 121 Uint16 CLKSTP:2; // 12:11 Clock stop mode 122 Uint16 RJUST:2; // 14:13 Rx sign extension and justification mode 123 Uint16 DLB:1; // 15 Digital loopback 124 }; 125 126 union SPCR1_REG { 127 Uint16 all; 128 struct SPCR1_BITS bit; 129 }; 130 131 struct RCR2_BITS { // bits description 132 Uint16 RDATDLY:2; // 1:0 Receive data delay 133 Uint16 RFIG:1; // 2 Receive frame sync ignore 134 Uint16 RCOMPAND:2; // 4:3 Receive Companding Mode selects 135 Uint16 RWDLEN2:3; // 7:5 Receive word length 2 136 Uint16 RFRLEN2:7; // 14:8 Receive Frame length 2 137 Uint16 RPHASE:1; // 15 Receive Phase 138 }; 139 140 union RCR2_REG { 141 Uint16 all; 142 struct RCR2_BITS bit; 143 }; 144 145 struct RCR1_BITS { // bits description 146 Uint16 rsvd1:5; // 4:0 Reserved 147 Uint16 RWDLEN1:3; // 7:5 Receive word length 1 148 Uint16 RFRLEN1:7; // 14:8 Receive Frame length 1 149 Uint16 rsvd2:1; // 15 Reserved 150 }; 151 152 union RCR1_REG { 153 Uint16 all; 154 struct RCR1_BITS bit; 155 }; 156 157 struct XCR2_BITS { // bits description 158 Uint16 XDATDLY:2; // 1:0 Transmit data delay 159 Uint16 XFIG:1; // 2 Transmit frame sync ignore 160 Uint16 XCOMPAND:2; // 4:3 Transmit Companding Mode selects 161 Uint16 XWDLEN2:3; // 7:5 Transmit word length 2 162 Uint16 XFRLEN2:7; // 14:8 Transmit Frame length 2 163 Uint16 XPHASE:1; // 15 Transmit Phase 164 }; 165 166 union XCR2_REG { 167 Uint16 all; 168 struct XCR2_BITS bit; 169 }; 170 171 struct XCR1_BITS { // bits description 172 Uint16 rsvd1:5; // 4:0 Reserved 173 Uint16 XWDLEN1:3; // 7:5 Transmit word length 1 174 Uint16 XFRLEN1:7; // 14:8 Transmit Frame length 1 175 Uint16 rsvd2:1; // 15 Reserved 176 }; 177 178 union XCR1_REG { 179 Uint16 all; 180 struct XCR1_BITS bit; 181 }; 182 183 struct SRGR2_BITS { // bits description 184 Uint16 FPER:12; // 11:0 Frame-sync period 185 Uint16 FSGM:1; // 12 Frame sync generator mode 186 Uint16 CLKSM:1; // 13 Sample rate generator mode 187 Uint16 rsvd1:1; // 14 Reserved 188 Uint16 GSYNC:1; // 15 CLKG sync 189 }; 190 191 union SRGR2_REG { 192 Uint16 all; 193 struct SRGR2_BITS bit; 194 }; 195 196 struct SRGR1_BITS { // bits description 197 Uint16 CLKGDV:8; // 7:0 CLKG divider 198 Uint16 FWID:8; // 15:8 Frame width 199 }; 200 201 union SRGR1_REG { 202 Uint16 all; 203 struct SRGR1_BITS bit; 204 }; 205 206 struct MCR2_BITS { // bits description 207 Uint16 XMCM:2; // 1:0 Transmit data delay 208 Uint16 XCBLK:3; // 4:2 Transmit frame sync ignore 209 Uint16 XPABLK:2; // 6:5 Transmit Companding Mode selects 210 Uint16 XPBBLK:2; // 8:7 Transmit word length 2 211 Uint16 XMCME:1; // 9 Transmit Frame length 2 212 Uint16 rsvd1:6; // 15:10 Reserved 213 }; 214 215 union MCR2_REG { 216 Uint16 all; 217 struct MCR2_BITS bit; 218 }; 219 220 struct MCR1_BITS { // bits description 221 Uint16 RMCM:1; // 0 Receive multichannel mode 222 Uint16 rsvd1:1; // 1 Reserved 223 Uint16 RCBLK:3; // 4:2 eceive current block 224 Uint16 RPABLK:2; // 6:5 Receive partition A Block 225 Uint16 RPBBLK:2; // 8:7 Receive partition B Block 226 Uint16 RMCME:1; // 9 Receive multi-channel enhance mode 227 Uint16 rsvd2:6; // 15:10 Reserved 228 }; 229 230 union MCR1_REG { 231 Uint16 all; 232 struct MCR1_BITS bit; 233 }; 234 235 struct PCR_BITS { // bits description 236 Uint16 CLKRP:1; // 0 Receive Clock polarity 237 Uint16 CLKXP:1; // 1 Transmit clock polarity 238 Uint16 FSRP:1; // 2 Receive Frame synchronization polarity 239 Uint16 FSXP:1; // 3 Transmit Frame synchronization polarity 240 Uint16 rsvd1:1; // 4 Reserved 241 Uint16 rsvd2:1; // 5 Reserved 242 Uint16 rsvd3:1; // 6 Reserved 243 Uint16 SCLKME:1; // 7 Sample clock mode selection 244 Uint16 CLKRM:1; // 8 Receiver Clock Mode 245 Uint16 CLKXM:1; // 9 Transmit Clock Mode. 246 Uint16 FSRM:1; // 10 Receive Frame Synchronization Mode 247 Uint16 FSXM:1; // 11 Transmit Frame Synchronization Mode 248 Uint16 rsvd4:4; // 15:12 Reserved 249 }; 250 251 union PCR_REG { 252 Uint16 all; 253 struct PCR_BITS bit; 254 }; 255 256 struct MFFINT_BITS { // bits description 257 Uint16 XINT:1; // 0 Enable for Receive Interrupt 258 Uint16 rsvd1:1; // 1 Reserved 259 Uint16 RINT:1; // 2 Enable for transmit Interrupt 260 Uint16 rsvd2:13; // 15:3 Reserved 261 }; 262 263 union MFFINT_REG { 264 Uint16 all; 265 struct MFFINT_BITS bit; 266 }; 267 268 struct McBSP_REGS { 269 union DRR2_REG DRR2; // Data receive register bits 31-16 270 union DRR1_REG DRR1; // Data receive register bits 15-0 271 union DXR2_REG DXR2; // Data transmit register bits 31-16 272 union DXR1_REG DXR1; // Data transmit register bits 15-0 273 union SPCR2_REG SPCR2; // Control register 2 274 union SPCR1_REG SPCR1; // Control register 1 275 union RCR2_REG RCR2; // Receive Control register 2 276 union RCR1_REG RCR1; // Receive Control register 1 277 union XCR2_REG XCR2; // Transmit Control register 2 278 union XCR1_REG XCR1; // Transmit Control register 1 279 union SRGR2_REG SRGR2; // Sample rate generator register 2 280 union SRGR1_REG SRGR1; // Sample rate generator register 1 281 union MCR2_REG MCR2; // Multi-channel register 2 282 union MCR1_REG MCR1; // Multi-channel register 1 283 Uint16 RCERA; // Receive channel enable partition A 284 Uint16 RCERB; // Receive channel enable partition B 285 Uint16 XCERA; // Transmit channel enable partition A 286 Uint16 XCERB; // Transmit channel enable partition B 287 union PCR_REG PCR; // Pin Control register 288 Uint16 RCERC; // Receive channel enable partition C 289 Uint16 RCERD; // Receive channel enable partition D 290 Uint16 XCERC; // Transmit channel enable partition C 291 Uint16 XCERD; // Transmit channel enable partition D 292 Uint16 RCERE; // Receive channel enable partition E 293 Uint16 RCERF; // Receive channel enable partition F 294 Uint16 XCERE; // Transmit channel enable partition E 295 Uint16 XCERF; // Transmit channel enable partition F 296 Uint16 RCERG; // Receive channel enable partition G 297 Uint16 RCERH; // Receive channel enable partition H 298 Uint16 XCERG; // Transmit channel enable partition G 299 Uint16 XCERH; // Transmit channel enable partition H 300 Uint16 rsvd1[4]; // Reserved 301 union MFFINT_REG MFFINT; // Interrupt enable 302 }; 303 304 //--------------------------------------------------------------------------- 305 // MCBSP External References & Function Declarations: 306 // 307 #ifdef CPU1 308 extern volatile struct McBSP_REGS McbspaRegs; 309 extern volatile struct McBSP_REGS McbspbRegs; 310 #endif 311 #ifdef CPU2 312 extern volatile struct McBSP_REGS McbspaRegs; 313 extern volatile struct McBSP_REGS McbspbRegs; 314 #endif 315 #ifdef __cplusplus 316 } 317 #endif /* extern "C" */ 318 319 #endif 320 321 //=========================================================================== 322 // End of file. 323 //=========================================================================== 324