1 /****************************************************************************** 2 * Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 ******************************************************************************/ 5 6 /*****************************************************************************/ 7 /** 8 * 9 * @file xemacps_hw.h 10 * @addtogroup emacps_v3_11 11 * @{ 12 * 13 * This header file contains identifiers and low-level driver functions (or 14 * macros) that can be used to access the PS Ethernet MAC (XEmacPs) device. 15 * High-level driver functions are defined in xemacps.h. 16 * 17 * @note 18 * 19 * <pre> 20 * MODIFICATION HISTORY: 21 * 22 * Ver Who Date Changes 23 * ----- ---- -------- ------------------------------------------------------- 24 * 1.00a wsy 01/10/10 First release. 25 * 1.02a asa 11/05/12 Added hash defines for DMACR burst length configuration. 26 * 1.05a kpc 28/06/13 Added XEmacPs_ResetHw function prototype 27 * 1.06a asa 11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff 28 * to 0x1fff. This fixes the CR#744902. 29 * 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp GEM specification. 30 * 3.0 kvn 12/16/14 Changed name of XEMACPS_NWCFG_LENGTHERRDSCRD_MASK to 31 * XEMACPS_NWCFG_LENERRDSCRD_MASK as it exceeds 31 characters. 32 * 3.0 kpc 1/23/15 Corrected the extended descriptor macro values. 33 * 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance. 34 * 3.0 hk 03/18/15 Added support for jumbo frames. 35 * Remove "used bit set" from TX error interrupt masks. 36 * 3.1 hk 08/10/15 Update upper 32 bit tx and rx queue ptr register offsets. 37 * 3.2 hk 02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC. 38 * 3.8 hk 09/17/18 Fix PTP interrupt masks. 39 * 3.9 hk 01/23/19 Add RX watermark support 40 * 3.10 hk 05/16/19 Clear status registers properly in reset 41 * </pre> 42 * 43 ******************************************************************************/ 44 45 #ifndef XEMACPS_HW_H /* prevent circular inclusions */ 46 #define XEMACPS_HW_H /* by using protection macros */ 47 48 /***************************** Include Files *********************************/ 49 50 #include "xil_types.h" 51 #include "xil_assert.h" 52 #include "xil_io.h" 53 54 #ifdef __cplusplus 55 extern "C" { 56 #endif 57 58 /************************** Constant Definitions *****************************/ 59 60 #define XEMACPS_MAX_MAC_ADDR 4U /**< Maxmum number of mac address 61 supported */ 62 #define XEMACPS_MAX_TYPE_ID 4U /**< Maxmum number of type id supported */ 63 64 #ifdef __aarch64__ 65 #define XEMACPS_BD_ALIGNMENT 64U /**< Minimum buffer descriptor alignment 66 on the local bus */ 67 #else 68 69 #define XEMACPS_BD_ALIGNMENT 4U /**< Minimum buffer descriptor alignment 70 on the local bus */ 71 #endif 72 #define XEMACPS_RX_BUF_ALIGNMENT 4U /**< Minimum buffer alignment when using 73 options that impose alignment 74 restrictions on the buffer data on 75 the local bus */ 76 77 /** @name Direction identifiers 78 * 79 * These are used by several functions and callbacks that need 80 * to specify whether an operation specifies a send or receive channel. 81 * @{ 82 */ 83 #define XEMACPS_SEND 1U /**< send direction */ 84 #define XEMACPS_RECV 2U /**< receive direction */ 85 /*@}*/ 86 87 /** @name MDC clock division 88 * currently supporting 8, 16, 32, 48, 64, 96, 128, 224. 89 * @{ 90 */ 91 typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48, 92 MDC_DIV_64, MDC_DIV_96, MDC_DIV_128, MDC_DIV_224 93 } XEmacPs_MdcDiv; 94 95 /*@}*/ 96 97 #define XEMACPS_RX_BUF_SIZE 1536U /**< Specify the receive buffer size in 98 bytes, 64, 128, ... 10240 */ 99 #define XEMACPS_RX_BUF_SIZE_JUMBO 10240U 100 101 #define XEMACPS_RX_BUF_UNIT 64U /**< Number of receive buffer bytes as a 102 unit, this is HW setup */ 103 104 #define XEMACPS_MAX_RXBD 128U /**< Size of RX buffer descriptor queues */ 105 #define XEMACPS_MAX_TXBD 128U /**< Size of TX buffer descriptor queues */ 106 107 #define XEMACPS_MAX_HASH_BITS 64U /**< Maximum value for hash bits. 2**6 */ 108 109 /* Register offset definitions. Unless otherwise noted, register access is 110 * 32 bit. Names are self explained here. 111 */ 112 113 #define XEMACPS_NWCTRL_OFFSET 0x00000000U /**< Network Control reg */ 114 #define XEMACPS_NWCFG_OFFSET 0x00000004U /**< Network Config reg */ 115 #define XEMACPS_NWSR_OFFSET 0x00000008U /**< Network Status reg */ 116 117 #define XEMACPS_DMACR_OFFSET 0x00000010U /**< DMA Control reg */ 118 #define XEMACPS_TXSR_OFFSET 0x00000014U /**< TX Status reg */ 119 #define XEMACPS_RXQBASE_OFFSET 0x00000018U /**< RX Q Base address reg */ 120 #define XEMACPS_TXQBASE_OFFSET 0x0000001CU /**< TX Q Base address reg */ 121 #define XEMACPS_RXSR_OFFSET 0x00000020U /**< RX Status reg */ 122 123 #define XEMACPS_ISR_OFFSET 0x00000024U /**< Interrupt Status reg */ 124 #define XEMACPS_IER_OFFSET 0x00000028U /**< Interrupt Enable reg */ 125 #define XEMACPS_IDR_OFFSET 0x0000002CU /**< Interrupt Disable reg */ 126 #define XEMACPS_IMR_OFFSET 0x00000030U /**< Interrupt Mask reg */ 127 128 #define XEMACPS_PHYMNTNC_OFFSET 0x00000034U /**< Phy Maintaince reg */ 129 #define XEMACPS_RXPAUSE_OFFSET 0x00000038U /**< RX Pause Time reg */ 130 #define XEMACPS_TXPAUSE_OFFSET 0x0000003CU /**< TX Pause Time reg */ 131 132 #define XEMACPS_JUMBOMAXLEN_OFFSET 0x00000048U /**< Jumbo max length reg */ 133 134 #define XEMACPS_RXWATERMARK_OFFSET 0x0000007CU /**< RX watermark reg */ 135 136 #define XEMACPS_HASHL_OFFSET 0x00000080U /**< Hash Low address reg */ 137 #define XEMACPS_HASHH_OFFSET 0x00000084U /**< Hash High address reg */ 138 139 #define XEMACPS_LADDR1L_OFFSET 0x00000088U /**< Specific1 addr low reg */ 140 #define XEMACPS_LADDR1H_OFFSET 0x0000008CU /**< Specific1 addr high reg */ 141 #define XEMACPS_LADDR2L_OFFSET 0x00000090U /**< Specific2 addr low reg */ 142 #define XEMACPS_LADDR2H_OFFSET 0x00000094U /**< Specific2 addr high reg */ 143 #define XEMACPS_LADDR3L_OFFSET 0x00000098U /**< Specific3 addr low reg */ 144 #define XEMACPS_LADDR3H_OFFSET 0x0000009CU /**< Specific3 addr high reg */ 145 #define XEMACPS_LADDR4L_OFFSET 0x000000A0U /**< Specific4 addr low reg */ 146 #define XEMACPS_LADDR4H_OFFSET 0x000000A4U /**< Specific4 addr high reg */ 147 148 #define XEMACPS_MATCH1_OFFSET 0x000000A8U /**< Type ID1 Match reg */ 149 #define XEMACPS_MATCH2_OFFSET 0x000000ACU /**< Type ID2 Match reg */ 150 #define XEMACPS_MATCH3_OFFSET 0x000000B0U /**< Type ID3 Match reg */ 151 #define XEMACPS_MATCH4_OFFSET 0x000000B4U /**< Type ID4 Match reg */ 152 153 #define XEMACPS_STRETCH_OFFSET 0x000000BCU /**< IPG Stretch reg */ 154 155 #define XEMACPS_OCTTXL_OFFSET 0x00000100U /**< Octects transmitted Low 156 reg */ 157 #define XEMACPS_OCTTXH_OFFSET 0x00000104U /**< Octects transmitted High 158 reg */ 159 160 #define XEMACPS_TXCNT_OFFSET 0x00000108U /**< Error-free Frmaes 161 transmitted counter */ 162 #define XEMACPS_TXBCCNT_OFFSET 0x0000010CU /**< Error-free Broadcast 163 Frames counter*/ 164 #define XEMACPS_TXMCCNT_OFFSET 0x00000110U /**< Error-free Multicast 165 Frame counter */ 166 #define XEMACPS_TXPAUSECNT_OFFSET 0x00000114U /**< Pause Frames Transmitted 167 Counter */ 168 #define XEMACPS_TX64CNT_OFFSET 0x00000118U /**< Error-free 64 byte Frames 169 Transmitted counter */ 170 #define XEMACPS_TX65CNT_OFFSET 0x0000011CU /**< Error-free 65-127 byte 171 Frames Transmitted 172 counter */ 173 #define XEMACPS_TX128CNT_OFFSET 0x00000120U /**< Error-free 128-255 byte 174 Frames Transmitted 175 counter*/ 176 #define XEMACPS_TX256CNT_OFFSET 0x00000124U /**< Error-free 256-511 byte 177 Frames transmitted 178 counter */ 179 #define XEMACPS_TX512CNT_OFFSET 0x00000128U /**< Error-free 512-1023 byte 180 Frames transmitted 181 counter */ 182 #define XEMACPS_TX1024CNT_OFFSET 0x0000012CU /**< Error-free 1024-1518 byte 183 Frames transmitted 184 counter */ 185 #define XEMACPS_TX1519CNT_OFFSET 0x00000130U /**< Error-free larger than 186 1519 byte Frames 187 transmitted counter */ 188 #define XEMACPS_TXURUNCNT_OFFSET 0x00000134U /**< TX under run error 189 counter */ 190 191 #define XEMACPS_SNGLCOLLCNT_OFFSET 0x00000138U /**< Single Collision Frame 192 Counter */ 193 #define XEMACPS_MULTICOLLCNT_OFFSET 0x0000013CU /**< Multiple Collision Frame 194 Counter */ 195 #define XEMACPS_EXCESSCOLLCNT_OFFSET 0x00000140U /**< Excessive Collision Frame 196 Counter */ 197 #define XEMACPS_LATECOLLCNT_OFFSET 0x00000144U /**< Late Collision Frame 198 Counter */ 199 #define XEMACPS_TXDEFERCNT_OFFSET 0x00000148U /**< Deferred Transmission 200 Frame Counter */ 201 #define XEMACPS_TXCSENSECNT_OFFSET 0x0000014CU /**< Transmit Carrier Sense 202 Error Counter */ 203 204 #define XEMACPS_OCTRXL_OFFSET 0x00000150U /**< Octects Received register 205 Low */ 206 #define XEMACPS_OCTRXH_OFFSET 0x00000154U /**< Octects Received register 207 High */ 208 209 #define XEMACPS_RXCNT_OFFSET 0x00000158U /**< Error-free Frames 210 Received Counter */ 211 #define XEMACPS_RXBROADCNT_OFFSET 0x0000015CU /**< Error-free Broadcast 212 Frames Received Counter */ 213 #define XEMACPS_RXMULTICNT_OFFSET 0x00000160U /**< Error-free Multicast 214 Frames Received Counter */ 215 #define XEMACPS_RXPAUSECNT_OFFSET 0x00000164U /**< Pause Frames 216 Received Counter */ 217 #define XEMACPS_RX64CNT_OFFSET 0x00000168U /**< Error-free 64 byte Frames 218 Received Counter */ 219 #define XEMACPS_RX65CNT_OFFSET 0x0000016CU /**< Error-free 65-127 byte 220 Frames Received Counter */ 221 #define XEMACPS_RX128CNT_OFFSET 0x00000170U /**< Error-free 128-255 byte 222 Frames Received Counter */ 223 #define XEMACPS_RX256CNT_OFFSET 0x00000174U /**< Error-free 256-512 byte 224 Frames Received Counter */ 225 #define XEMACPS_RX512CNT_OFFSET 0x00000178U /**< Error-free 512-1023 byte 226 Frames Received Counter */ 227 #define XEMACPS_RX1024CNT_OFFSET 0x0000017CU /**< Error-free 1024-1518 byte 228 Frames Received Counter */ 229 #define XEMACPS_RX1519CNT_OFFSET 0x00000180U /**< Error-free 1519-max byte 230 Frames Received Counter */ 231 #define XEMACPS_RXUNDRCNT_OFFSET 0x00000184U /**< Undersize Frames Received 232 Counter */ 233 #define XEMACPS_RXOVRCNT_OFFSET 0x00000188U /**< Oversize Frames Received 234 Counter */ 235 #define XEMACPS_RXJABCNT_OFFSET 0x0000018CU /**< Jabbers Received 236 Counter */ 237 #define XEMACPS_RXFCSCNT_OFFSET 0x00000190U /**< Frame Check Sequence 238 Error Counter */ 239 #define XEMACPS_RXLENGTHCNT_OFFSET 0x00000194U /**< Length Field Error 240 Counter */ 241 #define XEMACPS_RXSYMBCNT_OFFSET 0x00000198U /**< Symbol Error Counter */ 242 #define XEMACPS_RXALIGNCNT_OFFSET 0x0000019CU /**< Alignment Error Counter */ 243 #define XEMACPS_RXRESERRCNT_OFFSET 0x000001A0U /**< Receive Resource Error 244 Counter */ 245 #define XEMACPS_RXORCNT_OFFSET 0x000001A4U /**< Receive Overrun Counter */ 246 #define XEMACPS_RXIPCCNT_OFFSET 0x000001A8U /**< IP header Checksum Error 247 Counter */ 248 #define XEMACPS_RXTCPCCNT_OFFSET 0x000001ACU /**< TCP Checksum Error 249 Counter */ 250 #define XEMACPS_RXUDPCCNT_OFFSET 0x000001B0U /**< UDP Checksum Error 251 Counter */ 252 #define XEMACPS_LAST_OFFSET 0x000001B4U /**< Last statistic counter 253 offset, for clearing */ 254 255 #define XEMACPS_1588_SEC_OFFSET 0x000001D0U /**< 1588 second counter */ 256 #define XEMACPS_1588_NANOSEC_OFFSET 0x000001D4U /**< 1588 nanosecond counter */ 257 #define XEMACPS_1588_ADJ_OFFSET 0x000001D8U /**< 1588 nanosecond 258 adjustment counter */ 259 #define XEMACPS_1588_INC_OFFSET 0x000001DCU /**< 1588 nanosecond 260 increment counter */ 261 #define XEMACPS_PTP_TXSEC_OFFSET 0x000001E0U /**< 1588 PTP transmit second 262 counter */ 263 #define XEMACPS_PTP_TXNANOSEC_OFFSET 0x000001E4U /**< 1588 PTP transmit 264 nanosecond counter */ 265 #define XEMACPS_PTP_RXSEC_OFFSET 0x000001E8U /**< 1588 PTP receive second 266 counter */ 267 #define XEMACPS_PTP_RXNANOSEC_OFFSET 0x000001ECU /**< 1588 PTP receive 268 nanosecond counter */ 269 #define XEMACPS_PTPP_TXSEC_OFFSET 0x000001F0U /**< 1588 PTP peer transmit 270 second counter */ 271 #define XEMACPS_PTPP_TXNANOSEC_OFFSET 0x000001F4U /**< 1588 PTP peer transmit 272 nanosecond counter */ 273 #define XEMACPS_PTPP_RXSEC_OFFSET 0x000001F8U /**< 1588 PTP peer receive 274 second counter */ 275 #define XEMACPS_PTPP_RXNANOSEC_OFFSET 0x000001FCU /**< 1588 PTP peer receive 276 nanosecond counter */ 277 278 #define XEMACPS_INTQ1_STS_OFFSET 0x00000400U /**< Interrupt Q1 Status 279 reg */ 280 #define XEMACPS_TXQ1BASE_OFFSET 0x00000440U /**< TX Q1 Base address 281 reg */ 282 #define XEMACPS_RXQ1BASE_OFFSET 0x00000480U /**< RX Q1 Base address 283 reg */ 284 #define XEMACPS_MSBBUF_TXQBASE_OFFSET 0x000004C8U /**< MSB Buffer TX Q Base 285 reg */ 286 #define XEMACPS_MSBBUF_RXQBASE_OFFSET 0x000004D4U /**< MSB Buffer RX Q Base 287 reg */ 288 #define XEMACPS_INTQ1_IER_OFFSET 0x00000600U /**< Interrupt Q1 Enable 289 reg */ 290 #define XEMACPS_INTQ1_IDR_OFFSET 0x00000620U /**< Interrupt Q1 Disable 291 reg */ 292 #define XEMACPS_INTQ1_IMR_OFFSET 0x00000640U /**< Interrupt Q1 Mask 293 reg */ 294 295 /* Define some bit positions for registers. */ 296 297 /** @name network control register bit definitions 298 * @{ 299 */ 300 #define XEMACPS_NWCTRL_FLUSH_DPRAM_MASK 0x00040000U /**< Flush a packet from 301 Rx SRAM */ 302 #define XEMACPS_NWCTRL_ZEROPAUSETX_MASK 0x00000800U /**< Transmit zero quantum 303 pause frame */ 304 #define XEMACPS_NWCTRL_PAUSETX_MASK 0x00000800U /**< Transmit pause frame */ 305 #define XEMACPS_NWCTRL_HALTTX_MASK 0x00000400U /**< Halt transmission 306 after current frame */ 307 #define XEMACPS_NWCTRL_STARTTX_MASK 0x00000200U /**< Start tx (tx_go) */ 308 309 #define XEMACPS_NWCTRL_STATWEN_MASK 0x00000080U /**< Enable writing to 310 stat counters */ 311 #define XEMACPS_NWCTRL_STATINC_MASK 0x00000040U /**< Increment statistic 312 registers */ 313 #define XEMACPS_NWCTRL_STATCLR_MASK 0x00000020U /**< Clear statistic 314 registers */ 315 #define XEMACPS_NWCTRL_MDEN_MASK 0x00000010U /**< Enable MDIO port */ 316 #define XEMACPS_NWCTRL_TXEN_MASK 0x00000008U /**< Enable transmit */ 317 #define XEMACPS_NWCTRL_RXEN_MASK 0x00000004U /**< Enable receive */ 318 #define XEMACPS_NWCTRL_LOOPEN_MASK 0x00000002U /**< local loopback */ 319 /*@}*/ 320 321 /** @name network configuration register bit definitions 322 * @{ 323 */ 324 #define XEMACPS_NWCFG_BADPREAMBEN_MASK 0x20000000U /**< disable rejection of 325 non-standard preamble */ 326 #define XEMACPS_NWCFG_IPDSTRETCH_MASK 0x10000000U /**< enable transmit IPG */ 327 #define XEMACPS_NWCFG_SGMIIEN_MASK 0x08000000U /**< SGMII Enable */ 328 #define XEMACPS_NWCFG_FCSIGNORE_MASK 0x04000000U /**< disable rejection of 329 FCS error */ 330 #define XEMACPS_NWCFG_HDRXEN_MASK 0x02000000U /**< RX half duplex */ 331 #define XEMACPS_NWCFG_RXCHKSUMEN_MASK 0x01000000U /**< enable RX checksum 332 offload */ 333 #define XEMACPS_NWCFG_PAUSECOPYDI_MASK 0x00800000U /**< Do not copy pause 334 Frames to memory */ 335 #define XEMACPS_NWCFG_DWIDTH_64_MASK 0x00200000U /**< 64 bit Data bus width */ 336 #define XEMACPS_NWCFG_MDC_SHIFT_MASK 18U /**< shift bits for MDC */ 337 #define XEMACPS_NWCFG_MDCCLKDIV_MASK 0x001C0000U /**< MDC Mask PCLK divisor */ 338 #define XEMACPS_NWCFG_FCSREM_MASK 0x00020000U /**< Discard FCS from 339 received frames */ 340 #define XEMACPS_NWCFG_LENERRDSCRD_MASK 0x00010000U 341 /**< RX length error discard */ 342 #define XEMACPS_NWCFG_RXOFFS_MASK 0x0000C000U /**< RX buffer offset */ 343 #define XEMACPS_NWCFG_PAUSEEN_MASK 0x00002000U /**< Enable pause RX */ 344 #define XEMACPS_NWCFG_RETRYTESTEN_MASK 0x00001000U /**< Retry test */ 345 #define XEMACPS_NWCFG_XTADDMACHEN_MASK 0x00000200U 346 /**< External address match enable */ 347 #define XEMACPS_NWCFG_PCSSEL_MASK 0x00000800U /**< PCS Select */ 348 #define XEMACPS_NWCFG_1000_MASK 0x00000400U /**< 1000 Mbps */ 349 #define XEMACPS_NWCFG_1536RXEN_MASK 0x00000100U /**< Enable 1536 byte 350 frames reception */ 351 #define XEMACPS_NWCFG_UCASTHASHEN_MASK 0x00000080U /**< Receive unicast hash 352 frames */ 353 #define XEMACPS_NWCFG_MCASTHASHEN_MASK 0x00000040U /**< Receive multicast hash 354 frames */ 355 #define XEMACPS_NWCFG_BCASTDI_MASK 0x00000020U /**< Do not receive 356 broadcast frames */ 357 #define XEMACPS_NWCFG_COPYALLEN_MASK 0x00000010U /**< Copy all frames */ 358 #define XEMACPS_NWCFG_JUMBO_MASK 0x00000008U /**< Jumbo frames */ 359 #define XEMACPS_NWCFG_NVLANDISC_MASK 0x00000004U /**< Receive only VLAN 360 frames */ 361 #define XEMACPS_NWCFG_FDEN_MASK 0x00000002U/**< full duplex */ 362 #define XEMACPS_NWCFG_100_MASK 0x00000001U /**< 100 Mbps */ 363 #define XEMACPS_NWCFG_RESET_MASK 0x00080000U/**< reset value */ 364 /*@}*/ 365 366 /** @name network status register bit definitaions 367 * @{ 368 */ 369 #define XEMACPS_NWSR_MDIOIDLE_MASK 0x00000004U /**< PHY management idle */ 370 #define XEMACPS_NWSR_MDIO_MASK 0x00000002U /**< Status of mdio_in */ 371 /*@}*/ 372 373 374 /** @name MAC address register word 1 mask 375 * @{ 376 */ 377 #define XEMACPS_LADDR_MACH_MASK 0x0000FFFFU /**< Address bits[47:32] 378 bit[31:0] are in BOTTOM */ 379 /*@}*/ 380 381 382 /** @name DMA control register bit definitions 383 * @{ 384 */ 385 #define XEMACPS_DMACR_ADDR_WIDTH_64 0x40000000U /**< 64 bit address bus */ 386 #define XEMACPS_DMACR_TXEXTEND_MASK 0x20000000U /**< Tx Extended desc mode */ 387 #define XEMACPS_DMACR_RXEXTEND_MASK 0x10000000U /**< Rx Extended desc mode */ 388 #define XEMACPS_DMACR_RXBUF_MASK 0x00FF0000U /**< Mask bit for RX buffer 389 size */ 390 #define XEMACPS_DMACR_RXBUF_SHIFT 16U /**< Shift bit for RX buffer 391 size */ 392 #define XEMACPS_DMACR_TCPCKSUM_MASK 0x00000800U /**< enable/disable TX 393 checksum offload */ 394 #define XEMACPS_DMACR_TXSIZE_MASK 0x00000400U /**< TX buffer memory size */ 395 #define XEMACPS_DMACR_RXSIZE_MASK 0x00000300U /**< RX buffer memory size */ 396 #define XEMACPS_DMACR_ENDIAN_MASK 0x00000080U /**< endian configuration */ 397 #define XEMACPS_DMACR_BLENGTH_MASK 0x0000001FU /**< buffer burst length */ 398 #define XEMACPS_DMACR_SINGLE_AHB_BURST 0x00000001U /**< single AHB bursts */ 399 #define XEMACPS_DMACR_INCR4_AHB_BURST 0x00000004U /**< 4 bytes AHB bursts */ 400 #define XEMACPS_DMACR_INCR8_AHB_BURST 0x00000008U /**< 8 bytes AHB bursts */ 401 #define XEMACPS_DMACR_INCR16_AHB_BURST 0x00000010U /**< 16 bytes AHB bursts */ 402 /*@}*/ 403 404 /** @name transmit status register bit definitions 405 * @{ 406 */ 407 #define XEMACPS_TXSR_HRESPNOK_MASK 0x00000100U /**< Transmit hresp not OK */ 408 #define XEMACPS_TXSR_URUN_MASK 0x00000040U /**< Transmit underrun */ 409 #define XEMACPS_TXSR_TXCOMPL_MASK 0x00000020U /**< Transmit completed OK */ 410 #define XEMACPS_TXSR_BUFEXH_MASK 0x00000010U /**< Transmit buffs exhausted 411 mid frame */ 412 #define XEMACPS_TXSR_TXGO_MASK 0x00000008U /**< Status of go flag */ 413 #define XEMACPS_TXSR_RXOVR_MASK 0x00000004U /**< Retry limit exceeded */ 414 #define XEMACPS_TXSR_FRAMERX_MASK 0x00000002U /**< Collision tx frame */ 415 #define XEMACPS_TXSR_USEDREAD_MASK 0x00000001U /**< TX buffer used bit set */ 416 417 #define XEMACPS_TXSR_ERROR_MASK ((u32)XEMACPS_TXSR_HRESPNOK_MASK | \ 418 (u32)XEMACPS_TXSR_URUN_MASK | \ 419 (u32)XEMACPS_TXSR_BUFEXH_MASK | \ 420 (u32)XEMACPS_TXSR_RXOVR_MASK | \ 421 (u32)XEMACPS_TXSR_FRAMERX_MASK | \ 422 (u32)XEMACPS_TXSR_USEDREAD_MASK) 423 /*@}*/ 424 425 /** 426 * @name receive status register bit definitions 427 * @{ 428 */ 429 #define XEMACPS_RXSR_HRESPNOK_MASK 0x00000008U /**< Receive hresp not OK */ 430 #define XEMACPS_RXSR_RXOVR_MASK 0x00000004U /**< Receive overrun */ 431 #define XEMACPS_RXSR_FRAMERX_MASK 0x00000002U /**< Frame received OK */ 432 #define XEMACPS_RXSR_BUFFNA_MASK 0x00000001U /**< RX buffer used bit set */ 433 434 #define XEMACPS_RXSR_ERROR_MASK ((u32)XEMACPS_RXSR_HRESPNOK_MASK | \ 435 (u32)XEMACPS_RXSR_RXOVR_MASK | \ 436 (u32)XEMACPS_RXSR_BUFFNA_MASK) 437 438 #define XEMACPS_SR_ALL_MASK 0xFFFFFFFFU /**< Mask for full register */ 439 440 /*@}*/ 441 442 /** 443 * @name Interrupt Q1 status register bit definitions 444 * @{ 445 */ 446 #define XEMACPS_INTQ1SR_TXCOMPL_MASK 0x00000080U /**< Transmit completed OK */ 447 #define XEMACPS_INTQ1SR_TXERR_MASK 0x00000040U /**< Transmit AMBA Error */ 448 449 #define XEMACPS_INTQ1_IXR_ALL_MASK ((u32)XEMACPS_INTQ1SR_TXCOMPL_MASK | \ 450 (u32)XEMACPS_INTQ1SR_TXERR_MASK) 451 452 /*@}*/ 453 454 /** 455 * @name interrupts bit definitions 456 * Bits definitions are same in XEMACPS_ISR_OFFSET, 457 * XEMACPS_IER_OFFSET, XEMACPS_IDR_OFFSET, and XEMACPS_IMR_OFFSET 458 * @{ 459 */ 460 #define XEMACPS_IXR_PTPPSTX_MASK 0x02000000U /**< PTP Pdelay_resp TXed */ 461 #define XEMACPS_IXR_PTPPDRTX_MASK 0x01000000U /**< PTP Pdelay_req TXed */ 462 #define XEMACPS_IXR_PTPPSRX_MASK 0x00800000U /**< PTP Pdelay_resp RXed */ 463 #define XEMACPS_IXR_PTPPDRRX_MASK 0x00400000U /**< PTP Pdelay_req RXed */ 464 465 #define XEMACPS_IXR_PTPSTX_MASK 0x00200000U /**< PTP Sync TXed */ 466 #define XEMACPS_IXR_PTPDRTX_MASK 0x00100000U /**< PTP Delay_req TXed */ 467 #define XEMACPS_IXR_PTPSRX_MASK 0x00080000U /**< PTP Sync RXed */ 468 #define XEMACPS_IXR_PTPDRRX_MASK 0x00040000U /**< PTP Delay_req RXed */ 469 470 #define XEMACPS_IXR_PAUSETX_MASK 0x00004000U /**< Pause frame transmitted */ 471 #define XEMACPS_IXR_PAUSEZERO_MASK 0x00002000U /**< Pause time has reached 472 zero */ 473 #define XEMACPS_IXR_PAUSENZERO_MASK 0x00001000U /**< Pause frame received */ 474 #define XEMACPS_IXR_HRESPNOK_MASK 0x00000800U /**< hresp not ok */ 475 #define XEMACPS_IXR_RXOVR_MASK 0x00000400U /**< Receive overrun occurred */ 476 #define XEMACPS_IXR_TXCOMPL_MASK 0x00000080U /**< Frame transmitted ok */ 477 #define XEMACPS_IXR_TXEXH_MASK 0x00000040U /**< Transmit err occurred or 478 no buffers*/ 479 #define XEMACPS_IXR_RETRY_MASK 0x00000020U /**< Retry limit exceeded */ 480 #define XEMACPS_IXR_URUN_MASK 0x00000010U /**< Transmit underrun */ 481 #define XEMACPS_IXR_TXUSED_MASK 0x00000008U /**< Tx buffer used bit read */ 482 #define XEMACPS_IXR_RXUSED_MASK 0x00000004U /**< Rx buffer used bit read */ 483 #define XEMACPS_IXR_FRAMERX_MASK 0x00000002U /**< Frame received ok */ 484 #define XEMACPS_IXR_MGMNT_MASK 0x00000001U /**< PHY management complete */ 485 #define XEMACPS_IXR_ALL_MASK 0x00007FFFU /**< Everything! */ 486 487 #define XEMACPS_IXR_TX_ERR_MASK ((u32)XEMACPS_IXR_TXEXH_MASK | \ 488 (u32)XEMACPS_IXR_RETRY_MASK | \ 489 (u32)XEMACPS_IXR_URUN_MASK) 490 491 492 #define XEMACPS_IXR_RX_ERR_MASK ((u32)XEMACPS_IXR_HRESPNOK_MASK | \ 493 (u32)XEMACPS_IXR_RXUSED_MASK | \ 494 (u32)XEMACPS_IXR_RXOVR_MASK) 495 496 /*@}*/ 497 498 /** @name PHY Maintenance bit definitions 499 * @{ 500 */ 501 #define XEMACPS_PHYMNTNC_OP_MASK 0x40020000U /**< operation mask bits */ 502 #define XEMACPS_PHYMNTNC_OP_R_MASK 0x20000000U /**< read operation */ 503 #define XEMACPS_PHYMNTNC_OP_W_MASK 0x10000000U /**< write operation */ 504 #define XEMACPS_PHYMNTNC_ADDR_MASK 0x0F800000U /**< Address bits */ 505 #define XEMACPS_PHYMNTNC_REG_MASK 0x007C0000U /**< register bits */ 506 #define XEMACPS_PHYMNTNC_DATA_MASK 0x00000FFFU /**< data bits */ 507 #define XEMACPS_PHYMNTNC_PHAD_SHFT_MSK 23U /**< Shift bits for PHYAD */ 508 #define XEMACPS_PHYMNTNC_PREG_SHFT_MSK 18U /**< Shift bits for PHREG */ 509 /*@}*/ 510 511 /** @name RX watermark bit definitions 512 * @{ 513 */ 514 #define XEMACPS_RXWM_HIGH_MASK 0x0000FFFFU /**< RXWM high mask */ 515 #define XEMACPS_RXWM_LOW_MASK 0xFFFF0000U /**< RXWM low mask */ 516 #define XEMACPS_RXWM_LOW_SHFT_MSK 16U /**< Shift for RXWM low */ 517 /*@}*/ 518 519 /* Transmit buffer descriptor status words offset 520 * @{ 521 */ 522 #define XEMACPS_BD_ADDR_OFFSET 0x00000000U /**< word 0/addr of BDs */ 523 #define XEMACPS_BD_STAT_OFFSET 0x00000004U /**< word 1/status of BDs */ 524 #define XEMACPS_BD_ADDR_HI_OFFSET 0x00000008U /**< word 2/addr of BDs */ 525 526 /* 527 * @} 528 */ 529 530 /* Transmit buffer descriptor status words bit positions. 531 * Transmit buffer descriptor consists of two 32-bit registers, 532 * the first - word0 contains a 32-bit address pointing to the location of 533 * the transmit data. 534 * The following register - word1, consists of various information to control 535 * the XEmacPs transmit process. After transmit, this is updated with status 536 * information, whether the frame was transmitted OK or why it had failed. 537 * @{ 538 */ 539 #define XEMACPS_TXBUF_USED_MASK 0x80000000U /**< Used bit. */ 540 #define XEMACPS_TXBUF_WRAP_MASK 0x40000000U /**< Wrap bit, last descriptor */ 541 #define XEMACPS_TXBUF_RETRY_MASK 0x20000000U /**< Retry limit exceeded */ 542 #define XEMACPS_TXBUF_URUN_MASK 0x10000000U /**< Transmit underrun occurred */ 543 #define XEMACPS_TXBUF_EXH_MASK 0x08000000U /**< Buffers exhausted */ 544 #define XEMACPS_TXBUF_TCP_MASK 0x04000000U /**< Late collision. */ 545 #define XEMACPS_TXBUF_NOCRC_MASK 0x00010000U /**< No CRC */ 546 #define XEMACPS_TXBUF_LAST_MASK 0x00008000U /**< Last buffer */ 547 #define XEMACPS_TXBUF_LEN_MASK 0x00003FFFU /**< Mask for length field */ 548 /* 549 * @} 550 */ 551 552 /* Receive buffer descriptor status words bit positions. 553 * Receive buffer descriptor consists of two 32-bit registers, 554 * the first - word0 contains a 32-bit word aligned address pointing to the 555 * address of the buffer. The lower two bits make up the wrap bit indicating 556 * the last descriptor and the ownership bit to indicate it has been used by 557 * the XEmacPs. 558 * The following register - word1, contains status information regarding why 559 * the frame was received (the filter match condition) as well as other 560 * useful info. 561 * @{ 562 */ 563 #define XEMACPS_RXBUF_BCAST_MASK 0x80000000U /**< Broadcast frame */ 564 #define XEMACPS_RXBUF_MULTIHASH_MASK 0x40000000U /**< Multicast hashed frame */ 565 #define XEMACPS_RXBUF_UNIHASH_MASK 0x20000000U /**< Unicast hashed frame */ 566 #define XEMACPS_RXBUF_EXH_MASK 0x08000000U /**< buffer exhausted */ 567 #define XEMACPS_RXBUF_AMATCH_MASK 0x06000000U /**< Specific address 568 matched */ 569 #define XEMACPS_RXBUF_IDFOUND_MASK 0x01000000U /**< Type ID matched */ 570 #define XEMACPS_RXBUF_IDMATCH_MASK 0x00C00000U /**< ID matched mask */ 571 #define XEMACPS_RXBUF_VLAN_MASK 0x00200000U /**< VLAN tagged */ 572 #define XEMACPS_RXBUF_PRI_MASK 0x00100000U /**< Priority tagged */ 573 #define XEMACPS_RXBUF_VPRI_MASK 0x000E0000U /**< Vlan priority */ 574 #define XEMACPS_RXBUF_CFI_MASK 0x00010000U /**< CFI frame */ 575 #define XEMACPS_RXBUF_EOF_MASK 0x00008000U /**< End of frame. */ 576 #define XEMACPS_RXBUF_SOF_MASK 0x00004000U /**< Start of frame. */ 577 #define XEMACPS_RXBUF_LEN_MASK 0x00001FFFU /**< Mask for length field */ 578 #define XEMACPS_RXBUF_LEN_JUMBO_MASK 0x00003FFFU /**< Mask for jumbo length */ 579 580 #define XEMACPS_RXBUF_WRAP_MASK 0x00000002U /**< Wrap bit, last BD */ 581 #define XEMACPS_RXBUF_NEW_MASK 0x00000001U /**< Used bit.. */ 582 #define XEMACPS_RXBUF_ADD_MASK 0xFFFFFFFCU /**< Mask for address */ 583 /* 584 * @} 585 */ 586 587 /* 588 * Define appropriate I/O access method to memory mapped I/O or other 589 * interface if necessary. 590 */ 591 592 #define XEmacPs_In32 Xil_In32 593 #define XEmacPs_Out32 Xil_Out32 594 595 596 /****************************************************************************/ 597 /** 598 * 599 * Read the given register. 600 * 601 * @param BaseAddress is the base address of the device 602 * @param RegOffset is the register offset to be read 603 * 604 * @return The 32-bit value of the register 605 * 606 * @note 607 * C-style signature: 608 * u32 XEmacPs_ReadReg(u32 BaseAddress, u32 RegOffset) 609 * 610 *****************************************************************************/ 611 #define XEmacPs_ReadReg(BaseAddress, RegOffset) \ 612 XEmacPs_In32((BaseAddress) + (u32)(RegOffset)) 613 614 615 /****************************************************************************/ 616 /** 617 * 618 * Write the given register. 619 * 620 * @param BaseAddress is the base address of the device 621 * @param RegOffset is the register offset to be written 622 * @param Data is the 32-bit value to write to the register 623 * 624 * @return None. 625 * 626 * @note 627 * C-style signature: 628 * void XEmacPs_WriteReg(u32 BaseAddress, u32 RegOffset, 629 * u32 Data) 630 * 631 *****************************************************************************/ 632 #define XEmacPs_WriteReg(BaseAddress, RegOffset, Data) \ 633 XEmacPs_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data)) 634 635 /************************** Function Prototypes *****************************/ 636 /* 637 * Perform reset operation to the emacps interface 638 */ 639 void XEmacPs_ResetHw(u32 BaseAddr); 640 641 #ifdef __cplusplus 642 } 643 #endif 644 645 #endif /* end of protection macro */ 646 /** @} */ 647