1 /****************************************************************************** 2 * Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 ******************************************************************************/ 5 6 /****************************************************************************/ 7 /** 8 * 9 * @file xemacps.h 10 * @addtogroup emacps_v3_11 11 * @{ 12 * @details 13 * 14 * The Xilinx Embedded Processor Block Ethernet driver. 15 * 16 * For a full description of XEMACPS features, please see the hardware spec. 17 * This driver supports the following features: 18 * - Memory mapped access to host interface registers 19 * - Statistics counter registers for RMON/MIB 20 * - API for interrupt driven frame transfers for hardware configured DMA 21 * - Virtual memory support 22 * - Unicast, broadcast, and multicast receive address filtering 23 * - Full and half duplex operation 24 * - Automatic PAD & FCS insertion and stripping 25 * - Flow control 26 * - Support up to four 48bit addresses 27 * - Address checking for four specific 48bit addresses 28 * - VLAN frame support 29 * - Pause frame support 30 * - Large frame support up to 1536 bytes 31 * - Checksum offload 32 * 33 * <b>Driver Description</b> 34 * 35 * The device driver enables higher layer software (e.g., an application) to 36 * communicate to the XEmacPs. The driver handles transmission and reception 37 * of Ethernet frames, as well as configuration and control. No pre or post 38 * processing of frame data is performed. The driver does not validate the 39 * contents of an incoming frame in addition to what has already occurred in 40 * hardware. 41 * A single device driver can support multiple devices even when those devices 42 * have significantly different configurations. 43 * 44 * <b>Initialization & Configuration</b> 45 * 46 * The XEmacPs_Config structure is used by the driver to configure itself. 47 * This configuration structure is typically created by the tool-chain based 48 * on hardware build properties. 49 * 50 * The driver instance can be initialized in 51 * 52 * - XEmacPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddress): Uses a 53 * configuration structure provided by the caller. If running in a system 54 * with address translation, the provided virtual memory base address 55 * replaces the physical address present in the configuration structure. 56 * 57 * The device supports DMA only as current development plan. No FIFO mode is 58 * supported. The driver expects to start the DMA channels and expects that 59 * the user has set up the buffer descriptor lists. 60 * 61 * <b>Interrupts and Asynchronous Callbacks</b> 62 * 63 * The driver has no dependencies on the interrupt controller. When an 64 * interrupt occurs, the handler will perform a small amount of 65 * housekeeping work, determine the source of the interrupt, and call the 66 * appropriate callback function. All callbacks are registered by the user 67 * level application. 68 * 69 * <b>Virtual Memory</b> 70 * 71 * All virtual to physical memory mappings must occur prior to accessing the 72 * driver API. 73 * 74 * For DMA transactions, user buffers supplied to the driver must be in terms 75 * of their physical address. 76 * 77 * <b>DMA</b> 78 * 79 * The DMA engine uses buffer descriptors (BDs) to describe Ethernet frames. 80 * These BDs are typically chained together into a list the hardware follows 81 * when transferring data in and out of the packet buffers. Each BD describes 82 * a memory region containing either a full or partial Ethernet packet. 83 * 84 * Interrupt coalescing is not supported from this built-in DMA engine. 85 * 86 * This API requires the user to understand how the DMA operates. The 87 * following paragraphs provide some explanation, but the user is encouraged 88 * to read documentation in xemacps_bdring.h as well as study example code 89 * that accompanies this driver. 90 * 91 * The API is designed to get BDs to and from the DMA engine in the most 92 * efficient means possible. The first step is to establish a memory region 93 * to contain all BDs for a specific channel. This is done with 94 * XEmacPs_BdRingCreate(). This function sets up a BD ring that hardware will 95 * follow as BDs are processed. The ring will consist of a user defined number 96 * of BDs which will all be partially initialized. For example on the transmit 97 * channel, the driver will initialize all BDs' so that they are configured 98 * for transmit. The more fields that can be permanently setup at 99 * initialization, then the fewer accesses will be needed to each BD while 100 * the DMA engine is in operation resulting in better throughput and CPU 101 * utilization. The best case initialization would require the user to set 102 * only a frame buffer address and length prior to submitting the BD to the 103 * engine. 104 * 105 * BDs move through the engine with the help of functions 106 * XEmacPs_BdRingAlloc(), XEmacPs_BdRingToHw(), XEmacPs_BdRingFromHw(), 107 * and XEmacPs_BdRingFree(). 108 * All these functions handle BDs that are in place. That is, there are no 109 * copies of BDs kept anywhere and any BD the user interacts with is an actual 110 * BD from the same ring hardware accesses. 111 * 112 * BDs in the ring go through a series of states as follows: 113 * 1. Idle. The driver controls BDs in this state. 114 * 2. The user has data to transfer. XEmacPs_BdRingAlloc() is called to 115 * reserve BD(s). Once allocated, the user may setup the BD(s) with 116 * frame buffer address, length, and other attributes. The user controls 117 * BDs in this state. 118 * 3. The user submits BDs to the DMA engine with XEmacPs_BdRingToHw. BDs 119 * in this state are either waiting to be processed by hardware, are in 120 * process, or have been processed. The DMA engine controls BDs in this 121 * state. 122 * 4. Processed BDs are retrieved with XEmacEpv_BdRingFromHw() by the 123 * user. Once retrieved, the user can examine each BD for the outcome of 124 * the DMA transfer. The user controls BDs in this state. After examining 125 * the BDs the user calls XEmacPs_BdRingFree() which places the BDs back 126 * into state 1. 127 * 128 * Each of the four BD accessor functions operate on a set of BDs. A set is 129 * defined as a segment of the BD ring consisting of one or more BDs. The user 130 * views the set as a pointer to the first BD along with the number of BDs for 131 * that set. The set can be navigated by using macros XEmacPs_BdNext(). The 132 * user must exercise extreme caution when changing BDs in a set as there is 133 * nothing to prevent doing a mBdNext past the end of the set and modifying a 134 * BD out of bounds. 135 * 136 * XEmacPs_BdRingAlloc() + XEmacPs_BdRingToHw(), as well as 137 * XEmacPs_BdRingFromHw() + XEmacPs_BdRingFree() are designed to be used in 138 * tandem. The same BD set retrieved with BdRingAlloc should be the same one 139 * provided to hardware with BdRingToHw. Same goes with BdRingFromHw and 140 * BdRIngFree. 141 * 142 * <b>Alignment & Data Cache Restrictions</b> 143 * 144 * Due to the design of the hardware, all RX buffers, BDs need to be 4-byte 145 * aligned. Please reference xemacps_bd.h for cache related macros. 146 * 147 * DMA Tx: 148 * 149 * - If frame buffers exist in cached memory, then they must be flushed 150 * prior to committing them to hardware. 151 * 152 * DMA Rx: 153 * 154 * - If frame buffers exist in cached memory, then the cache must be 155 * invalidated for the memory region containing the frame prior to data 156 * access 157 * 158 * Both cache invalidate/flush are taken care of in driver code. 159 * 160 * <b>Buffer Copying</b> 161 * 162 * The driver is designed for a zero-copy buffer scheme. That is, the driver 163 * will not copy buffers. This avoids potential throughput bottlenecks within 164 * the driver. If byte copying is required, then the transfer will take longer 165 * to complete. 166 * 167 * <b>Checksum Offloading</b> 168 * 169 * The Embedded Processor Block Ethernet can be configured to perform IP, TCP 170 * and UDP checksum offloading in both receive and transmit directions. 171 * 172 * IP packets contain a 16-bit checksum field, which is the 16-bit 1s 173 * complement of the 1s complement sum of all 16-bit words in the header. 174 * TCP and UDP packets contain a 16-bit checksum field, which is the 16-bit 175 * 1s complement of the 1s complement sum of all 16-bit words in the header, 176 * the data and a conceptual pseudo header. 177 * 178 * To calculate these checksums in software requires each byte of the packet 179 * to be read. For TCP and UDP this can use a large amount of processing power. 180 * Offloading the checksum calculation to hardware can result in significant 181 * performance improvements. 182 * 183 * The transmit checksum offload is only available to use DMA in packet buffer 184 * mode. This is because the complete frame to be transmitted must be read 185 * into the packet buffer memory before the checksum can be calculated and 186 * written to the header at the beginning of the frame. 187 * 188 * For IP, TCP or UDP receive checksum offload to be useful, the operating 189 * system containing the protocol stack must be aware that this offload is 190 * available so that it can make use of the fact that the hardware has verified 191 * the checksum. 192 * 193 * When receive checksum offloading is enabled in the hardware, the IP header 194 * checksum is checked, where the packet meets the following criteria: 195 * 196 * 1. If present, the VLAN header must be four octets long and the CFI bit 197 * must not be set. 198 * 2. Encapsulation must be RFC 894 Ethernet Type Encoding or RFC 1042 SNAP 199 * encoding. 200 * 3. IP v4 packet. 201 * 4. IP header is of a valid length. 202 * 5. Good IP header checksum. 203 * 6. No IP fragmentation. 204 * 7. TCP or UDP packet. 205 * 206 * When an IP, TCP or UDP frame is received, the receive buffer descriptor 207 * gives an indication if the hardware was able to verify the checksums. 208 * There is also an indication if the frame had SNAP encapsulation. These 209 * indication bits will replace the type ID match indication bits when the 210 * receive checksum offload is enabled. 211 * 212 * If any of the checksums are verified incorrect by the hardware, the packet 213 * is discarded and the appropriate statistics counter incremented. 214 * 215 * <b>PHY Interfaces</b> 216 * 217 * RGMII 1.3 is the only interface supported. 218 * 219 * <b>Asserts</b> 220 * 221 * Asserts are used within all Xilinx drivers to enforce constraints on 222 * parameters. Asserts can be turned off on a system-wide basis by defining, 223 * at compile time, the NDEBUG identifier. By default, asserts are turned on 224 * and it is recommended that users leave asserts on during development. For 225 * deployment use -DNDEBUG compiler switch to remove assert code. 226 * 227 * @note 228 * 229 * Xilinx drivers are typically composed of two parts, one is the driver 230 * and the other is the adapter. The driver is independent of OS and processor 231 * and is intended to be highly portable. The adapter is OS-specific and 232 * facilitates communication between the driver and an OS. 233 * This driver is intended to be RTOS and processor independent. Any needs for 234 * dynamic memory management, threads or thread mutual exclusion, or cache 235 * control must be satisfied bythe layer above this driver. 236 * 237 * <pre> 238 * MODIFICATION HISTORY: 239 * 240 * Ver Who Date Changes 241 * ----- ---- -------- ------------------------------------------------------- 242 * 1.00a wsy 01/10/10 First release 243 * 1.00a asa 11/21/11 The function XEmacPs_BdRingFromHwTx in file 244 * xemacps_bdring.c is modified. Earlier it was checking for 245 * "BdLimit"(passed argument) number of BDs for finding out 246 * which BDs are successfully processed. Now one more check 247 * is added. It looks for BDs till the current BD pointer 248 * reaches HwTail. By doing this processing time is saved. 249 * 1.00a asa 01/24/12 The function XEmacPs_BdRingFromHwTx in file 250 * xemacps_bdring.c is modified. Now start of packet is 251 * searched for returning the number of BDs processed. 252 * 1.02a asa 11/05/12 Added a new API for deleting an entry from the HASH 253 * registers. Added a new API to set the bust length. 254 * Added some new hash-defines. 255 * 1.03a asa 01/23/12 Fix for CR #692702 which updates error handling for 256 * Rx errors. Under heavy Rx traffic, there will be a large 257 * number of errors related to receive buffer not available. 258 * Because of a HW bug (SI #692601), under such heavy errors, 259 * the Rx data path can become unresponsive. To reduce the 260 * probabilities for hitting this HW bug, the SW writes to 261 * bit 18 to flush a packet from Rx DPRAM immediately. The 262 * changes for it are done in the function 263 * XEmacPs_IntrHandler. 264 * 1.05a asa 09/23/13 Cache operations on BDs are not required and hence 265 * removed. It is expected that all BDs are allocated in 266 * from uncached area. 267 * 1.06a asa 11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff 268 * to 0x1fff. This fixes the CR#744902. 269 * Made changes in example file xemacps_example.h to fix compilation 270 * issues with iarcc compiler. 271 * 2.0 adk 10/12/13 Updated as per the New Tcl API's 272 * 2.1 adk 11/08/14 Fixed the CR#811288. Changes are made in the driver tcl file. 273 * 2.1 bss 09/08/14 Modified driver tcl to fix CR#820349 to export phy 274 * address in xparameters.h when GMII to RGMII converter 275 * is present in hw. 276 * 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp GEM specification and 64-bit 277 * changes. 278 * 2.2 adk 29/10/14 Fixed CR#827686 when PCS/PMA core is configured with 279 * 1000BASE-X mode export proper values to the xparameters.h 280 * file. Changes are made in the driver tcl file. 281 * 3.0 adk 08/1/15 Don't include gem in peripheral test when gem is 282 * configured with PCS/PMA Core. Changes are made in the 283 * test app tcl(CR:827686). 284 * 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance. 285 * 3.0 hk 03/18/15 Added support for jumbo frames. Increase AHB burst. 286 * Disable extended mode. Perform all 64 bit changes under 287 * check for arch64. 288 * Remove "used bit set" from TX error interrupt masks. 289 * 3.1 hk 07/27/15 Do not call error handler with '0' error code when 290 * there is no error. CR# 869403 291 * 08/10/15 Update upper 32 bit tx and rx queue ptr registers. 292 * 3.2 hk 02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC. 293 * 3.4 ms 01/23/17 Modified xil_printf statement in main function for all 294 * examples to ensure that "Successfully ran" and "Failed" 295 * strings are available in all examples. This is a fix 296 * for CR-965028. 297 * ms 03/17/17 Modified text file in examples folder for doxygen 298 * generation. 299 * ms 04/05/17 Added tabspace for return statements in functions of 300 * xemacps_ieee1588_example.c for proper documentation 301 * while generating doxygen. 302 * 3.5 hk 08/14/17 Update cache coherency information of the interface in 303 * its config structure. 304 * 3.6 rb 09/08/17 HwCnt variable (in XEmacPs_BdRing structure) is 305 * changed to volatile. 306 * Add API XEmacPs_BdRingPtrReset() to reset pointers 307 * 3.8 hk 07/19/18 Fixed CPP, GCC and doxygen warnings - CR-1006327 308 * hk 09/17/18 Fix PTP interrupt masks and cleanup comments. 309 * 3.9 hk 01/23/19 Add RX watermark support 310 * 3.11 sd 02/14/20 Add clock support 311 * 312 * </pre> 313 * 314 ****************************************************************************/ 315 316 #ifndef XEMACPS_H /* prevent circular inclusions */ 317 #define XEMACPS_H /* by using protection macros */ 318 319 #ifdef __cplusplus 320 extern "C" { 321 #endif 322 323 /***************************** Include Files ********************************/ 324 325 #include "xil_types.h" 326 #include "xil_assert.h" 327 #include "xstatus.h" 328 #include "xemacps_hw.h" 329 #include "xemacps_bd.h" 330 #include "xemacps_bdring.h" 331 #if defined (XCLOCKING) 332 #include "xil_clocking.h" 333 #endif 334 335 /************************** Constant Definitions ****************************/ 336 337 /* 338 * Device information 339 */ 340 #define XEMACPS_DEVICE_NAME "xemacps" 341 #define XEMACPS_DEVICE_DESC "Xilinx PS 10/100/1000 MAC" 342 343 344 /** @name Configuration options 345 * 346 * Device configuration options. See the XEmacPs_SetOptions(), 347 * XEmacPs_ClearOptions() and XEmacPs_GetOptions() for information on how to 348 * use options. 349 * 350 * The default state of the options are noted and are what the device and 351 * driver will be set to after calling XEmacPs_Reset() or 352 * XEmacPs_Initialize(). 353 * 354 * @{ 355 */ 356 357 #define XEMACPS_PROMISC_OPTION 0x00000001U 358 /**< Accept all incoming packets. 359 * This option defaults to disabled (cleared) */ 360 361 #define XEMACPS_FRAME1536_OPTION 0x00000002U 362 /**< Frame larger than 1516 support for Tx & Rx. 363 * This option defaults to disabled (cleared) */ 364 365 #define XEMACPS_VLAN_OPTION 0x00000004U 366 /**< VLAN Rx & Tx frame support. 367 * This option defaults to disabled (cleared) */ 368 369 #define XEMACPS_FLOW_CONTROL_OPTION 0x00000010U 370 /**< Enable recognition of flow control frames on Rx 371 * This option defaults to enabled (set) */ 372 373 #define XEMACPS_FCS_STRIP_OPTION 0x00000020U 374 /**< Strip FCS and PAD from incoming frames. Note: PAD from VLAN frames is not 375 * stripped. 376 * This option defaults to enabled (set) */ 377 378 #define XEMACPS_FCS_INSERT_OPTION 0x00000040U 379 /**< Generate FCS field and add PAD automatically for outgoing frames. 380 * This option defaults to disabled (cleared) */ 381 382 #define XEMACPS_LENTYPE_ERR_OPTION 0x00000080U 383 /**< Enable Length/Type error checking for incoming frames. When this option is 384 * set, the MAC will filter frames that have a mismatched type/length field 385 * and if XEMACPS_REPORT_RXERR_OPTION is set, the user is notified when these 386 * types of frames are encountered. When this option is cleared, the MAC will 387 * allow these types of frames to be received. 388 * 389 * This option defaults to disabled (cleared) */ 390 391 #define XEMACPS_TRANSMITTER_ENABLE_OPTION 0x00000100U 392 /**< Enable the transmitter. 393 * This option defaults to enabled (set) */ 394 395 #define XEMACPS_RECEIVER_ENABLE_OPTION 0x00000200U 396 /**< Enable the receiver 397 * This option defaults to enabled (set) */ 398 399 #define XEMACPS_BROADCAST_OPTION 0x00000400U 400 /**< Allow reception of the broadcast address 401 * This option defaults to enabled (set) */ 402 403 #define XEMACPS_MULTICAST_OPTION 0x00000800U 404 /**< Allows reception of multicast addresses programmed into hash 405 * This option defaults to disabled (clear) */ 406 407 #define XEMACPS_RX_CHKSUM_ENABLE_OPTION 0x00001000U 408 /**< Enable the RX checksum offload 409 * This option defaults to enabled (set) */ 410 411 #define XEMACPS_TX_CHKSUM_ENABLE_OPTION 0x00002000U 412 /**< Enable the TX checksum offload 413 * This option defaults to enabled (set) */ 414 415 #define XEMACPS_JUMBO_ENABLE_OPTION 0x00004000U 416 #define XEMACPS_SGMII_ENABLE_OPTION 0x00008000U 417 418 #define XEMACPS_DEFAULT_OPTIONS \ 419 ((u32)XEMACPS_FLOW_CONTROL_OPTION | \ 420 (u32)XEMACPS_FCS_INSERT_OPTION | \ 421 (u32)XEMACPS_FCS_STRIP_OPTION | \ 422 (u32)XEMACPS_BROADCAST_OPTION | \ 423 (u32)XEMACPS_LENTYPE_ERR_OPTION | \ 424 (u32)XEMACPS_TRANSMITTER_ENABLE_OPTION | \ 425 (u32)XEMACPS_RECEIVER_ENABLE_OPTION | \ 426 (u32)XEMACPS_RX_CHKSUM_ENABLE_OPTION | \ 427 (u32)XEMACPS_TX_CHKSUM_ENABLE_OPTION) 428 429 /**< Default options set when device is initialized or reset */ 430 /*@}*/ 431 432 /** @name Callback identifiers 433 * 434 * These constants are used as parameters to XEmacPs_SetHandler() 435 * @{ 436 */ 437 #define XEMACPS_HANDLER_DMASEND 1U 438 #define XEMACPS_HANDLER_DMARECV 2U 439 #define XEMACPS_HANDLER_ERROR 3U 440 /*@}*/ 441 442 /* Constants to determine the configuration of the hardware device. They are 443 * used to allow the driver to verify it can operate with the hardware. 444 */ 445 #define XEMACPS_MDIO_DIV_DFT MDC_DIV_32 /**< Default MDIO clock divisor */ 446 447 /* The next few constants help upper layers determine the size of memory 448 * pools used for Ethernet buffers and descriptor lists. 449 */ 450 #define XEMACPS_MAC_ADDR_SIZE 6U /* size of Ethernet header */ 451 452 #define XEMACPS_MTU 1500U /* max MTU size of Ethernet frame */ 453 #define XEMACPS_MTU_JUMBO 10240U /* max MTU size of jumbo frame */ 454 #define XEMACPS_HDR_SIZE 14U /* size of Ethernet header */ 455 #define XEMACPS_HDR_VLAN_SIZE 18U /* size of Ethernet header with VLAN */ 456 #define XEMACPS_TRL_SIZE 4U /* size of Ethernet trailer (FCS) */ 457 #define XEMACPS_MAX_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \ 458 XEMACPS_TRL_SIZE) 459 #define XEMACPS_MAX_VLAN_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \ 460 XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE) 461 #define XEMACPS_MAX_VLAN_FRAME_SIZE_JUMBO (XEMACPS_MTU_JUMBO + XEMACPS_HDR_SIZE + \ 462 XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE) 463 464 /* DMACR Bust length hash defines */ 465 466 #define XEMACPS_SINGLE_BURST 0x00000001 467 #define XEMACPS_4BYTE_BURST 0x00000004 468 #define XEMACPS_8BYTE_BURST 0x00000008 469 #define XEMACPS_16BYTE_BURST 0x00000010 470 471 472 /**************************** Type Definitions ******************************/ 473 /** @name Typedefs for callback functions 474 * 475 * These callbacks are invoked in interrupt context. 476 * @{ 477 */ 478 /** 479 * Callback invoked when frame(s) have been sent or received in interrupt 480 * driven DMA mode. To set the send callback, invoke XEmacPs_SetHandler(). 481 * 482 * @param CallBackRef is user data assigned when the callback was set. 483 * 484 * @note 485 * See xemacps_hw.h for bitmasks definitions and the device hardware spec for 486 * further information on their meaning. 487 * 488 */ 489 typedef void (*XEmacPs_Handler) (void *CallBackRef); 490 491 /** 492 * Callback when an asynchronous error occurs. To set this callback, invoke 493 * XEmacPs_SetHandler() with XEMACPS_HANDLER_ERROR in the HandlerType 494 * parameter. 495 * 496 * @param CallBackRef is user data assigned when the callback was set. 497 * @param Direction defines either receive or transmit error(s) has occurred. 498 * @param ErrorWord definition varies with Direction 499 * 500 */ 501 typedef void (*XEmacPs_ErrHandler) (void *CallBackRef, u8 Direction, 502 u32 ErrorWord); 503 504 /*@}*/ 505 506 /** 507 * This typedef contains configuration information for a device. 508 */ 509 typedef struct { 510 u16 DeviceId; /**< Unique ID of device */ 511 UINTPTR BaseAddress;/**< Physical base address of IPIF registers */ 512 u8 IsCacheCoherent; /**< Applicable only to A53 in EL1 mode; 513 * describes whether Cache Coherent or not */ 514 #if defined (XCLOCKING) 515 u32 RefClk; /**< Input clock */ 516 #endif 517 } XEmacPs_Config; 518 519 520 /** 521 * The XEmacPs driver instance data. The user is required to allocate a 522 * structure of this type for every XEmacPs device in the system. A pointer 523 * to a structure of this type is then passed to the driver API functions. 524 */ 525 typedef struct XEmacPs_Instance { 526 XEmacPs_Config Config; /* Hardware configuration */ 527 u32 IsStarted; /* Device is currently started */ 528 u32 IsReady; /* Device is initialized and ready */ 529 u32 Options; /* Current options word */ 530 531 XEmacPs_BdRing TxBdRing; /* Transmit BD ring */ 532 XEmacPs_BdRing RxBdRing; /* Receive BD ring */ 533 534 XEmacPs_Handler SendHandler; 535 XEmacPs_Handler RecvHandler; 536 void *SendRef; 537 void *RecvRef; 538 539 XEmacPs_ErrHandler ErrorHandler; 540 void *ErrorRef; 541 u32 Version; 542 u32 RxBufMask; 543 u32 MaxMtuSize; 544 u32 MaxFrameSize; 545 u32 MaxVlanFrameSize; 546 547 } XEmacPs; 548 549 550 /***************** Macros (Inline Functions) Definitions ********************/ 551 552 /****************************************************************************/ 553 /** 554 * Retrieve the Tx ring object. This object can be used in the various Ring 555 * API functions. 556 * 557 * @param InstancePtr is the DMA channel to operate on. 558 * 559 * @return TxBdRing attribute 560 * 561 * @note 562 * C-style signature: 563 * XEmacPs_BdRing XEmacPs_GetTxRing(XEmacPs *InstancePtr) 564 * 565 *****************************************************************************/ 566 #define XEmacPs_GetTxRing(InstancePtr) ((InstancePtr)->TxBdRing) 567 568 /****************************************************************************/ 569 /** 570 * Retrieve the Rx ring object. This object can be used in the various Ring 571 * API functions. 572 * 573 * @param InstancePtr is the DMA channel to operate on. 574 * 575 * @return RxBdRing attribute 576 * 577 * @note 578 * C-style signature: 579 * XEmacPs_BdRing XEmacPs_GetRxRing(XEmacPs *InstancePtr) 580 * 581 *****************************************************************************/ 582 #define XEmacPs_GetRxRing(InstancePtr) ((InstancePtr)->RxBdRing) 583 584 /****************************************************************************/ 585 /** 586 * 587 * Enable interrupts specified in <i>Mask</i>. The corresponding interrupt for 588 * each bit set to 1 in <i>Mask</i>, will be enabled. 589 * 590 * @param InstancePtr is a pointer to the instance to be worked on. 591 * @param Mask contains a bit mask of interrupts to enable. The mask can 592 * be formed using a set of bitwise or'd values. 593 * 594 * @note 595 * The state of the transmitter and receiver are not modified by this function. 596 * C-style signature 597 * void XEmacPs_IntEnable(XEmacPs *InstancePtr, u32 Mask) 598 * 599 *****************************************************************************/ 600 #define XEmacPs_IntEnable(InstancePtr, Mask) \ 601 XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \ 602 XEMACPS_IER_OFFSET, \ 603 ((Mask) & XEMACPS_IXR_ALL_MASK)); 604 605 /****************************************************************************/ 606 /** 607 * 608 * Disable interrupts specified in <i>Mask</i>. The corresponding interrupt for 609 * each bit set to 1 in <i>Mask</i>, will be enabled. 610 * 611 * @param InstancePtr is a pointer to the instance to be worked on. 612 * @param Mask contains a bit mask of interrupts to disable. The mask can 613 * be formed using a set of bitwise or'd values. 614 * 615 * @note 616 * The state of the transmitter and receiver are not modified by this function. 617 * C-style signature 618 * void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask) 619 * 620 *****************************************************************************/ 621 #define XEmacPs_IntDisable(InstancePtr, Mask) \ 622 XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \ 623 XEMACPS_IDR_OFFSET, \ 624 ((Mask) & XEMACPS_IXR_ALL_MASK)); 625 626 /****************************************************************************/ 627 /** 628 * 629 * Enable interrupts specified in <i>Mask</i>. The corresponding interrupt for 630 * each bit set to 1 in <i>Mask</i>, will be enabled. 631 * 632 * @param InstancePtr is a pointer to the instance to be worked on. 633 * @param Mask contains a bit mask of interrupts to enable. The mask can 634 * be formed using a set of bitwise or'd values. 635 * 636 * @note 637 * The state of the transmitter and receiver are not modified by this function. 638 * C-style signature 639 * void XEmacPs_IntQ1Enable(XEmacPs *InstancePtr, u32 Mask) 640 * 641 *****************************************************************************/ 642 #define XEmacPs_IntQ1Enable(InstancePtr, Mask) \ 643 XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \ 644 XEMACPS_INTQ1_IER_OFFSET, \ 645 ((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK)); 646 647 /****************************************************************************/ 648 /** 649 * 650 * Disable interrupts specified in <i>Mask</i>. The corresponding interrupt for 651 * each bit set to 1 in <i>Mask</i>, will be enabled. 652 * 653 * @param InstancePtr is a pointer to the instance to be worked on. 654 * @param Mask contains a bit mask of interrupts to disable. The mask can 655 * be formed using a set of bitwise or'd values. 656 * 657 * @note 658 * The state of the transmitter and receiver are not modified by this function. 659 * C-style signature 660 * void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask) 661 * 662 *****************************************************************************/ 663 #define XEmacPs_IntQ1Disable(InstancePtr, Mask) \ 664 XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \ 665 XEMACPS_INTQ1_IDR_OFFSET, \ 666 ((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK)); 667 668 /****************************************************************************/ 669 /** 670 * 671 * This macro triggers trasmit circuit to send data currently in TX buffer(s). 672 * 673 * @param InstancePtr is a pointer to the XEmacPs instance to be worked on. 674 * 675 * @return 676 * 677 * @note 678 * 679 * Signature: void XEmacPs_Transmit(XEmacPs *InstancePtr) 680 * 681 *****************************************************************************/ 682 #define XEmacPs_Transmit(InstancePtr) \ 683 XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \ 684 XEMACPS_NWCTRL_OFFSET, \ 685 (XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \ 686 XEMACPS_NWCTRL_OFFSET) | XEMACPS_NWCTRL_STARTTX_MASK)) 687 688 /****************************************************************************/ 689 /** 690 * 691 * This macro determines if the device is configured with checksum offloading 692 * on the receive channel 693 * 694 * @param InstancePtr is a pointer to the XEmacPs instance to be worked on. 695 * 696 * @return 697 * 698 * Boolean TRUE if the device is configured with checksum offloading, or 699 * FALSE otherwise. 700 * 701 * @note 702 * 703 * Signature: u32 XEmacPs_IsRxCsum(XEmacPs *InstancePtr) 704 * 705 *****************************************************************************/ 706 #define XEmacPs_IsRxCsum(InstancePtr) \ 707 ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \ 708 XEMACPS_NWCFG_OFFSET) & XEMACPS_NWCFG_RXCHKSUMEN_MASK) != 0U \ 709 ? TRUE : FALSE) 710 711 /****************************************************************************/ 712 /** 713 * 714 * This macro determines if the device is configured with checksum offloading 715 * on the transmit channel 716 * 717 * @param InstancePtr is a pointer to the XEmacPs instance to be worked on. 718 * 719 * @return 720 * 721 * Boolean TRUE if the device is configured with checksum offloading, or 722 * FALSE otherwise. 723 * 724 * @note 725 * 726 * Signature: u32 XEmacPs_IsTxCsum(XEmacPs *InstancePtr) 727 * 728 *****************************************************************************/ 729 #define XEmacPs_IsTxCsum(InstancePtr) \ 730 ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \ 731 XEMACPS_DMACR_OFFSET) & XEMACPS_DMACR_TCPCKSUM_MASK) != 0U \ 732 ? TRUE : FALSE) 733 734 /************************** Function Prototypes *****************************/ 735 736 /****************************************************************************/ 737 /** 738 * 739 * This macro sets RX watermark register. 740 * 741 * @param InstancePtr is a pointer to the XEmacPs instance to be worked on. 742 * @param High is the non-zero RX high watermark value. When SRAM fill level 743 * is above this, a pause frame will be sent. 744 * @param Low is the non-zero RX low watermark value. When SRAM fill level 745 * is below this, a zero length pause frame will be sent IF the last 746 * pause frame sent was non-zero. 747 * 748 * @return None 749 * 750 * @note 751 * 752 * Signature: void XEmacPs_SetRXWatermark(XEmacPs *InstancePtr, u16 High, 753 * u16 Low) 754 * 755 *****************************************************************************/ 756 #define XEmacPs_SetRXWatermark(InstancePtr, High, Low) \ 757 XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \ 758 XEMACPS_RXWATERMARK_OFFSET, \ 759 (High & XEMACPS_RXWM_HIGH_MASK) | \ 760 ((Low << XEMACPS_RXWM_LOW_SHFT_MSK) & XEMACPS_RXWM_LOW_MASK) |) 761 762 /****************************************************************************/ 763 /** 764 * 765 * This macro gets RX watermark register. 766 * 767 * @param InstancePtr is a pointer to the XEmacPs instance to be worked on. 768 * 769 * @return RX watermark register value 770 * 771 * @note 772 * 773 * Signature: void XEmacPs_GetRXWatermark(XEmacPs *InstancePtr) 774 * 775 *****************************************************************************/ 776 #define XEmacPs_GetRXWatermark(InstancePtr) \ 777 XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \ 778 XEMACPS_RXWATERMARK_OFFSET) 779 /* 780 * Initialization functions in xemacps.c 781 */ 782 LONG XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config *CfgPtr, 783 UINTPTR EffectiveAddress); 784 void XEmacPs_Start(XEmacPs *InstancePtr); 785 void XEmacPs_Stop(XEmacPs *InstancePtr); 786 void XEmacPs_Reset(XEmacPs *InstancePtr); 787 void XEmacPs_SetQueuePtr(XEmacPs *InstancePtr, UINTPTR QPtr, u8 QueueNum, 788 u16 Direction); 789 790 /* 791 * Lookup configuration in xemacps_sinit.c 792 */ 793 XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId); 794 795 /* 796 * Interrupt-related functions in xemacps_intr.c 797 * DMA only and FIFO is not supported. This DMA does not support coalescing. 798 */ 799 LONG XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType, 800 void *FuncPointer, void *CallBackRef); 801 void XEmacPs_IntrHandler(void *XEmacPsPtr); 802 803 /* 804 * MAC configuration/control functions in XEmacPs_control.c 805 */ 806 LONG XEmacPs_SetOptions(XEmacPs *InstancePtr, u32 Options); 807 LONG XEmacPs_ClearOptions(XEmacPs *InstancePtr, u32 Options); 808 u32 XEmacPs_GetOptions(XEmacPs *InstancePtr); 809 810 LONG XEmacPs_SetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index); 811 LONG XEmacPs_DeleteHash(XEmacPs *InstancePtr, void *AddressPtr); 812 void XEmacPs_GetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index); 813 814 LONG XEmacPs_SetHash(XEmacPs *InstancePtr, void *AddressPtr); 815 void XEmacPs_ClearHash(XEmacPs *InstancePtr); 816 void XEmacPs_GetHash(XEmacPs *InstancePtr, void *AddressPtr); 817 818 void XEmacPs_SetMdioDivisor(XEmacPs *InstancePtr, 819 XEmacPs_MdcDiv Divisor); 820 void XEmacPs_SetOperatingSpeed(XEmacPs *InstancePtr, u16 Speed); 821 u16 XEmacPs_GetOperatingSpeed(XEmacPs *InstancePtr); 822 LONG XEmacPs_PhyRead(XEmacPs *InstancePtr, u32 PhyAddress, 823 u32 RegisterNum, u16 *PhyDataPtr); 824 LONG XEmacPs_PhyWrite(XEmacPs *InstancePtr, u32 PhyAddress, 825 u32 RegisterNum, u16 PhyData); 826 LONG XEmacPs_SetTypeIdCheck(XEmacPs *InstancePtr, u32 Id_Check, u8 Index); 827 828 LONG XEmacPs_SendPausePacket(XEmacPs *InstancePtr); 829 void XEmacPs_DMABLengthUpdate(XEmacPs *InstancePtr, s32 BLength); 830 831 #ifdef __cplusplus 832 } 833 #endif 834 835 #endif /* end of protection macro */ 836 /** @} */ 837