1 /******************************************************************************
2 * Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
3 * SPDX-License-Identifier: MIT
4 ******************************************************************************/
5
6 /*****************************************************************************/
7 /**
8 *
9 * @file xemacps_intr.c
10 * @addtogroup emacps_v3_11
11 * @{
12 *
13 * Functions in this file implement general purpose interrupt processing related
14 * functionality. See xemacps.h for a detailed description of the driver.
15 *
16 * <pre>
17 * MODIFICATION HISTORY:
18 *
19 * Ver Who Date Changes
20 * ----- ---- -------- -------------------------------------------------------
21 * 1.00a wsy 01/10/10 First release
22 * 1.03a asa 01/24/13 Fix for CR #692702 which updates error handling for
23 * Rx errors. Under heavy Rx traffic, there will be a large
24 * number of errors related to receive buffer not available.
25 * Because of a HW bug (SI #692601), under such heavy errors,
26 * the Rx data path can become unresponsive. To reduce the
27 * probabilities for hitting this HW bug, the SW writes to
28 * bit 18 to flush a packet from Rx DPRAM immediately. The
29 * changes for it are done in the function
30 * XEmacPs_IntrHandler.
31 * 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp GEM specification
32 * and 64-bit changes.
33 * 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
34 * 3.1 hk 07/27/15 Do not call error handler with '0' error code when
35 * there is no error. CR# 869403
36 * </pre>
37 ******************************************************************************/
38
39 /***************************** Include Files *********************************/
40
41 #include "xemacps.h"
42
43 /************************** Constant Definitions *****************************/
44
45
46 /**************************** Type Definitions *******************************/
47
48
49 /***************** Macros (Inline Functions) Definitions *********************/
50
51
52 /************************** Function Prototypes ******************************/
53
54
55 /************************** Variable Definitions *****************************/
56
57
58 /*****************************************************************************/
59 /**
60 * Install an asynchronous handler function for the given HandlerType:
61 *
62 * @param InstancePtr is a pointer to the instance to be worked on.
63 * @param HandlerType indicates what interrupt handler type is.
64 * XEMACPS_HANDLER_DMASEND, XEMACPS_HANDLER_DMARECV and
65 * XEMACPS_HANDLER_ERROR.
66 * @param FuncPointer is the pointer to the callback function
67 * @param CallBackRef is the upper layer callback reference passed back when
68 * when the callback function is invoked.
69 *
70 * @return
71 *
72 * None.
73 *
74 * @note
75 * There is no assert on the CallBackRef since the driver doesn't know what
76 * it is.
77 *
78 *****************************************************************************/
XEmacPs_SetHandler(XEmacPs * InstancePtr,u32 HandlerType,void * FuncPointer,void * CallBackRef)79 LONG XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType,
80 void *FuncPointer, void *CallBackRef)
81 {
82 LONG Status;
83 Xil_AssertNonvoid(InstancePtr != NULL);
84 Xil_AssertNonvoid(FuncPointer != NULL);
85 Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
86
87 switch (HandlerType) {
88 case XEMACPS_HANDLER_DMASEND:
89 Status = (LONG)(XST_SUCCESS);
90 InstancePtr->SendHandler = ((XEmacPs_Handler)(void *)FuncPointer);
91 InstancePtr->SendRef = CallBackRef;
92 break;
93 case XEMACPS_HANDLER_DMARECV:
94 Status = (LONG)(XST_SUCCESS);
95 InstancePtr->RecvHandler = ((XEmacPs_Handler)(void *)FuncPointer);
96 InstancePtr->RecvRef = CallBackRef;
97 break;
98 case XEMACPS_HANDLER_ERROR:
99 Status = (LONG)(XST_SUCCESS);
100 InstancePtr->ErrorHandler = ((XEmacPs_ErrHandler)(void *)FuncPointer);
101 InstancePtr->ErrorRef = CallBackRef;
102 break;
103 default:
104 Status = (LONG)(XST_INVALID_PARAM);
105 break;
106 }
107 return Status;
108 }
109
110 /*****************************************************************************/
111 /**
112 * Master interrupt handler for EMAC driver. This routine will query the
113 * status of the device, bump statistics, and invoke user callbacks.
114 *
115 * This routine must be connected to an interrupt controller using OS/BSP
116 * specific methods.
117 *
118 * @param XEmacPsPtr is a pointer to the XEMACPS instance that has caused the
119 * interrupt.
120 *
121 ******************************************************************************/
XEmacPs_IntrHandler(void * XEmacPsPtr)122 void XEmacPs_IntrHandler(void *XEmacPsPtr)
123 {
124 u32 RegISR;
125 u32 RegSR;
126 u32 RegCtrl;
127 u32 RegQ1ISR = 0U;
128 XEmacPs *InstancePtr = (XEmacPs *) XEmacPsPtr;
129
130 Xil_AssertVoid(InstancePtr != NULL);
131 Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
132
133 /* This ISR will try to handle as many interrupts as it can in a single
134 * call. However, in most of the places where the user's error handler
135 * is called, this ISR exits because it is expected that the user will
136 * reset the device in nearly all instances.
137 */
138 RegISR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
139 XEMACPS_ISR_OFFSET);
140
141 /* Read Transmit Q1 ISR */
142
143 if (InstancePtr->Version > 2)
144 RegQ1ISR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
145 XEMACPS_INTQ1_STS_OFFSET);
146
147 /* Clear the interrupt status register */
148 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET,
149 RegISR);
150
151 /* Receive complete interrupt */
152 if ((RegISR & XEMACPS_IXR_FRAMERX_MASK) != 0x00000000U) {
153 /* Clear RX status register RX complete indication but preserve
154 * error bits if there is any */
155 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
156 XEMACPS_RXSR_OFFSET,
157 ((u32)XEMACPS_RXSR_FRAMERX_MASK |
158 (u32)XEMACPS_RXSR_BUFFNA_MASK));
159 InstancePtr->RecvHandler(InstancePtr->RecvRef);
160 }
161
162 /* Transmit Q1 complete interrupt */
163 if ((InstancePtr->Version > 2) &&
164 ((RegQ1ISR & XEMACPS_INTQ1SR_TXCOMPL_MASK) != 0x00000000U)) {
165 /* Clear TX status register TX complete indication but preserve
166 * error bits if there is any */
167 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
168 XEMACPS_INTQ1_STS_OFFSET,
169 XEMACPS_INTQ1SR_TXCOMPL_MASK);
170 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
171 XEMACPS_TXSR_OFFSET,
172 ((u32)XEMACPS_TXSR_TXCOMPL_MASK |
173 (u32)XEMACPS_TXSR_USEDREAD_MASK));
174 InstancePtr->SendHandler(InstancePtr->SendRef);
175 }
176
177 /* Transmit complete interrupt */
178 if ((RegISR & XEMACPS_IXR_TXCOMPL_MASK) != 0x00000000U) {
179 /* Clear TX status register TX complete indication but preserve
180 * error bits if there is any */
181 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
182 XEMACPS_TXSR_OFFSET,
183 ((u32)XEMACPS_TXSR_TXCOMPL_MASK |
184 (u32)XEMACPS_TXSR_USEDREAD_MASK));
185 InstancePtr->SendHandler(InstancePtr->SendRef);
186 }
187
188 /* Receive error conditions interrupt */
189 if ((RegISR & XEMACPS_IXR_RX_ERR_MASK) != 0x00000000U) {
190 /* Clear RX status register */
191 RegSR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
192 XEMACPS_RXSR_OFFSET);
193 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
194 XEMACPS_RXSR_OFFSET, RegSR);
195
196 /* Fix for CR # 692702. Write to bit 18 of net_ctrl
197 * register to flush a packet out of Rx SRAM upon
198 * an error for receive buffer not available. */
199 if ((RegISR & XEMACPS_IXR_RXUSED_MASK) != 0x00000000U) {
200 RegCtrl =
201 XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
202 XEMACPS_NWCTRL_OFFSET);
203 RegCtrl |= (u32)XEMACPS_NWCTRL_FLUSH_DPRAM_MASK;
204 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
205 XEMACPS_NWCTRL_OFFSET, RegCtrl);
206 }
207
208 if(RegSR != 0) {
209 InstancePtr->ErrorHandler(InstancePtr->ErrorRef,
210 XEMACPS_RECV, RegSR);
211 }
212 }
213
214 /* When XEMACPS_IXR_TXCOMPL_MASK is flagged, XEMACPS_IXR_TXUSED_MASK
215 * will be asserted the same time.
216 * Have to distinguish this bit to handle the real error condition.
217 */
218 /* Transmit Q1 error conditions interrupt */
219 if ((InstancePtr->Version > 2) &&
220 ((RegQ1ISR & XEMACPS_INTQ1SR_TXERR_MASK) != 0x00000000U) &&
221 ((RegQ1ISR & XEMACPS_INTQ1SR_TXCOMPL_MASK) != 0x00000000U)) {
222 /* Clear Interrupt Q1 status register */
223 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
224 XEMACPS_INTQ1_STS_OFFSET, RegQ1ISR);
225 InstancePtr->ErrorHandler(InstancePtr->ErrorRef, XEMACPS_SEND,
226 RegQ1ISR);
227 }
228
229 /* Transmit error conditions interrupt */
230 if (((RegISR & XEMACPS_IXR_TX_ERR_MASK) != 0x00000000U) &&
231 (!(RegISR & XEMACPS_IXR_TXCOMPL_MASK) != 0x00000000U)) {
232 /* Clear TX status register */
233 RegSR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
234 XEMACPS_TXSR_OFFSET);
235 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
236 XEMACPS_TXSR_OFFSET, RegSR);
237 InstancePtr->ErrorHandler(InstancePtr->ErrorRef, XEMACPS_SEND,
238 RegSR);
239 }
240
241 }
242 /** @} */
243