1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* 3 * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. 4 */ 5 6 #ifndef __SOC_H 7 #define __SOC_H 8 #ifdef __cplusplus 9 extern "C" { 10 #endif 11 12 #ifndef __ASSEMBLY__ 13 /* ================================================================================ */ 14 /* ================ DMA REQ =============== */ 15 /* ================================================================================ */ 16 typedef enum { 17 DMA_REQ_UART0_TX = 0, 18 DMA_REQ_UART0_RX = 1, 19 DMA_REQ_UART1_TX = 2, 20 DMA_REQ_UART1_RX = 3, 21 DMA_REQ_UART2_TX = 4, 22 DMA_REQ_UART2_RX = 5, 23 DMA_REQ_I2S0_TX = 6, 24 DMA_REQ_I2S0_RX = 7, 25 DMA_REQ_I2S1_TX = 8, 26 DMA_REQ_I2S1_RX = 9, 27 DMA_REQ_PDM0 = 10, 28 DMA_REQ_SPI1_TX = 11, 29 DMA_REQ_SPI1_RX = 12, 30 DMA_REQ_SPI2_TX = 13, 31 DMA_REQ_SPI2_RX = 14, 32 DMA_REQ_PWM = 15, 33 DMA_REQ_AUDIOPWM = 16, 34 } DMA_REQ_Type; 35 36 /* ================================================================================ */ 37 /* ================ IRQ ================ */ 38 /* ================================================================================ */ 39 typedef enum 40 { 41 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ 42 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ 43 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ 44 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ 45 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ 46 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ 47 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ 48 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ 49 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ 50 /****** RK2108 specific Interrupt Numbers **********************************************************************/ 51 CACHE_IRQn = 0, /* cortex m4 cache */ 52 MAILBOX0_AP_IRQn = 2, /* Mailbox0 ap */ 53 MAILBOX0_BB_IRQn = 3, /* Mailbox0 bb */ 54 MAILBOX1_AP_IRQn = 4, /* Mailbox1 ap */ 55 MAILBOX1_BB_IRQn = 5, /* Mailbox1 bb */ 56 MAILBOX2_AP_IRQn = 6, /* Mailbox2 ap */ 57 MAILBOX2_BB_IRQn = 7, /* Mailbox2 bb */ 58 PMU_IRQn = 8, /* PMU */ 59 DMAC_IRQn = 9, /* DMAC */ 60 DMAC_ABORT_IRQn = 10, /* DMA Abort */ 61 UART0_IRQn = 11, /* UART 0 */ 62 UART1_IRQn = 12, /* UART 1 */ 63 UART2_IRQn = 13, /* UART 2 */ 64 TIMER0_IRQn = 14, /* Timer 0 */ 65 TIMER1_IRQn = 15, /* Timer 1 */ 66 TIMER2_IRQn = 16, /* Timer 2 */ 67 TIMER3_IRQn = 17, /* Timer 3 */ 68 TIMER4_IRQn = 18, /* Timer 4 */ 69 TIMER5_IRQn = 19, /* Timer 5 */ 70 WDT0_IRQn = 20, /* Watch dog 0 */ 71 WDT1_IRQn = 21, /* Watch dog 1 */ 72 I2CMST0_IRQn = 22, /* I2C Master 0 */ 73 I2CMST1_IRQn = 23, /* I2C Master 1 */ 74 I2CMST2_IRQn = 24, /* I2C Master 2 */ 75 SPISLV0_IRQn = 25, /* SPI Slave 0 */ 76 SPIMST1_IRQn = 26, /* SPI Master 1 */ 77 FSPI0_IRQn = 27, /* FSPI0 */ 78 SDIO_IRQn = 28, /* SDIO */ 79 GPIO0_IRQn = 29, /* GPIO 0 */ 80 GPIO1_IRQn = 30, /* GPIO 1 */ 81 USB_IRQn = 31, /* USB */ 82 I2S0_IRQn = 32, /* I2S 0 */ 83 PDM0_IRQn = 33, /* PDM 0 */ 84 I2S1_IRQn = 34, /* I2S 1 */ 85 VAD_IRQn = 35, /* VAD */ 86 VOP_IRQn = 36, /* VOP */ 87 VOP_POST_LB_IRQn = 37, /* VOP post lb */ 88 MIPI_DSI_HOST_IRQn = 38, /* MIPI dsi host */ 89 TP_IRQn = 39, /* TP */ 90 DSP_PFATAL_ERROR_IRQn = 40, /* DSP pfatal error */ 91 PWM_IRQn = 41, /* PWM */ 92 PWM_PWR_IRQn = 42, /* PWM PWR */ 93 AUDIOPWM_IRQn = 43, /* AUDIOPWM */ 94 VICAP_IRQn = 44, /* VICAP */ 95 SPIMST2_IRQn = 45, /* SPI Master 2 */ 96 KEY_CTRL_IRQn = 46, /* KEY Control */ 97 FSPI1_IRQn = 47, /* FSPI1 */ 98 NUM_INTERRUPTS 99 } IRQn_Type; 100 #endif /* __ASSEMBLY__ */ 101 102 #define NVIC_PERIPH_IRQ_NUM MAX_IRQn 103 #define NVIC_PERIPH_IRQ_OFFSET 16 104 105 #define MAILBOX0_AP_IRQ0 MAILBOX0_AP_IRQn 106 #define MAILBOX0_AP_IRQ1 MAILBOX0_AP_IRQn 107 #define MAILBOX0_AP_IRQ2 MAILBOX0_AP_IRQn 108 #define MAILBOX0_AP_IRQ3 MAILBOX0_AP_IRQn 109 110 /* ================================================================================ */ 111 /* ================ Processor and Core Peripheral Section ================ */ 112 /* ================================================================================ */ 113 114 #define __CM4_REV 0x0001U /* Core revision r0p1 */ 115 #define __MPU_PRESENT 1U /* RK2108 provides an MPU */ 116 #define __VTOR_PRESENT 1U /* VTOR present */ 117 #define __NVIC_PRIO_BITS 3U /* RK2108 uses 3 Bits for the Priority Levels */ 118 #define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ 119 #define __FPU_PRESENT 1U /* FPU present */ 120 121 #ifndef __ASSEMBLY__ 122 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ 123 #include "system_rk2108.h" 124 #endif /* __ASSEMBLY__ */ 125 #include "rk2108.h" 126 #include "rk2108_usb.h" 127 128 /****************************************************************************************/ 129 /* */ 130 /* Module Structure Section */ 131 /* */ 132 /****************************************************************************************/ 133 134 /****************************************************************************************/ 135 /* */ 136 /* Module Address Section */ 137 /* */ 138 /****************************************************************************************/ 139 /* Memory Base */ 140 #define XIP_MAP0_BASE0 0x18000000U /* FSPI0 map address0 */ 141 #define XIP_MAP1_BASE0 0x1C000000U /* FSPI1 map address0 */ 142 #define DSP_ITCM_BASE 0x30000000U /* DSP itcm base address */ 143 #define DSP_ITCM_END 0x3000ffffU /* DSP itcm end address */ 144 #define DSP_DTCM_BASE 0x30200000U /* DSP dtcm base address */ 145 #define DSP_DTCM_END 0x3027ffffU /* DSP dtcm end address */ 146 #define USB_M31PHY_BASE 0x400B0340U /* USB M31 PHY base address */ 147 #define SDIO_BASE MMC_BASE /* 0x40C90000U MMC base address */ 148 #define USB_BASE 0x41300000U /* USB base address */ 149 #define XIP_MAP0_BASE1 0x60000000U /* FSPI0 map address1 */ 150 #define XIP_MAP1_BASE1 0x64000000U /* FSPI1 map address1 */ 151 #define USB_PHY_CON_BASE (GRF->USBPHY_CON0) /* USB PHY control base address */ 152 #define USB_PHY_STATUS_BASE (GRF->USBPHY_STATUS0) /* USB PHY status base address */ 153 /****************************************************************************************/ 154 /* */ 155 /* Module Variable Section */ 156 /* */ 157 /****************************************************************************************/ 158 /* Module Variable Define */ 159 #define USB ((struct USB_GLOBAL_REG *) USB_BASE) 160 161 #define IS_PCD_INSTANCE(instance) ((instance) == USB) 162 #define IS_HCD_INSTANCE(instance) ((instance) == USB) 163 /****************************************************************************************/ 164 /* */ 165 /* Register Bitmap Section */ 166 /* */ 167 /****************************************************************************************/ 168 /*****************************************ICACHE*****************************************/ 169 /* CACHE LINE SIZE */ 170 #define CACHE_LINE_SHIFT (5U) 171 #define CACHE_LINE_SIZE (0x1U << CACHE_LINE_SHIFT) 172 #define CACHE_LINE_ADDR_MASK (0xFFFFFFFFU << CACHE_LINE_SHIFT) 173 #define CACHE_M_CLEAN 0x0U 174 #define CACHE_M_INVALID 0x2U 175 #define CACHE_M_CLEAN_INVALID 0x4U 176 #define CACHE_M_INVALID_ALL 0x6U 177 178 /* ICACHE ADDR TO DCACHE ADDR */ 179 #define SRAM_IADDR_START (0x04000000U) 180 #define SRAM_SIZE (0x00100000U) 181 #define SRAM_IADDR_TO_DADDR_OFFSET (0x1c000000U) 182 #define XIP_NOR_IADDR_START (0x18000000U) 183 #define XIP_NOR_SIZE (0x04000000U) 184 #define XIP_NOR_IADDR_TO_DADDR_OFFSET (0x48000000U) 185 #define XIP_PSRAM_IADDR_START (0x1C000000U) 186 #define XIP_PSRAM_SIZE (0x04000000U) 187 #define XIP_PSRAM_IADDR_TO_DADDR_OFFSET (0x48000000U) 188 189 #define CACHE_REVISION (0x00000100U) 190 /*****************************************PMU*****************************************/ 191 #ifndef __ASSEMBLY__ 192 typedef enum PD_Id { 193 PD_DSP = 0x80000000U, 194 PD_LOGIC = 0x80011111U, 195 PD_SHRM = 0x80022222U, 196 PD_AUDIO = 0x80033333U, 197 } ePD_Id; 198 #endif 199 /****************************************FSPI********************************************/ 200 #define FSPI_CHIP_CNT (2) 201 /****************************************MMC*********************************************/ 202 #define CLK_SDIO_PLL CLK_SDIO_SRC 203 /****************************************WDT*********************************************/ 204 #define PCLK_WDT PCLK_LOGIC 205 /****************************************CRU*********************************************/ 206 #define CPU_CLK_ID HCLK_M4 207 #define MEM_CLK_ID SCLK_SHRM 208 #define DSP_CLK_ID ACLK_DSP 209 /****************************************MBOX********************************************/ 210 #define MBOX_CNT 2 211 #define MBOX_CHAN_CNT 4 212 /****************************************USB********************************************/ 213 #define USB_PHY_SUSPEND_MASK \ 214 (GRF_USBPHY_CON0_UTMI_SEL_MASK | GRF_USBPHY_CON0_UTMI_SUSPEND_N_MASK | \ 215 GRF_USBPHY_CON0_UTMI_OPMODE_MASK | GRF_USBPHY_CON0_UTMI_XCVRSELECT_MASK | \ 216 GRF_USBPHY_CON0_UTMI_TERMSELECT_MASK | GRF_USBPHY_CON0_UTMI_DPPULLDOWN_MASK |\ 217 GRF_USBPHY_CON0_UTMI_DMPULLDOWN_MASK) 218 #define USB_PHY_RESUME_MASK GRF_USBPHY_CON0_UTMI_SEL_MASK 219 #define USB_PHY_CON_SHIFT GRF_USBPHY_CON0_UTMI_SEL_SHIFT 220 #define USB_PHY_LINESTATE_MASK GRF_USBPHY_STATUS0_UTMI_LINESTATE_MASK 221 #define USB_PHY_LINESTATE_SHIFT GRF_USBPHY_STATUS0_UTMI_LINESTATE_SHIFT 222 #define USB_PHY_SUSPEND_VAL 0x1d1U 223 #define USB_PHY_RESUME_VAL 0 224 225 #ifdef __cplusplus 226 } 227 #endif /* __cplusplus */ 228 #endif /* __SOC_H */ 229