1 #ifndef XPARAMETERS_H /* prevent circular inclusions */ 2 #define XPARAMETERS_H /* by using protection macros */ 3 4 /* Definition for CPU ID */ 5 #define XPAR_CPU_ID 0U 6 7 /* Definitions for peripheral PSU_CORTEXR5_0 */ 8 #define XPAR_PSU_CORTEXR5_0_CPU_CLK_FREQ_HZ 499994995 9 10 11 /******************************************************************/ 12 13 /* Canonical definitions for peripheral PSU_CORTEXR5_0 */ 14 #define XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ 499994995 15 16 17 /******************************************************************/ 18 19 /* Definition for PSS REF CLK FREQUENCY */ 20 #define XPAR_PSU_PSS_REF_CLK_FREQ_HZ 33333000U 21 22 #include "xparameters_ps.h" 23 24 /******************************************************************/ 25 26 /*Definitions for peripheral PSU_R5_DDR_1 */ 27 #define XPAR_PSU_R5_DDR_1_S_AXI_BASEADDR 0x0 28 #define XPAR_PSU_R5_DDR_1_S_AXI_HIGHADDR 0x7fffffff 29 30 31 /* Number of Fabric Resets */ 32 #define XPAR_NUM_FABRIC_RESETS 1 33 34 #define STDIN_BASEADDRESS 0xFF000000 35 #define STDOUT_BASEADDRESS 0xFF000000 36 37 /******************************************************************/ 38 39 /* Platform specific definitions */ 40 #define PLATFORM_ZYNQMP 41 42 /* Definitions for debug logic configuration in lockstep mode */ 43 #define LOCKSTEP_MODE_DEBUG 0U 44 45 /* Definitions for sleep timer configuration */ 46 #define XSLEEP_TIMER_IS_DEFAULT_TIMER 47 48 /* Definitions for processor access to RPU/IOU slcr address space*/ 49 #define PROCESSOR_ACCESS_VALUE 255 50 51 /******************************************************************/ 52 /* Definitions for driver AVBUF */ 53 #define XPAR_XAVBUF_NUM_INSTANCES 1 54 55 /* Definitions for peripheral PSU_DP */ 56 #define XPAR_PSU_DP_DEVICE_ID 0 57 #define XPAR_PSU_DP_BASEADDR 0xFD4A0000 58 #define XPAR_PSU_DP_HIGHADDR 0xFD4AFFFF 59 60 61 /******************************************************************/ 62 63 /* Canonical definitions for peripheral PSU_DP */ 64 #define XPAR_XAVBUF_0_DEVICE_ID XPAR_PSU_DP_DEVICE_ID 65 #define XPAR_XAVBUF_0_BASEADDR 0xFD4A0000 66 #define XPAR_XAVBUF_0_HIGHADDR 0xFD4AFFFF 67 68 69 /******************************************************************/ 70 71 /* Definitions for driver AXIPMON */ 72 #define XPAR_XAXIPMON_NUM_INSTANCES 4U 73 74 /* Definitions for peripheral PSU_APM_0 */ 75 #define XPAR_PSU_APM_0_DEVICE_ID 0U 76 #define XPAR_PSU_APM_0_BASEADDR 0xFD0B0000U 77 #define XPAR_PSU_APM_0_HIGHADDR 0xFD0BFFFFU 78 #define XPAR_PSU_APM_0_GLOBAL_COUNT_WIDTH 32U 79 #define XPAR_PSU_APM_0_METRICS_SAMPLE_COUNT_WIDTH 32U 80 #define XPAR_PSU_APM_0_ENABLE_EVENT_COUNT 1U 81 #define XPAR_PSU_APM_0_NUM_MONITOR_SLOTS 6U 82 #define XPAR_PSU_APM_0_NUM_OF_COUNTERS 10U 83 #define XPAR_PSU_APM_0_HAVE_SAMPLED_METRIC_CNT 1U 84 #define XPAR_PSU_APM_0_ENABLE_EVENT_LOG 0U 85 #define XPAR_PSU_APM_0_FIFO_AXIS_DEPTH 32U 86 #define XPAR_PSU_APM_0_FIFO_AXIS_TDATA_WIDTH 56U 87 #define XPAR_PSU_APM_0_FIFO_AXIS_TID_WIDTH 1U 88 #define XPAR_PSU_APM_0_METRIC_COUNT_SCALE 1U 89 #define XPAR_PSU_APM_0_ENABLE_ADVANCED 1U 90 #define XPAR_PSU_APM_0_ENABLE_PROFILE 0U 91 #define XPAR_PSU_APM_0_ENABLE_TRACE 0U 92 #define XPAR_PSU_APM_0_S_AXI4_BASEADDR 0x00000000U 93 #define XPAR_PSU_APM_0_S_AXI4_HIGHADDR 0x00000000U 94 #define XPAR_PSU_APM_0_ENABLE_32BIT_FILTER_ID 1U 95 96 97 /* Definitions for peripheral PSU_APM_1 */ 98 #define XPAR_PSU_APM_1_DEVICE_ID 1U 99 #define XPAR_PSU_APM_1_BASEADDR 0xFFA00000U 100 #define XPAR_PSU_APM_1_HIGHADDR 0xFFA0FFFFU 101 #define XPAR_PSU_APM_1_GLOBAL_COUNT_WIDTH 32U 102 #define XPAR_PSU_APM_1_METRICS_SAMPLE_COUNT_WIDTH 32U 103 #define XPAR_PSU_APM_1_ENABLE_EVENT_COUNT 1U 104 #define XPAR_PSU_APM_1_NUM_MONITOR_SLOTS 1U 105 #define XPAR_PSU_APM_1_NUM_OF_COUNTERS 3U 106 #define XPAR_PSU_APM_1_HAVE_SAMPLED_METRIC_CNT 1U 107 #define XPAR_PSU_APM_1_ENABLE_EVENT_LOG 0U 108 #define XPAR_PSU_APM_1_FIFO_AXIS_DEPTH 32U 109 #define XPAR_PSU_APM_1_FIFO_AXIS_TDATA_WIDTH 56U 110 #define XPAR_PSU_APM_1_FIFO_AXIS_TID_WIDTH 1U 111 #define XPAR_PSU_APM_1_METRIC_COUNT_SCALE 1U 112 #define XPAR_PSU_APM_1_ENABLE_ADVANCED 1U 113 #define XPAR_PSU_APM_1_ENABLE_PROFILE 0U 114 #define XPAR_PSU_APM_1_ENABLE_TRACE 0U 115 #define XPAR_PSU_APM_1_S_AXI4_BASEADDR 0x00000000U 116 #define XPAR_PSU_APM_1_S_AXI4_HIGHADDR 0x00000000U 117 #define XPAR_PSU_APM_1_ENABLE_32BIT_FILTER_ID 1U 118 119 120 /* Definitions for peripheral PSU_APM_2 */ 121 #define XPAR_PSU_APM_2_DEVICE_ID 2U 122 #define XPAR_PSU_APM_2_BASEADDR 0xFFA10000U 123 #define XPAR_PSU_APM_2_HIGHADDR 0xFFA1FFFFU 124 #define XPAR_PSU_APM_2_GLOBAL_COUNT_WIDTH 32U 125 #define XPAR_PSU_APM_2_METRICS_SAMPLE_COUNT_WIDTH 32U 126 #define XPAR_PSU_APM_2_ENABLE_EVENT_COUNT 1U 127 #define XPAR_PSU_APM_2_NUM_MONITOR_SLOTS 1U 128 #define XPAR_PSU_APM_2_NUM_OF_COUNTERS 3U 129 #define XPAR_PSU_APM_2_HAVE_SAMPLED_METRIC_CNT 1U 130 #define XPAR_PSU_APM_2_ENABLE_EVENT_LOG 0U 131 #define XPAR_PSU_APM_2_FIFO_AXIS_DEPTH 32U 132 #define XPAR_PSU_APM_2_FIFO_AXIS_TDATA_WIDTH 56U 133 #define XPAR_PSU_APM_2_FIFO_AXIS_TID_WIDTH 1U 134 #define XPAR_PSU_APM_2_METRIC_COUNT_SCALE 1U 135 #define XPAR_PSU_APM_2_ENABLE_ADVANCED 1U 136 #define XPAR_PSU_APM_2_ENABLE_PROFILE 0U 137 #define XPAR_PSU_APM_2_ENABLE_TRACE 0U 138 #define XPAR_PSU_APM_2_S_AXI4_BASEADDR 0x00000000U 139 #define XPAR_PSU_APM_2_S_AXI4_HIGHADDR 0x00000000U 140 #define XPAR_PSU_APM_2_ENABLE_32BIT_FILTER_ID 1U 141 142 143 /* Definitions for peripheral PSU_APM_5 */ 144 #define XPAR_PSU_APM_5_DEVICE_ID 3U 145 #define XPAR_PSU_APM_5_BASEADDR 0xFD490000U 146 #define XPAR_PSU_APM_5_HIGHADDR 0xFD49FFFFU 147 #define XPAR_PSU_APM_5_GLOBAL_COUNT_WIDTH 32U 148 #define XPAR_PSU_APM_5_METRICS_SAMPLE_COUNT_WIDTH 32U 149 #define XPAR_PSU_APM_5_ENABLE_EVENT_COUNT 1U 150 #define XPAR_PSU_APM_5_NUM_MONITOR_SLOTS 1U 151 #define XPAR_PSU_APM_5_NUM_OF_COUNTERS 3U 152 #define XPAR_PSU_APM_5_HAVE_SAMPLED_METRIC_CNT 1U 153 #define XPAR_PSU_APM_5_ENABLE_EVENT_LOG 0U 154 #define XPAR_PSU_APM_5_FIFO_AXIS_DEPTH 32U 155 #define XPAR_PSU_APM_5_FIFO_AXIS_TDATA_WIDTH 56U 156 #define XPAR_PSU_APM_5_FIFO_AXIS_TID_WIDTH 1U 157 #define XPAR_PSU_APM_5_METRIC_COUNT_SCALE 1U 158 #define XPAR_PSU_APM_5_ENABLE_ADVANCED 1U 159 #define XPAR_PSU_APM_5_ENABLE_PROFILE 0U 160 #define XPAR_PSU_APM_5_ENABLE_TRACE 0U 161 #define XPAR_PSU_APM_5_S_AXI4_BASEADDR 0x00000000U 162 #define XPAR_PSU_APM_5_S_AXI4_HIGHADDR 0x00000000U 163 #define XPAR_PSU_APM_5_ENABLE_32BIT_FILTER_ID 1U 164 165 166 /******************************************************************/ 167 168 /* Canonical definitions for peripheral PSU_APM_0 */ 169 #define XPAR_AXIPMON_0_DEVICE_ID XPAR_PSU_APM_0_DEVICE_ID 170 #define XPAR_AXIPMON_0_BASEADDR 0xFD0B0000U 171 #define XPAR_AXIPMON_0_HIGHADDR 0xFD0BFFFFU 172 #define XPAR_AXIPMON_0_GLOBAL_COUNT_WIDTH 32U 173 #define XPAR_AXIPMON_0_METRICS_SAMPLE_COUNT_WIDTH 32U 174 #define XPAR_AXIPMON_0_ENABLE_EVENT_COUNT 1U 175 #define XPAR_AXIPMON_0_NUM_MONITOR_SLOTS 6U 176 #define XPAR_AXIPMON_0_NUM_OF_COUNTERS 10U 177 #define XPAR_AXIPMON_0_HAVE_SAMPLED_METRIC_CNT 1U 178 #define XPAR_AXIPMON_0_ENABLE_EVENT_LOG 0U 179 #define XPAR_AXIPMON_0_FIFO_AXIS_DEPTH 32U 180 #define XPAR_AXIPMON_0_FIFO_AXIS_TDATA_WIDTH 56U 181 #define XPAR_AXIPMON_0_FIFO_AXIS_TID_WIDTH 1U 182 #define XPAR_AXIPMON_0_METRIC_COUNT_SCALE 1U 183 #define XPAR_AXIPMON_0_ENABLE_ADVANCED 1U 184 #define XPAR_AXIPMON_0_ENABLE_PROFILE 0U 185 #define XPAR_AXIPMON_0_ENABLE_TRACE 0U 186 #define XPAR_AXIPMON_0_S_AXI4_BASEADDR 0x00000000U 187 #define XPAR_AXIPMON_0_S_AXI4_HIGHADDR 0x00000000U 188 #define XPAR_AXIPMON_0_ENABLE_32BIT_FILTER_ID 1U 189 190 /* Canonical definitions for peripheral PSU_APM_1 */ 191 #define XPAR_AXIPMON_1_DEVICE_ID XPAR_PSU_APM_1_DEVICE_ID 192 #define XPAR_AXIPMON_1_BASEADDR 0xFFA00000U 193 #define XPAR_AXIPMON_1_HIGHADDR 0xFFA0FFFFU 194 #define XPAR_AXIPMON_1_GLOBAL_COUNT_WIDTH 32U 195 #define XPAR_AXIPMON_1_METRICS_SAMPLE_COUNT_WIDTH 32U 196 #define XPAR_AXIPMON_1_ENABLE_EVENT_COUNT 1U 197 #define XPAR_AXIPMON_1_NUM_MONITOR_SLOTS 1U 198 #define XPAR_AXIPMON_1_NUM_OF_COUNTERS 3U 199 #define XPAR_AXIPMON_1_HAVE_SAMPLED_METRIC_CNT 1U 200 #define XPAR_AXIPMON_1_ENABLE_EVENT_LOG 0U 201 #define XPAR_AXIPMON_1_FIFO_AXIS_DEPTH 32U 202 #define XPAR_AXIPMON_1_FIFO_AXIS_TDATA_WIDTH 56U 203 #define XPAR_AXIPMON_1_FIFO_AXIS_TID_WIDTH 1U 204 #define XPAR_AXIPMON_1_METRIC_COUNT_SCALE 1U 205 #define XPAR_AXIPMON_1_ENABLE_ADVANCED 1U 206 #define XPAR_AXIPMON_1_ENABLE_PROFILE 0U 207 #define XPAR_AXIPMON_1_ENABLE_TRACE 0U 208 #define XPAR_AXIPMON_1_S_AXI4_BASEADDR 0x00000000U 209 #define XPAR_AXIPMON_1_S_AXI4_HIGHADDR 0x00000000U 210 #define XPAR_AXIPMON_1_ENABLE_32BIT_FILTER_ID 1U 211 212 /* Canonical definitions for peripheral PSU_APM_2 */ 213 #define XPAR_AXIPMON_2_DEVICE_ID XPAR_PSU_APM_2_DEVICE_ID 214 #define XPAR_AXIPMON_2_BASEADDR 0xFFA10000U 215 #define XPAR_AXIPMON_2_HIGHADDR 0xFFA1FFFFU 216 #define XPAR_AXIPMON_2_GLOBAL_COUNT_WIDTH 32U 217 #define XPAR_AXIPMON_2_METRICS_SAMPLE_COUNT_WIDTH 32U 218 #define XPAR_AXIPMON_2_ENABLE_EVENT_COUNT 1U 219 #define XPAR_AXIPMON_2_NUM_MONITOR_SLOTS 1U 220 #define XPAR_AXIPMON_2_NUM_OF_COUNTERS 3U 221 #define XPAR_AXIPMON_2_HAVE_SAMPLED_METRIC_CNT 1U 222 #define XPAR_AXIPMON_2_ENABLE_EVENT_LOG 0U 223 #define XPAR_AXIPMON_2_FIFO_AXIS_DEPTH 32U 224 #define XPAR_AXIPMON_2_FIFO_AXIS_TDATA_WIDTH 56U 225 #define XPAR_AXIPMON_2_FIFO_AXIS_TID_WIDTH 1U 226 #define XPAR_AXIPMON_2_METRIC_COUNT_SCALE 1U 227 #define XPAR_AXIPMON_2_ENABLE_ADVANCED 1U 228 #define XPAR_AXIPMON_2_ENABLE_PROFILE 0U 229 #define XPAR_AXIPMON_2_ENABLE_TRACE 0U 230 #define XPAR_AXIPMON_2_S_AXI4_BASEADDR 0x00000000U 231 #define XPAR_AXIPMON_2_S_AXI4_HIGHADDR 0x00000000U 232 #define XPAR_AXIPMON_2_ENABLE_32BIT_FILTER_ID 1U 233 234 /* Canonical definitions for peripheral PSU_APM_5 */ 235 #define XPAR_AXIPMON_3_DEVICE_ID XPAR_PSU_APM_5_DEVICE_ID 236 #define XPAR_AXIPMON_3_BASEADDR 0xFD490000U 237 #define XPAR_AXIPMON_3_HIGHADDR 0xFD49FFFFU 238 #define XPAR_AXIPMON_3_GLOBAL_COUNT_WIDTH 32U 239 #define XPAR_AXIPMON_3_METRICS_SAMPLE_COUNT_WIDTH 32U 240 #define XPAR_AXIPMON_3_ENABLE_EVENT_COUNT 1U 241 #define XPAR_AXIPMON_3_NUM_MONITOR_SLOTS 1U 242 #define XPAR_AXIPMON_3_NUM_OF_COUNTERS 3U 243 #define XPAR_AXIPMON_3_HAVE_SAMPLED_METRIC_CNT 1U 244 #define XPAR_AXIPMON_3_ENABLE_EVENT_LOG 0U 245 #define XPAR_AXIPMON_3_FIFO_AXIS_DEPTH 32U 246 #define XPAR_AXIPMON_3_FIFO_AXIS_TDATA_WIDTH 56U 247 #define XPAR_AXIPMON_3_FIFO_AXIS_TID_WIDTH 1U 248 #define XPAR_AXIPMON_3_METRIC_COUNT_SCALE 1U 249 #define XPAR_AXIPMON_3_ENABLE_ADVANCED 1U 250 #define XPAR_AXIPMON_3_ENABLE_PROFILE 0U 251 #define XPAR_AXIPMON_3_ENABLE_TRACE 0U 252 #define XPAR_AXIPMON_3_S_AXI4_BASEADDR 0x00000000U 253 #define XPAR_AXIPMON_3_S_AXI4_HIGHADDR 0x00000000U 254 #define XPAR_AXIPMON_3_ENABLE_32BIT_FILTER_ID 1U 255 256 257 /******************************************************************/ 258 259 /* Definitions for driver CANPS */ 260 #define XPAR_XCANPS_NUM_INSTANCES 2 261 262 /* Definitions for peripheral PSU_CAN_0 */ 263 #define XPAR_PSU_CAN_0_DEVICE_ID 0 264 #define XPAR_PSU_CAN_0_BASEADDR 0xFF060000 265 #define XPAR_PSU_CAN_0_HIGHADDR 0xFF06FFFF 266 #define XPAR_PSU_CAN_0_CAN_CLK_FREQ_HZ 99999001 267 268 269 /* Definitions for peripheral PSU_CAN_1 */ 270 #define XPAR_PSU_CAN_1_DEVICE_ID 1 271 #define XPAR_PSU_CAN_1_BASEADDR 0xFF070000 272 #define XPAR_PSU_CAN_1_HIGHADDR 0xFF07FFFF 273 #define XPAR_PSU_CAN_1_CAN_CLK_FREQ_HZ 99999001 274 275 276 /******************************************************************/ 277 278 /* Canonical definitions for peripheral PSU_CAN_0 */ 279 #define XPAR_XCANPS_0_DEVICE_ID XPAR_PSU_CAN_0_DEVICE_ID 280 #define XPAR_XCANPS_0_BASEADDR 0xFF060000 281 #define XPAR_XCANPS_0_HIGHADDR 0xFF06FFFF 282 #define XPAR_XCANPS_0_CAN_CLK_FREQ_HZ 99999001 283 284 /* Canonical definitions for peripheral PSU_CAN_1 */ 285 #define XPAR_XCANPS_1_DEVICE_ID XPAR_PSU_CAN_1_DEVICE_ID 286 #define XPAR_XCANPS_1_BASEADDR 0xFF070000 287 #define XPAR_XCANPS_1_HIGHADDR 0xFF07FFFF 288 #define XPAR_XCANPS_1_CAN_CLK_FREQ_HZ 99999001 289 290 291 /******************************************************************/ 292 293 /* Definitions for driver CSUDMA */ 294 #define XPAR_XCSUDMA_NUM_INSTANCES 1 295 296 /* Definitions for peripheral PSU_CSUDMA */ 297 #define XPAR_PSU_CSUDMA_DEVICE_ID 0 298 #define XPAR_PSU_CSUDMA_BASEADDR 0xFFC80000 299 #define XPAR_PSU_CSUDMA_HIGHADDR 0xFFC9FFFF 300 #define XPAR_PSU_CSUDMA_CSUDMA_CLK_FREQ_HZ 0 301 302 303 /******************************************************************/ 304 305 #define XPAR_PSU_CSUDMA_DMATYPE 0 306 /* Canonical definitions for peripheral PSU_CSUDMA */ 307 #define XPAR_XCSUDMA_0_DEVICE_ID XPAR_PSU_CSUDMA_DEVICE_ID 308 #define XPAR_XCSUDMA_0_BASEADDR 0xFFC80000 309 #define XPAR_XCSUDMA_0_HIGHADDR 0xFFC9FFFF 310 #define XPAR_XCSUDMA_0_CSUDMA_CLK_FREQ_HZ 0 311 312 313 /******************************************************************/ 314 315 /* Definitions for driver DDRCPSU */ 316 #define XPAR_XDDRCPSU_NUM_INSTANCES 1 317 318 /* Definitions for peripheral PSU_DDRC_0 */ 319 #define XPAR_PSU_DDRC_0_DEVICE_ID 0 320 #define XPAR_PSU_DDRC_0_BASEADDR 0xFD070000 321 #define XPAR_PSU_DDRC_0_HIGHADDR 0xFD070FFF 322 #define XPAR_PSU_DDRC_0_HAS_ECC 0 323 #define XPAR_PSU_DDRC_0_DDRC_CLK_FREQ_HZ 599994019 324 325 326 /******************************************************************/ 327 328 #define XPAR_PSU_DDRC_0_DDR4_ADDR_MAPPING 0 329 #define XPAR_PSU_DDRC_0_DDR_FREQ_MHZ 1199.988037 330 #define XPAR_PSU_DDRC_0_VIDEO_BUFFER_SIZE 0 331 #define XPAR_PSU_DDRC_0_BRC_MAPPING 0 332 #define XPAR_PSU_DDRC_0_DDR_MEMORY_TYPE 4 333 #define XPAR_PSU_DDRC_0_DDR_MEMORY_ADDRESS_MAP 0 334 #define XPAR_PSU_DDRC_0_DDR_DATA_MASK_AND_DBI 7 335 #define XPAR_PSU_DDRC_0_DDR_ADDRESS_MIRRORING 0 336 #define XPAR_PSU_DDRC_0_DDR_2ND_CLOCK 0 337 #define XPAR_PSU_DDRC_0_DDR_PARITY 0 338 #define XPAR_PSU_DDRC_0_DDR_POWER_DOWN_ENABLE 0 339 #define XPAR_PSU_DDRC_0_CLOCK_STOP 0 340 #define XPAR_PSU_DDRC_0_DDR_LOW_POWER_AUTO_SELF_REFRESH 0 341 #define XPAR_PSU_DDRC_0_DDR_TEMP_CONTROLLED_REFRESH 0 342 #define XPAR_PSU_DDRC_0_DDR_MAX_OPERATING_TEMPARATURE 0 343 #define XPAR_PSU_DDRC_0_DDR_FINE_GRANULARITY_REFRESH_MODE 0 344 #define XPAR_PSU_DDRC_0_DDR_SELF_REFRESH_ABORT 0 345 /* Canonical definitions for peripheral PSU_DDRC_0 */ 346 #define XPAR_DDRCPSU_0_DEVICE_ID XPAR_PSU_DDRC_0_DEVICE_ID 347 #define XPAR_DDRCPSU_0_BASEADDR 0xFD070000 348 #define XPAR_DDRCPSU_0_HIGHADDR 0xFD070FFF 349 #define XPAR_DDRCPSU_0_DDRC_CLK_FREQ_HZ 599994019 350 351 352 /******************************************************************/ 353 354 #define XPAR_DDRCPSU_0_DDR4_ADDR_MAPPING 0 355 #define XPAR_DDRCPSU_0_DDR_FREQ_MHZ 1199.988037 356 #define XPAR_DDRCPSU_0_VIDEO_BUFFER_SIZE 0 357 #define XPAR_DDRCPSU_0_BRC_MAPPING 0 358 #define XPAR_DDRCPSU_0_DDR_MEMORY_TYPE 4 359 #define XPAR_DDRCPSU_0_DDR_MEMORY_ADDRESS_MAP 0 360 #define XPAR_DDRCPSU_0_DDR_DATA_MASK_AND_DBI 7 361 #define XPAR_DDRCPSU_0_DDR_ADDRESS_MIRRORING 0 362 #define XPAR_DDRCPSU_0_DDR_2ND_CLOCK 0 363 #define XPAR_DDRCPSU_0_DDR_PARITY 0 364 #define XPAR_DDRCPSU_0_DDR_POWER_DOWN_ENABLE 0 365 #define XPAR_DDRCPSU_0_CLOCK_STOP 0 366 #define XPAR_DDRCPSU_0_DDR_LOW_POWER_AUTO_SELF_REFRESH 0 367 #define XPAR_DDRCPSU_0_DDR_TEMP_CONTROLLED_REFRESH 0 368 #define XPAR_DDRCPSU_0_DDR_MAX_OPERATING_TEMPARATURE 0 369 #define XPAR_DDRCPSU_0_DDR_FINE_GRANULARITY_REFRESH_MODE 0 370 #define XPAR_DDRCPSU_0_DDR_SELF_REFRESH_ABORT 0 371 /* Definitions for driver DPDMA */ 372 #define XPAR_XDPDMA_NUM_INSTANCES 1 373 374 /* Definitions for peripheral PSU_DPDMA */ 375 #define XPAR_PSU_DPDMA_DEVICE_ID 0 376 #define XPAR_PSU_DPDMA_BASEADDR 0xFD4C0000 377 #define XPAR_PSU_DPDMA_HIGHADDR 0xFD4CFFFF 378 379 380 /******************************************************************/ 381 382 /* Canonical definitions for peripheral PSU_DPDMA */ 383 #define XPAR_XDPDMA_0_DEVICE_ID XPAR_PSU_DPDMA_DEVICE_ID 384 #define XPAR_XDPDMA_0_BASEADDR 0xFD4C0000 385 #define XPAR_XDPDMA_0_HIGHADDR 0xFD4CFFFF 386 387 388 /******************************************************************/ 389 390 /* Definitions for driver EMACPS */ 391 #define XPAR_XEMACPS_NUM_INSTANCES 1 392 393 /* Definitions for peripheral PSU_ETHERNET_3 */ 394 #define XPAR_PSU_ETHERNET_3_DEVICE_ID 0 395 #define XPAR_PSU_ETHERNET_3_BASEADDR 0xFF0E0000 396 #define XPAR_PSU_ETHERNET_3_HIGHADDR 0xFF0EFFFF 397 #define XPAR_PSU_ETHERNET_3_ENET_CLK_FREQ_HZ 124998749 398 #define XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV0 12 399 #define XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV1 1 400 #define XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV0 60 401 #define XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV1 1 402 #define XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV0 60 403 #define XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV1 10 404 #define XPAR_PSU_ETHERNET_3_ENET_TSU_CLK_FREQ_HZ 249997498 405 406 407 /******************************************************************/ 408 409 #define XPAR_PSU_ETHERNET_3_IS_CACHE_COHERENT 0 410 #define XPAR_XEMACPS_0_IS_CACHE_COHERENT 0 411 #define XPAR_PSU_ETHERNET_3_REF_CLK 0xff 412 /* Canonical definitions for peripheral PSU_ETHERNET_3 */ 413 #define XPAR_XEMACPS_0_DEVICE_ID XPAR_PSU_ETHERNET_3_DEVICE_ID 414 #define XPAR_XEMACPS_0_BASEADDR 0xFF0E0000 415 #define XPAR_XEMACPS_0_HIGHADDR 0xFF0EFFFF 416 #define XPAR_XEMACPS_0_ENET_CLK_FREQ_HZ 124998749 417 #define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV0 12 418 #define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV1 1 419 #define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV0 60 420 #define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV1 1 421 #define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV0 60 422 #define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV1 10 423 #define XPAR_XEMACPS_0_ENET_TSU_CLK_FREQ_HZ 249997498 424 425 426 /******************************************************************/ 427 428 429 /* Definitions for peripheral PSU_AFI_0 */ 430 #define XPAR_PSU_AFI_0_S_AXI_BASEADDR 0xFD360000 431 #define XPAR_PSU_AFI_0_S_AXI_HIGHADDR 0xFD36FFFF 432 433 434 /* Definitions for peripheral PSU_AFI_1 */ 435 #define XPAR_PSU_AFI_1_S_AXI_BASEADDR 0xFD370000 436 #define XPAR_PSU_AFI_1_S_AXI_HIGHADDR 0xFD37FFFF 437 438 439 /* Definitions for peripheral PSU_AFI_2 */ 440 #define XPAR_PSU_AFI_2_S_AXI_BASEADDR 0xFD380000 441 #define XPAR_PSU_AFI_2_S_AXI_HIGHADDR 0xFD38FFFF 442 443 444 /* Definitions for peripheral PSU_AFI_3 */ 445 #define XPAR_PSU_AFI_3_S_AXI_BASEADDR 0xFD390000 446 #define XPAR_PSU_AFI_3_S_AXI_HIGHADDR 0xFD39FFFF 447 448 449 /* Definitions for peripheral PSU_AFI_4 */ 450 #define XPAR_PSU_AFI_4_S_AXI_BASEADDR 0xFD3A0000 451 #define XPAR_PSU_AFI_4_S_AXI_HIGHADDR 0xFD3AFFFF 452 453 454 /* Definitions for peripheral PSU_AFI_5 */ 455 #define XPAR_PSU_AFI_5_S_AXI_BASEADDR 0xFD3B0000 456 #define XPAR_PSU_AFI_5_S_AXI_HIGHADDR 0xFD3BFFFF 457 458 459 /* Definitions for peripheral PSU_AFI_6 */ 460 #define XPAR_PSU_AFI_6_S_AXI_BASEADDR 0xFF9B0000 461 #define XPAR_PSU_AFI_6_S_AXI_HIGHADDR 0xFF9BFFFF 462 463 464 /* Definitions for peripheral PSU_APU */ 465 #define XPAR_PSU_APU_S_AXI_BASEADDR 0xFD5C0000 466 #define XPAR_PSU_APU_S_AXI_HIGHADDR 0xFD5CFFFF 467 468 469 /* Definitions for peripheral PSU_CCI_GPV */ 470 #define XPAR_PSU_CCI_GPV_S_AXI_BASEADDR 0xFD6E0000 471 #define XPAR_PSU_CCI_GPV_S_AXI_HIGHADDR 0xFD6EFFFF 472 473 474 /* Definitions for peripheral PSU_CCI_REG */ 475 #define XPAR_PSU_CCI_REG_S_AXI_BASEADDR 0xFD5E0000 476 #define XPAR_PSU_CCI_REG_S_AXI_HIGHADDR 0xFD5EFFFF 477 478 479 /* Definitions for peripheral PSU_CRL_APB */ 480 #define XPAR_PSU_CRL_APB_S_AXI_BASEADDR 0xFF5E0000 481 #define XPAR_PSU_CRL_APB_S_AXI_HIGHADDR 0xFF85FFFF 482 483 484 /* Definitions for peripheral PSU_CSU_0 */ 485 #define XPAR_PSU_CSU_0_S_AXI_BASEADDR 0xFFCA0000 486 #define XPAR_PSU_CSU_0_S_AXI_HIGHADDR 0xFFCAFFFF 487 488 489 /* Definitions for peripheral PSU_CTRL_IPI */ 490 #define XPAR_PSU_CTRL_IPI_S_AXI_BASEADDR 0xFF380000 491 #define XPAR_PSU_CTRL_IPI_S_AXI_HIGHADDR 0xFF3FFFFF 492 493 494 /* Definitions for peripheral PSU_DDR_PHY */ 495 #define XPAR_PSU_DDR_PHY_S_AXI_BASEADDR 0xFD080000 496 #define XPAR_PSU_DDR_PHY_S_AXI_HIGHADDR 0xFD08FFFF 497 498 499 /* Definitions for peripheral PSU_DDR_QOS_CTRL */ 500 #define XPAR_PSU_DDR_QOS_CTRL_S_AXI_BASEADDR 0xFD090000 501 #define XPAR_PSU_DDR_QOS_CTRL_S_AXI_HIGHADDR 0xFD09FFFF 502 503 504 /* Definitions for peripheral PSU_DDR_XMPU0_CFG */ 505 #define XPAR_PSU_DDR_XMPU0_CFG_S_AXI_BASEADDR 0xFD000000 506 #define XPAR_PSU_DDR_XMPU0_CFG_S_AXI_HIGHADDR 0xFD00FFFF 507 508 509 /* Definitions for peripheral PSU_DDR_XMPU1_CFG */ 510 #define XPAR_PSU_DDR_XMPU1_CFG_S_AXI_BASEADDR 0xFD010000 511 #define XPAR_PSU_DDR_XMPU1_CFG_S_AXI_HIGHADDR 0xFD01FFFF 512 513 514 /* Definitions for peripheral PSU_DDR_XMPU2_CFG */ 515 #define XPAR_PSU_DDR_XMPU2_CFG_S_AXI_BASEADDR 0xFD020000 516 #define XPAR_PSU_DDR_XMPU2_CFG_S_AXI_HIGHADDR 0xFD02FFFF 517 518 519 /* Definitions for peripheral PSU_DDR_XMPU3_CFG */ 520 #define XPAR_PSU_DDR_XMPU3_CFG_S_AXI_BASEADDR 0xFD030000 521 #define XPAR_PSU_DDR_XMPU3_CFG_S_AXI_HIGHADDR 0xFD03FFFF 522 523 524 /* Definitions for peripheral PSU_DDR_XMPU4_CFG */ 525 #define XPAR_PSU_DDR_XMPU4_CFG_S_AXI_BASEADDR 0xFD040000 526 #define XPAR_PSU_DDR_XMPU4_CFG_S_AXI_HIGHADDR 0xFD04FFFF 527 528 529 /* Definitions for peripheral PSU_DDR_XMPU5_CFG */ 530 #define XPAR_PSU_DDR_XMPU5_CFG_S_AXI_BASEADDR 0xFD050000 531 #define XPAR_PSU_DDR_XMPU5_CFG_S_AXI_HIGHADDR 0xFD05FFFF 532 533 534 /* Definitions for peripheral PSU_EFUSE */ 535 #define XPAR_PSU_EFUSE_S_AXI_BASEADDR 0xFFCC0000 536 #define XPAR_PSU_EFUSE_S_AXI_HIGHADDR 0xFFCCFFFF 537 538 539 /* Definitions for peripheral PSU_FPD_GPV */ 540 #define XPAR_PSU_FPD_GPV_S_AXI_BASEADDR 0xFD700000 541 #define XPAR_PSU_FPD_GPV_S_AXI_HIGHADDR 0xFD7FFFFF 542 543 544 /* Definitions for peripheral PSU_FPD_SLCR */ 545 #define XPAR_PSU_FPD_SLCR_S_AXI_BASEADDR 0xFD610000 546 #define XPAR_PSU_FPD_SLCR_S_AXI_HIGHADDR 0xFD68FFFF 547 548 549 /* Definitions for peripheral PSU_FPD_SLCR_SECURE */ 550 #define XPAR_PSU_FPD_SLCR_SECURE_S_AXI_BASEADDR 0xFD690000 551 #define XPAR_PSU_FPD_SLCR_SECURE_S_AXI_HIGHADDR 0xFD6CFFFF 552 553 554 /* Definitions for peripheral PSU_FPD_XMPU_CFG */ 555 #define XPAR_PSU_FPD_XMPU_CFG_S_AXI_BASEADDR 0xFD5D0000 556 #define XPAR_PSU_FPD_XMPU_CFG_S_AXI_HIGHADDR 0xFD5DFFFF 557 558 559 /* Definitions for peripheral PSU_FPD_XMPU_SINK */ 560 #define XPAR_PSU_FPD_XMPU_SINK_S_AXI_BASEADDR 0xFD4F0000 561 #define XPAR_PSU_FPD_XMPU_SINK_S_AXI_HIGHADDR 0xFD4FFFFF 562 563 564 /* Definitions for peripheral PSU_GPU */ 565 #define XPAR_PSU_GPU_S_AXI_BASEADDR 0xFD4B0000 566 #define XPAR_PSU_GPU_S_AXI_HIGHADDR 0xFD4BFFFF 567 568 569 /* Definitions for peripheral PSU_IOU_SCNTR */ 570 #define XPAR_PSU_IOU_SCNTR_S_AXI_BASEADDR 0xFF250000 571 #define XPAR_PSU_IOU_SCNTR_S_AXI_HIGHADDR 0xFF25FFFF 572 573 574 /* Definitions for peripheral PSU_IOU_SCNTRS */ 575 #define XPAR_PSU_IOU_SCNTRS_S_AXI_BASEADDR 0xFF260000 576 #define XPAR_PSU_IOU_SCNTRS_S_AXI_HIGHADDR 0xFF26FFFF 577 578 579 /* Definitions for peripheral PSU_IOUSECURE_SLCR */ 580 #define XPAR_PSU_IOUSECURE_SLCR_S_AXI_BASEADDR 0xFF240000 581 #define XPAR_PSU_IOUSECURE_SLCR_S_AXI_HIGHADDR 0xFF24FFFF 582 583 584 /* Definitions for peripheral PSU_IOUSLCR_0 */ 585 #define XPAR_PSU_IOUSLCR_0_S_AXI_BASEADDR 0xFF180000 586 #define XPAR_PSU_IOUSLCR_0_S_AXI_HIGHADDR 0xFF23FFFF 587 588 589 /* Definitions for peripheral PSU_LPD_SLCR */ 590 #define XPAR_PSU_LPD_SLCR_S_AXI_BASEADDR 0xFF410000 591 #define XPAR_PSU_LPD_SLCR_S_AXI_HIGHADDR 0xFF4AFFFF 592 593 594 /* Definitions for peripheral PSU_LPD_SLCR_SECURE */ 595 #define XPAR_PSU_LPD_SLCR_SECURE_S_AXI_BASEADDR 0xFF4B0000 596 #define XPAR_PSU_LPD_SLCR_SECURE_S_AXI_HIGHADDR 0xFF4DFFFF 597 598 599 /* Definitions for peripheral PSU_LPD_XPPU */ 600 #define XPAR_PSU_LPD_XPPU_S_AXI_BASEADDR 0xFF980000 601 #define XPAR_PSU_LPD_XPPU_S_AXI_HIGHADDR 0xFF99FFFF 602 603 604 /* Definitions for peripheral PSU_LPD_XPPU_SINK */ 605 #define XPAR_PSU_LPD_XPPU_SINK_S_AXI_BASEADDR 0xFF9C0000 606 #define XPAR_PSU_LPD_XPPU_SINK_S_AXI_HIGHADDR 0xFF9CFFFF 607 608 609 /* Definitions for peripheral PSU_MBISTJTAG */ 610 #define XPAR_PSU_MBISTJTAG_S_AXI_BASEADDR 0xFFCF0000 611 #define XPAR_PSU_MBISTJTAG_S_AXI_HIGHADDR 0xFFCFFFFF 612 613 614 /* Definitions for peripheral PSU_MESSAGE_BUFFERS */ 615 #define XPAR_PSU_MESSAGE_BUFFERS_S_AXI_BASEADDR 0xFF990000 616 #define XPAR_PSU_MESSAGE_BUFFERS_S_AXI_HIGHADDR 0xFF99FFFF 617 618 619 /* Definitions for peripheral PSU_OCM */ 620 #define XPAR_PSU_OCM_S_AXI_BASEADDR 0xFF960000 621 #define XPAR_PSU_OCM_S_AXI_HIGHADDR 0xFF96FFFF 622 623 624 /* Definitions for peripheral PSU_OCM_RAM_0 */ 625 #define XPAR_PSU_OCM_RAM_0_S_AXI_BASEADDR 0xFFFC0000 626 #define XPAR_PSU_OCM_RAM_0_S_AXI_HIGHADDR 0xFFFFFFFF 627 628 629 /* Definitions for peripheral PSU_OCM_XMPU_CFG */ 630 #define XPAR_PSU_OCM_XMPU_CFG_S_AXI_BASEADDR 0xFFA70000 631 #define XPAR_PSU_OCM_XMPU_CFG_S_AXI_HIGHADDR 0xFFA7FFFF 632 633 634 /* Definitions for peripheral PSU_PMU_GLOBAL_0 */ 635 #define XPAR_PSU_PMU_GLOBAL_0_S_AXI_BASEADDR 0xFFD80000 636 #define XPAR_PSU_PMU_GLOBAL_0_S_AXI_HIGHADDR 0xFFDBFFFF 637 638 639 /* Definitions for peripheral PSU_QSPI_LINEAR_0 */ 640 #define XPAR_PSU_QSPI_LINEAR_0_S_AXI_BASEADDR 0xC0000000 641 #define XPAR_PSU_QSPI_LINEAR_0_S_AXI_HIGHADDR 0xDFFFFFFF 642 643 644 /* Definitions for peripheral PSU_R5_0_ATCM */ 645 #define XPAR_PSU_R5_0_ATCM_S_AXI_BASEADDR 0x00000000 646 #define XPAR_PSU_R5_0_ATCM_S_AXI_HIGHADDR 0x0000FFFF 647 648 649 /* Definitions for peripheral PSU_R5_0_BTCM */ 650 #define XPAR_PSU_R5_0_BTCM_S_AXI_BASEADDR 0x00020000 651 #define XPAR_PSU_R5_0_BTCM_S_AXI_HIGHADDR 0x0002FFFF 652 653 654 /* Definitions for peripheral PSU_R5_DDR_0 */ 655 #define XPAR_PSU_R5_DDR_0_S_AXI_BASEADDR 0x00100000 656 #define XPAR_PSU_R5_DDR_0_S_AXI_HIGHADDR 0x7FFFFFFF 657 658 659 /* Definitions for peripheral PSU_R5_TCM_RAM_0 */ 660 #define XPAR_PSU_R5_TCM_RAM_0_S_AXI_BASEADDR 0x00000000 661 #define XPAR_PSU_R5_TCM_RAM_0_S_AXI_HIGHADDR 0x0003FFFF 662 663 664 /* Definitions for peripheral PSU_RPU */ 665 #define XPAR_PSU_RPU_S_AXI_BASEADDR 0xFF9A0000 666 #define XPAR_PSU_RPU_S_AXI_HIGHADDR 0xFF9AFFFF 667 668 669 /* Definitions for peripheral PSU_RSA */ 670 #define XPAR_PSU_RSA_S_AXI_BASEADDR 0xFFCE0000 671 #define XPAR_PSU_RSA_S_AXI_HIGHADDR 0xFFCEFFFF 672 673 674 /* Definitions for peripheral PSU_SERDES */ 675 #define XPAR_PSU_SERDES_S_AXI_BASEADDR 0xFD400000 676 #define XPAR_PSU_SERDES_S_AXI_HIGHADDR 0xFD47FFFF 677 678 679 /* Definitions for peripheral PSU_SIOU */ 680 #define XPAR_PSU_SIOU_S_AXI_BASEADDR 0xFD3D0000 681 #define XPAR_PSU_SIOU_S_AXI_HIGHADDR 0xFD3DFFFF 682 683 684 /* Definitions for peripheral PSU_SMMU_GPV */ 685 #define XPAR_PSU_SMMU_GPV_S_AXI_BASEADDR 0xFD800000 686 #define XPAR_PSU_SMMU_GPV_S_AXI_HIGHADDR 0xFDFFFFFF 687 688 689 /* Definitions for peripheral PSU_SMMU_REG */ 690 #define XPAR_PSU_SMMU_REG_S_AXI_BASEADDR 0xFD5F0000 691 #define XPAR_PSU_SMMU_REG_S_AXI_HIGHADDR 0xFD5FFFFF 692 693 694 /* Definitions for peripheral PSU_USB_0 */ 695 #define XPAR_PSU_USB_0_S_AXI_BASEADDR 0xFF9D0000 696 #define XPAR_PSU_USB_0_S_AXI_HIGHADDR 0xFF9DFFFF 697 698 699 /******************************************************************/ 700 701 /* Definitions for driver GPIOPS */ 702 #define XPAR_XGPIOPS_NUM_INSTANCES 1 703 704 /* Definitions for peripheral PSU_GPIO_0 */ 705 #define XPAR_PSU_GPIO_0_DEVICE_ID 0 706 #define XPAR_PSU_GPIO_0_BASEADDR 0xFF0A0000 707 #define XPAR_PSU_GPIO_0_HIGHADDR 0xFF0AFFFF 708 709 710 /******************************************************************/ 711 712 /* Canonical definitions for peripheral PSU_GPIO_0 */ 713 #define XPAR_XGPIOPS_0_DEVICE_ID XPAR_PSU_GPIO_0_DEVICE_ID 714 #define XPAR_XGPIOPS_0_BASEADDR 0xFF0A0000 715 #define XPAR_XGPIOPS_0_HIGHADDR 0xFF0AFFFF 716 717 718 /******************************************************************/ 719 720 /* Definitions for driver IICPS */ 721 #define XPAR_XIICPS_NUM_INSTANCES 1 722 723 /* Definitions for peripheral PSU_I2C_1 */ 724 #define XPAR_PSU_I2C_1_DEVICE_ID 0 725 #define XPAR_PSU_I2C_1_BASEADDR 0xFF030000 726 #define XPAR_PSU_I2C_1_HIGHADDR 0xFF03FFFF 727 #define XPAR_PSU_I2C_1_I2C_CLK_FREQ_HZ 99999001 728 729 730 /******************************************************************/ 731 732 /* Canonical definitions for peripheral PSU_I2C_1 */ 733 #define XPAR_XIICPS_0_DEVICE_ID XPAR_PSU_I2C_1_DEVICE_ID 734 #define XPAR_XIICPS_0_BASEADDR 0xFF030000 735 #define XPAR_XIICPS_0_HIGHADDR 0xFF03FFFF 736 #define XPAR_XIICPS_0_I2C_CLK_FREQ_HZ 99999001 737 738 739 /******************************************************************/ 740 741 /* Definition for input Clock */ 742 #define XPAR_PSU_I2C_1_REF_CLK I2C1_REF 743 #define XPAR_XIPIPSU_NUM_INSTANCES 1U 744 745 /* Parameter definitions for peripheral psu_ipi_1 */ 746 #define XPAR_PSU_IPI_1_DEVICE_ID 0U 747 #define XPAR_PSU_IPI_1_S_AXI_BASEADDR 0xFF310000U 748 #define XPAR_PSU_IPI_1_BIT_MASK 0x00000100U 749 #define XPAR_PSU_IPI_1_BUFFER_INDEX 0U 750 #define XPAR_PSU_IPI_1_INT_ID 65U 751 752 /* Canonical definitions for peripheral psu_ipi_1 */ 753 #define XPAR_XIPIPSU_0_DEVICE_ID XPAR_PSU_IPI_1_DEVICE_ID 754 #define XPAR_XIPIPSU_0_BASE_ADDRESS XPAR_PSU_IPI_1_S_AXI_BASEADDR 755 #define XPAR_XIPIPSU_0_BIT_MASK XPAR_PSU_IPI_1_BIT_MASK 756 #define XPAR_XIPIPSU_0_BUFFER_INDEX XPAR_PSU_IPI_1_BUFFER_INDEX 757 #define XPAR_XIPIPSU_0_INT_ID XPAR_PSU_IPI_1_INT_ID 758 759 #define XPAR_XIPIPSU_NUM_TARGETS 7U 760 761 #define XPAR_PSU_IPI_0_BIT_MASK 0x00000001U 762 #define XPAR_PSU_IPI_0_BUFFER_INDEX 2U 763 #define XPAR_PSU_IPI_1_BIT_MASK 0x00000100U 764 #define XPAR_PSU_IPI_1_BUFFER_INDEX 0U 765 #define XPAR_PSU_IPI_2_BIT_MASK 0x00000200U 766 #define XPAR_PSU_IPI_2_BUFFER_INDEX 1U 767 #define XPAR_PSU_IPI_3_BIT_MASK 0x00010000U 768 #define XPAR_PSU_IPI_3_BUFFER_INDEX 7U 769 #define XPAR_PSU_IPI_4_BIT_MASK 0x00020000U 770 #define XPAR_PSU_IPI_4_BUFFER_INDEX 7U 771 #define XPAR_PSU_IPI_5_BIT_MASK 0x00040000U 772 #define XPAR_PSU_IPI_5_BUFFER_INDEX 7U 773 #define XPAR_PSU_IPI_6_BIT_MASK 0x00080000U 774 #define XPAR_PSU_IPI_6_BUFFER_INDEX 7U 775 /* Target List for referring to processor IPI Targets */ 776 777 #define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH0_MASK XPAR_PSU_IPI_0_BIT_MASK 778 #define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH0_INDEX 0U 779 780 #define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH0_MASK XPAR_PSU_IPI_0_BIT_MASK 781 #define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH0_INDEX 0U 782 783 #define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH0_MASK XPAR_PSU_IPI_0_BIT_MASK 784 #define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH0_INDEX 0U 785 786 #define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH0_MASK XPAR_PSU_IPI_0_BIT_MASK 787 #define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH0_INDEX 0U 788 789 #define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_0_CH0_MASK XPAR_PSU_IPI_1_BIT_MASK 790 #define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_0_CH0_INDEX 1U 791 792 #define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_1_CH0_MASK XPAR_PSU_IPI_2_BIT_MASK 793 #define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_1_CH0_INDEX 2U 794 795 #define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH0_MASK XPAR_PSU_IPI_3_BIT_MASK 796 #define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH0_INDEX 3U 797 #define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH1_MASK XPAR_PSU_IPI_4_BIT_MASK 798 #define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH1_INDEX 4U 799 #define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH2_MASK XPAR_PSU_IPI_5_BIT_MASK 800 #define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH2_INDEX 5U 801 #define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH3_MASK XPAR_PSU_IPI_6_BIT_MASK 802 #define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH3_INDEX 6U 803 804 /* Definitions for driver PCIEPSU */ 805 #define XPAR_XPCIEPSU_NUM_INSTANCES 6 806 807 /* Definitions for peripheral PSU_PCIE */ 808 #define XPAR_PSU_PCIE_DEVICE_ID 0 809 #define XPAR_PSU_PCIE_BASEADDR 0xFD0E0000 810 #define XPAR_PSU_PCIE_HIGHADDR 0xFD0EFFFF 811 812 813 /* Definitions for peripheral PSU_PCIE_ATTRIB_0 */ 814 #define XPAR_PSU_PCIE_ATTRIB_0_DEVICE_ID 1 815 #define XPAR_PSU_PCIE_ATTRIB_0_BASEADDR 0xFD480000 816 #define XPAR_PSU_PCIE_ATTRIB_0_HIGHADDR 0xFD48FFFF 817 818 819 /* Definitions for peripheral PSU_PCIE_DMA */ 820 #define XPAR_PSU_PCIE_DMA_DEVICE_ID 2 821 #define XPAR_PSU_PCIE_DMA_BASEADDR 0xFD0F0000 822 #define XPAR_PSU_PCIE_DMA_HIGHADDR 0xFD0FFFFF 823 824 825 /* Definitions for peripheral PSU_PCIE_HIGH1 */ 826 #define XPAR_PSU_PCIE_HIGH1_DEVICE_ID 3 827 #define XPAR_PSU_PCIE_HIGH1_BASEADDR 0x600000000 828 #define XPAR_PSU_PCIE_HIGH1_HIGHADDR 0x7FFFFFFFF 829 830 831 /* Definitions for peripheral PSU_PCIE_HIGH2 */ 832 #define XPAR_PSU_PCIE_HIGH2_DEVICE_ID 4 833 #define XPAR_PSU_PCIE_HIGH2_BASEADDR 0x8000000000 834 #define XPAR_PSU_PCIE_HIGH2_HIGHADDR 0xBFFFFFFFFF 835 836 837 /* Definitions for peripheral PSU_PCIE_LOW */ 838 #define XPAR_PSU_PCIE_LOW_DEVICE_ID 5 839 #define XPAR_PSU_PCIE_LOW_BASEADDR 0xE0000000 840 #define XPAR_PSU_PCIE_LOW_HIGHADDR 0xEFFFFFFF 841 842 843 /******************************************************************/ 844 845 #define XPAR_PSU_PCIE_PCIE_MODE 0x1 846 847 /* Canonical definitions for peripheral PSU_PCIE */ 848 #define XPAR_XPCIEPSU_0_DEVICE_ID XPAR_PSU_PCIE_DEVICE_ID 849 #define XPAR_XPCIEPSU_0_BASEADDR 0xFD0E0000 850 #define XPAR_XPCIEPSU_0_HIGHADDR 0xFD0EFFFF 851 #define XPAR_XPCIEPSU_0_PCIE_MODE Root Port 852 853 /* Canonical definitions for peripheral PSU_PCIE_ATTRIB_0 */ 854 #define XPAR_XPCIEPSU_1_DEVICE_ID XPAR_PSU_PCIE_ATTRIB_0_DEVICE_ID 855 #define XPAR_XPCIEPSU_1_BASEADDR 0xFD480000 856 #define XPAR_XPCIEPSU_1_HIGHADDR 0xFD48FFFF 857 #define XPAR_XPCIEPSU_1_PCIE_MODE 0 858 859 /* Canonical definitions for peripheral PSU_PCIE_DMA */ 860 #define XPAR_XPCIEPSU_2_DEVICE_ID XPAR_PSU_PCIE_DMA_DEVICE_ID 861 #define XPAR_XPCIEPSU_2_BASEADDR 0xFD0F0000 862 #define XPAR_XPCIEPSU_2_HIGHADDR 0xFD0FFFFF 863 #define XPAR_XPCIEPSU_2_PCIE_MODE 0 864 865 /* Canonical definitions for peripheral PSU_PCIE_HIGH1 */ 866 #define XPAR_XPCIEPSU_3_DEVICE_ID XPAR_PSU_PCIE_HIGH1_DEVICE_ID 867 #define XPAR_XPCIEPSU_3_BASEADDR 0x600000000 868 #define XPAR_XPCIEPSU_3_HIGHADDR 0x7FFFFFFFF 869 #define XPAR_XPCIEPSU_3_PCIE_MODE 0 870 871 /* Canonical definitions for peripheral PSU_PCIE_HIGH2 */ 872 #define XPAR_XPCIEPSU_4_DEVICE_ID XPAR_PSU_PCIE_HIGH2_DEVICE_ID 873 #define XPAR_XPCIEPSU_4_BASEADDR 0x8000000000 874 #define XPAR_XPCIEPSU_4_HIGHADDR 0xBFFFFFFFFF 875 #define XPAR_XPCIEPSU_4_PCIE_MODE 0 876 877 /* Canonical definitions for peripheral PSU_PCIE_LOW */ 878 #define XPAR_XPCIEPSU_5_DEVICE_ID XPAR_PSU_PCIE_LOW_DEVICE_ID 879 #define XPAR_XPCIEPSU_5_BASEADDR 0xE0000000 880 #define XPAR_XPCIEPSU_5_HIGHADDR 0xEFFFFFFF 881 #define XPAR_XPCIEPSU_5_PCIE_MODE 0 882 883 884 /******************************************************************/ 885 886 /* Definitions for driver QSPIPSU */ 887 #define XPAR_XQSPIPSU_NUM_INSTANCES 1 888 889 /* Definitions for peripheral PSU_QSPI_0 */ 890 #define XPAR_PSU_QSPI_0_DEVICE_ID 0 891 #define XPAR_PSU_QSPI_0_BASEADDR 0xFF0F0000 892 #define XPAR_PSU_QSPI_0_HIGHADDR 0xFF0FFFFF 893 #define XPAR_PSU_QSPI_0_QSPI_CLK_FREQ_HZ 299997009 894 #define XPAR_PSU_QSPI_0_QSPI_MODE 0 895 #define XPAR_PSU_QSPI_0_QSPI_BUS_WIDTH 2 896 897 898 /******************************************************************/ 899 900 #define XPAR_PSU_QSPI_0_IS_CACHE_COHERENT 0 901 #define XPAR_PSU_QSPI_0_REF_CLK 0xff 902 /* Canonical definitions for peripheral PSU_QSPI_0 */ 903 #define XPAR_XQSPIPSU_0_DEVICE_ID XPAR_PSU_QSPI_0_DEVICE_ID 904 #define XPAR_XQSPIPSU_0_BASEADDR 0xFF0F0000 905 #define XPAR_XQSPIPSU_0_HIGHADDR 0xFF0FFFFF 906 #define XPAR_XQSPIPSU_0_QSPI_CLK_FREQ_HZ 299997009 907 #define XPAR_XQSPIPSU_0_QSPI_MODE 0 908 #define XPAR_XQSPIPSU_0_QSPI_BUS_WIDTH 2 909 #define XPAR_XQSPIPSU_0_IS_CACHE_COHERENT 0 910 911 912 /******************************************************************/ 913 914 /* Definitions for driver RESETPS and CLOCKPS */ 915 #define XPAR_XCRPSU_NUM_INSTANCES 1U 916 917 /* Definitions for peripheral PSU_CR_0 */ 918 #define XPAR_PSU_CR_DEVICE_ID 0 919 920 /******************************************************************/ 921 922 /* Definitions for peripheral PSU_CRF_APB */ 923 #define XPAR_PSU_CRF_APB_S_AXI_BASEADDR 0xFD1A0000 924 #define XPAR_PSU_CRF_APB_S_AXI_HIGHADDR 0xFD2DFFFF 925 926 927 /******************************************************************/ 928 929 /* Canonical definitions for peripheral PSU_CR_0 */ 930 #define XPAR_XCRPSU_0_DEVICE_ID 0 931 932 /******************************************************************/ 933 934 935 /* Definitions for peripheral PSU_PMU_IOMODULE */ 936 #define XPAR_PSU_PMU_IOMODULE_S_AXI_BASEADDR 0xFFD40000 937 #define XPAR_PSU_PMU_IOMODULE_S_AXI_HIGHADDR 0xFFD5FFFF 938 939 940 /* Definitions for peripheral PSU_LPD_SLCR */ 941 #define XPAR_PSU_LPD_SLCR_S_AXI_BASEADDR 0xFF410000 942 #define XPAR_PSU_LPD_SLCR_S_AXI_HIGHADDR 0xFF4AFFFF 943 944 945 /******************************************************************/ 946 947 /* Definitions for driver RTCPSU */ 948 #define XPAR_XRTCPSU_NUM_INSTANCES 1 949 950 /* Definitions for peripheral PSU_RTC */ 951 #define XPAR_PSU_RTC_DEVICE_ID 0 952 #define XPAR_PSU_RTC_BASEADDR 0xFFA60000 953 #define XPAR_PSU_RTC_HIGHADDR 0xFFA6FFFF 954 955 956 /******************************************************************/ 957 958 /* Canonical definitions for peripheral PSU_RTC */ 959 #define XPAR_XRTCPSU_0_DEVICE_ID XPAR_PSU_RTC_DEVICE_ID 960 #define XPAR_XRTCPSU_0_BASEADDR 0xFFA60000 961 #define XPAR_XRTCPSU_0_HIGHADDR 0xFFA6FFFF 962 963 964 /******************************************************************/ 965 966 /* Definitions for driver SCUGIC */ 967 #define XPAR_XSCUGIC_NUM_INSTANCES 1U 968 969 /* Definitions for peripheral PSU_RCPU_GIC */ 970 #define XPAR_PSU_RCPU_GIC_DEVICE_ID 0U 971 #define XPAR_PSU_RCPU_GIC_BASEADDR 0xF9001000U 972 #define XPAR_PSU_RCPU_GIC_HIGHADDR 0xF9001FFFU 973 #define XPAR_PSU_RCPU_GIC_DIST_BASEADDR 0xF9000000U 974 975 976 /******************************************************************/ 977 978 /* Canonical definitions for peripheral PSU_RCPU_GIC */ 979 #define XPAR_SCUGIC_0_DEVICE_ID 0U 980 #define XPAR_SCUGIC_0_CPU_BASEADDR 0xF9001000U 981 #define XPAR_SCUGIC_0_CPU_HIGHADDR 0xF9001FFFU 982 #define XPAR_SCUGIC_0_DIST_BASEADDR 0xF9000000U 983 984 985 /******************************************************************/ 986 987 /* Definitions for driver SDPS */ 988 #define XPAR_XSDPS_NUM_INSTANCES 2 989 990 /* Definitions for peripheral PSU_SD_0 */ 991 #define XPAR_PSU_SD_0_DEVICE_ID 0 992 #define XPAR_PSU_SD_0_BASEADDR 0xFF160000 993 #define XPAR_PSU_SD_0_HIGHADDR 0xFF16FFFF 994 #define XPAR_PSU_SD_0_SDIO_CLK_FREQ_HZ 187498123 995 #define XPAR_PSU_SD_0_HAS_CD 0 996 #define XPAR_PSU_SD_0_HAS_WP 0 997 #define XPAR_PSU_SD_0_BUS_WIDTH 8 998 #define XPAR_PSU_SD_0_MIO_BANK 0 999 #define XPAR_PSU_SD_0_HAS_EMIO 0 1000 1001 1002 /* Definitions for peripheral PSU_SD_1 */ 1003 #define XPAR_PSU_SD_1_DEVICE_ID 1 1004 #define XPAR_PSU_SD_1_BASEADDR 0xFF170000 1005 #define XPAR_PSU_SD_1_HIGHADDR 0xFF17FFFF 1006 #define XPAR_PSU_SD_1_SDIO_CLK_FREQ_HZ 187498123 1007 #define XPAR_PSU_SD_1_HAS_CD 1 1008 #define XPAR_PSU_SD_1_HAS_WP 0 1009 #define XPAR_PSU_SD_1_BUS_WIDTH 4 1010 #define XPAR_PSU_SD_1_MIO_BANK 1 1011 #define XPAR_PSU_SD_1_HAS_EMIO 0 1012 1013 1014 /******************************************************************/ 1015 1016 #define XPAR_PSU_SD_0_IS_CACHE_COHERENT 0 1017 #define XPAR_PSU_SD_0_REF_CLK 0xff 1018 #define XPAR_PSU_SD_1_IS_CACHE_COHERENT 0 1019 #define XPAR_PSU_SD_1_REF_CLK 0xff 1020 /* Canonical definitions for peripheral PSU_SD_0 */ 1021 #define XPAR_XSDPS_0_DEVICE_ID XPAR_PSU_SD_0_DEVICE_ID 1022 #define XPAR_XSDPS_0_BASEADDR 0xFF160000 1023 #define XPAR_XSDPS_0_HIGHADDR 0xFF16FFFF 1024 #define XPAR_XSDPS_0_SDIO_CLK_FREQ_HZ 187498123 1025 #define XPAR_XSDPS_0_HAS_CD 0 1026 #define XPAR_XSDPS_0_HAS_WP 0 1027 #define XPAR_XSDPS_0_BUS_WIDTH 8 1028 #define XPAR_XSDPS_0_MIO_BANK 0 1029 #define XPAR_XSDPS_0_HAS_EMIO 0 1030 #define XPAR_XSDPS_0_IS_CACHE_COHERENT 0 1031 1032 /* Canonical definitions for peripheral PSU_SD_1 */ 1033 #define XPAR_XSDPS_1_DEVICE_ID XPAR_PSU_SD_1_DEVICE_ID 1034 #define XPAR_XSDPS_1_BASEADDR 0xFF170000 1035 #define XPAR_XSDPS_1_HIGHADDR 0xFF17FFFF 1036 #define XPAR_XSDPS_1_SDIO_CLK_FREQ_HZ 187498123 1037 #define XPAR_XSDPS_1_HAS_CD 1 1038 #define XPAR_XSDPS_1_HAS_WP 0 1039 #define XPAR_XSDPS_1_BUS_WIDTH 4 1040 #define XPAR_XSDPS_1_MIO_BANK 1 1041 #define XPAR_XSDPS_1_HAS_EMIO 0 1042 #define XPAR_XSDPS_1_IS_CACHE_COHERENT 0 1043 1044 1045 /******************************************************************/ 1046 1047 /* Definitions for driver SYSMONPSU */ 1048 #define XPAR_XSYSMONPSU_NUM_INSTANCES 1 1049 1050 /* Definitions for peripheral PSU_AMS */ 1051 #define XPAR_PSU_AMS_DEVICE_ID 0 1052 #define XPAR_PSU_AMS_BASEADDR 0xFFA50000 1053 #define XPAR_PSU_AMS_HIGHADDR 0xFFA5FFFF 1054 1055 1056 /******************************************************************/ 1057 1058 #define XPAR_PSU_AMS_REF_FREQMHZ 49.999500 1059 /* Canonical definitions for peripheral PSU_AMS */ 1060 #define XPAR_XSYSMONPSU_0_DEVICE_ID XPAR_PSU_AMS_DEVICE_ID 1061 #define XPAR_XSYSMONPSU_0_BASEADDR 0xFFA50000 1062 #define XPAR_XSYSMONPSU_0_HIGHADDR 0xFFA5FFFF 1063 1064 1065 /******************************************************************/ 1066 1067 #define XPAR_XSYSMONPSU_0_REF_FREQMHZ 49.999500 1068 /* Definitions for driver TTCPS */ 1069 #define XPAR_XTTCPS_NUM_INSTANCES 12U 1070 1071 /* Definitions for peripheral PSU_TTC_0 */ 1072 #define XPAR_PSU_TTC_0_DEVICE_ID 0U 1073 #define XPAR_PSU_TTC_0_BASEADDR 0XFF110000U 1074 #define XPAR_PSU_TTC_0_TTC_CLK_FREQ_HZ 100000000U 1075 #define XPAR_PSU_TTC_0_TTC_CLK_CLKSRC 0U 1076 #define XPAR_PSU_TTC_1_DEVICE_ID 1U 1077 #define XPAR_PSU_TTC_1_BASEADDR 0XFF110004U 1078 #define XPAR_PSU_TTC_1_TTC_CLK_FREQ_HZ 100000000U 1079 #define XPAR_PSU_TTC_1_TTC_CLK_CLKSRC 0U 1080 #define XPAR_PSU_TTC_2_DEVICE_ID 2U 1081 #define XPAR_PSU_TTC_2_BASEADDR 0XFF110008U 1082 #define XPAR_PSU_TTC_2_TTC_CLK_FREQ_HZ 100000000U 1083 #define XPAR_PSU_TTC_2_TTC_CLK_CLKSRC 0U 1084 1085 1086 /* Definitions for peripheral PSU_TTC_1 */ 1087 #define XPAR_PSU_TTC_3_DEVICE_ID 3U 1088 #define XPAR_PSU_TTC_3_BASEADDR 0XFF120000U 1089 #define XPAR_PSU_TTC_3_TTC_CLK_FREQ_HZ 100000000U 1090 #define XPAR_PSU_TTC_3_TTC_CLK_CLKSRC 0U 1091 #define XPAR_PSU_TTC_4_DEVICE_ID 4U 1092 #define XPAR_PSU_TTC_4_BASEADDR 0XFF120004U 1093 #define XPAR_PSU_TTC_4_TTC_CLK_FREQ_HZ 100000000U 1094 #define XPAR_PSU_TTC_4_TTC_CLK_CLKSRC 0U 1095 #define XPAR_PSU_TTC_5_DEVICE_ID 5U 1096 #define XPAR_PSU_TTC_5_BASEADDR 0XFF120008U 1097 #define XPAR_PSU_TTC_5_TTC_CLK_FREQ_HZ 100000000U 1098 #define XPAR_PSU_TTC_5_TTC_CLK_CLKSRC 0U 1099 1100 1101 /* Definitions for peripheral PSU_TTC_2 */ 1102 #define XPAR_PSU_TTC_6_DEVICE_ID 6U 1103 #define XPAR_PSU_TTC_6_BASEADDR 0XFF130000U 1104 #define XPAR_PSU_TTC_6_TTC_CLK_FREQ_HZ 100000000U 1105 #define XPAR_PSU_TTC_6_TTC_CLK_CLKSRC 0U 1106 #define XPAR_PSU_TTC_7_DEVICE_ID 7U 1107 #define XPAR_PSU_TTC_7_BASEADDR 0XFF130004U 1108 #define XPAR_PSU_TTC_7_TTC_CLK_FREQ_HZ 100000000U 1109 #define XPAR_PSU_TTC_7_TTC_CLK_CLKSRC 0U 1110 #define XPAR_PSU_TTC_8_DEVICE_ID 8U 1111 #define XPAR_PSU_TTC_8_BASEADDR 0XFF130008U 1112 #define XPAR_PSU_TTC_8_TTC_CLK_FREQ_HZ 100000000U 1113 #define XPAR_PSU_TTC_8_TTC_CLK_CLKSRC 0U 1114 1115 1116 /* Definitions for peripheral PSU_TTC_3 */ 1117 #define XPAR_PSU_TTC_9_DEVICE_ID 9U 1118 #define XPAR_PSU_TTC_9_BASEADDR 0XFF140000U 1119 #define XPAR_PSU_TTC_9_TTC_CLK_FREQ_HZ 100000000U 1120 #define XPAR_PSU_TTC_9_TTC_CLK_CLKSRC 0U 1121 #define XPAR_PSU_TTC_10_DEVICE_ID 10U 1122 #define XPAR_PSU_TTC_10_BASEADDR 0XFF140004U 1123 #define XPAR_PSU_TTC_10_TTC_CLK_FREQ_HZ 100000000U 1124 #define XPAR_PSU_TTC_10_TTC_CLK_CLKSRC 0U 1125 #define XPAR_PSU_TTC_11_DEVICE_ID 11U 1126 #define XPAR_PSU_TTC_11_BASEADDR 0XFF140008U 1127 #define XPAR_PSU_TTC_11_TTC_CLK_FREQ_HZ 100000000U 1128 #define XPAR_PSU_TTC_11_TTC_CLK_CLKSRC 0U 1129 1130 1131 /******************************************************************/ 1132 1133 /* Canonical definitions for peripheral PSU_TTC_0 */ 1134 #define XPAR_XTTCPS_0_DEVICE_ID XPAR_PSU_TTC_0_DEVICE_ID 1135 #define XPAR_XTTCPS_0_BASEADDR 0xFF110000U 1136 #define XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ 100000000U 1137 #define XPAR_XTTCPS_0_TTC_CLK_CLKSRC 0U 1138 1139 #define XPAR_XTTCPS_1_DEVICE_ID XPAR_PSU_TTC_1_DEVICE_ID 1140 #define XPAR_XTTCPS_1_BASEADDR 0xFF110004U 1141 #define XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ 100000000U 1142 #define XPAR_XTTCPS_1_TTC_CLK_CLKSRC 0U 1143 1144 #define XPAR_XTTCPS_2_DEVICE_ID XPAR_PSU_TTC_2_DEVICE_ID 1145 #define XPAR_XTTCPS_2_BASEADDR 0xFF110008U 1146 #define XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ 100000000U 1147 #define XPAR_XTTCPS_2_TTC_CLK_CLKSRC 0U 1148 1149 /* Canonical definitions for peripheral PSU_TTC_1 */ 1150 #define XPAR_XTTCPS_3_DEVICE_ID XPAR_PSU_TTC_3_DEVICE_ID 1151 #define XPAR_XTTCPS_3_BASEADDR 0xFF120000U 1152 #define XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ 100000000U 1153 #define XPAR_XTTCPS_3_TTC_CLK_CLKSRC 0U 1154 1155 #define XPAR_XTTCPS_4_DEVICE_ID XPAR_PSU_TTC_4_DEVICE_ID 1156 #define XPAR_XTTCPS_4_BASEADDR 0xFF120004U 1157 #define XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ 100000000U 1158 #define XPAR_XTTCPS_4_TTC_CLK_CLKSRC 0U 1159 1160 #define XPAR_XTTCPS_5_DEVICE_ID XPAR_PSU_TTC_5_DEVICE_ID 1161 #define XPAR_XTTCPS_5_BASEADDR 0xFF120008U 1162 #define XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ 100000000U 1163 #define XPAR_XTTCPS_5_TTC_CLK_CLKSRC 0U 1164 1165 /* Canonical definitions for peripheral PSU_TTC_2 */ 1166 #define XPAR_XTTCPS_6_DEVICE_ID XPAR_PSU_TTC_6_DEVICE_ID 1167 #define XPAR_XTTCPS_6_BASEADDR 0xFF130000U 1168 #define XPAR_XTTCPS_6_TTC_CLK_FREQ_HZ 100000000U 1169 #define XPAR_XTTCPS_6_TTC_CLK_CLKSRC 0U 1170 1171 #define XPAR_XTTCPS_7_DEVICE_ID XPAR_PSU_TTC_7_DEVICE_ID 1172 #define XPAR_XTTCPS_7_BASEADDR 0xFF130004U 1173 #define XPAR_XTTCPS_7_TTC_CLK_FREQ_HZ 100000000U 1174 #define XPAR_XTTCPS_7_TTC_CLK_CLKSRC 0U 1175 1176 #define XPAR_XTTCPS_8_DEVICE_ID XPAR_PSU_TTC_8_DEVICE_ID 1177 #define XPAR_XTTCPS_8_BASEADDR 0xFF130008U 1178 #define XPAR_XTTCPS_8_TTC_CLK_FREQ_HZ 100000000U 1179 #define XPAR_XTTCPS_8_TTC_CLK_CLKSRC 0U 1180 1181 /* Canonical definitions for peripheral PSU_TTC_3 */ 1182 #define XPAR_XTTCPS_9_DEVICE_ID XPAR_PSU_TTC_9_DEVICE_ID 1183 #define XPAR_XTTCPS_9_BASEADDR 0xFF140000U 1184 #define XPAR_XTTCPS_9_TTC_CLK_FREQ_HZ 100000000U 1185 #define XPAR_XTTCPS_9_TTC_CLK_CLKSRC 0U 1186 1187 #define XPAR_XTTCPS_10_DEVICE_ID XPAR_PSU_TTC_10_DEVICE_ID 1188 #define XPAR_XTTCPS_10_BASEADDR 0xFF140004U 1189 #define XPAR_XTTCPS_10_TTC_CLK_FREQ_HZ 100000000U 1190 #define XPAR_XTTCPS_10_TTC_CLK_CLKSRC 0U 1191 1192 #define XPAR_XTTCPS_11_DEVICE_ID XPAR_PSU_TTC_11_DEVICE_ID 1193 #define XPAR_XTTCPS_11_BASEADDR 0xFF140008U 1194 #define XPAR_XTTCPS_11_TTC_CLK_FREQ_HZ 100000000U 1195 #define XPAR_XTTCPS_11_TTC_CLK_CLKSRC 0U 1196 1197 1198 /******************************************************************/ 1199 1200 /* Definitions for driver UARTPS */ 1201 #define XPAR_XUARTPS_NUM_INSTANCES 1 1202 1203 /* Definitions for peripheral PSU_UART_0 */ 1204 #define XPAR_PSU_UART_0_DEVICE_ID 0 1205 #define XPAR_PSU_UART_0_BASEADDR 0xFF000000 1206 #define XPAR_PSU_UART_0_HIGHADDR 0xFF00FFFF 1207 #define XPAR_PSU_UART_0_UART_CLK_FREQ_HZ 99999001 1208 #define XPAR_PSU_UART_0_HAS_MODEM 0 1209 1210 1211 /******************************************************************/ 1212 1213 /* Canonical definitions for peripheral PSU_UART_0 */ 1214 #define XPAR_XUARTPS_0_DEVICE_ID XPAR_PSU_UART_0_DEVICE_ID 1215 #define XPAR_XUARTPS_0_BASEADDR 0xFF000000 1216 #define XPAR_XUARTPS_0_HIGHADDR 0xFF00FFFF 1217 #define XPAR_XUARTPS_0_UART_CLK_FREQ_HZ 99999001 1218 #define XPAR_XUARTPS_0_HAS_MODEM 0 1219 1220 1221 /******************************************************************/ 1222 1223 /* Definition for input Clock */ 1224 #define XPAR_PSU_UART_0_REF_CLK UART0_REF 1225 /* Definitions for driver USBPSU */ 1226 #define XPAR_XUSBPSU_NUM_INSTANCES 1 1227 1228 /* Definitions for peripheral PSU_USB_XHCI_0 */ 1229 #define XPAR_PSU_USB_XHCI_0_DEVICE_ID 0 1230 #define XPAR_PSU_USB_XHCI_0_BASEADDR 0xFE200000 1231 #define XPAR_PSU_USB_XHCI_0_HIGHADDR 0xFE20FFFF 1232 1233 1234 /******************************************************************/ 1235 1236 #define XPAR_PSU_USB_XHCI_0_IS_CACHE_COHERENT 0 1237 #define XPAR_PSU_USB_XHCI_0_REF_CLK 0xff 1238 #define XPAR_PSU_USB_XHCI_0_SUPER_SPEED 1 1239 /* Canonical definitions for peripheral PSU_USB_XHCI_0 */ 1240 #define XPAR_XUSBPSU_0_DEVICE_ID XPAR_PSU_USB_XHCI_0_DEVICE_ID 1241 #define XPAR_XUSBPSU_0_BASEADDR 0xFE200000 1242 #define XPAR_XUSBPSU_0_HIGHADDR 0xFE20FFFF 1243 1244 1245 /******************************************************************/ 1246 1247 /* Definitions for driver ZDMA */ 1248 #define XPAR_XZDMA_NUM_INSTANCES 16 1249 1250 /* Definitions for peripheral PSU_ADMA_0 */ 1251 #define XPAR_PSU_ADMA_0_DEVICE_ID 0 1252 #define XPAR_PSU_ADMA_0_BASEADDR 0xFFA80000 1253 #define XPAR_PSU_ADMA_0_DMA_MODE 1 1254 #define XPAR_PSU_ADMA_0_HIGHADDR 0xFFA8FFFF 1255 #define XPAR_PSU_ADMA_0_ZDMA_CLK_FREQ_HZ 0 1256 1257 1258 /* Definitions for peripheral PSU_ADMA_1 */ 1259 #define XPAR_PSU_ADMA_1_DEVICE_ID 1 1260 #define XPAR_PSU_ADMA_1_BASEADDR 0xFFA90000 1261 #define XPAR_PSU_ADMA_1_DMA_MODE 1 1262 #define XPAR_PSU_ADMA_1_HIGHADDR 0xFFA9FFFF 1263 #define XPAR_PSU_ADMA_1_ZDMA_CLK_FREQ_HZ 0 1264 1265 1266 /* Definitions for peripheral PSU_ADMA_2 */ 1267 #define XPAR_PSU_ADMA_2_DEVICE_ID 2 1268 #define XPAR_PSU_ADMA_2_BASEADDR 0xFFAA0000 1269 #define XPAR_PSU_ADMA_2_DMA_MODE 1 1270 #define XPAR_PSU_ADMA_2_HIGHADDR 0xFFAAFFFF 1271 #define XPAR_PSU_ADMA_2_ZDMA_CLK_FREQ_HZ 0 1272 1273 1274 /* Definitions for peripheral PSU_ADMA_3 */ 1275 #define XPAR_PSU_ADMA_3_DEVICE_ID 3 1276 #define XPAR_PSU_ADMA_3_BASEADDR 0xFFAB0000 1277 #define XPAR_PSU_ADMA_3_DMA_MODE 1 1278 #define XPAR_PSU_ADMA_3_HIGHADDR 0xFFABFFFF 1279 #define XPAR_PSU_ADMA_3_ZDMA_CLK_FREQ_HZ 0 1280 1281 1282 /* Definitions for peripheral PSU_ADMA_4 */ 1283 #define XPAR_PSU_ADMA_4_DEVICE_ID 4 1284 #define XPAR_PSU_ADMA_4_BASEADDR 0xFFAC0000 1285 #define XPAR_PSU_ADMA_4_DMA_MODE 1 1286 #define XPAR_PSU_ADMA_4_HIGHADDR 0xFFACFFFF 1287 #define XPAR_PSU_ADMA_4_ZDMA_CLK_FREQ_HZ 0 1288 1289 1290 /* Definitions for peripheral PSU_ADMA_5 */ 1291 #define XPAR_PSU_ADMA_5_DEVICE_ID 5 1292 #define XPAR_PSU_ADMA_5_BASEADDR 0xFFAD0000 1293 #define XPAR_PSU_ADMA_5_DMA_MODE 1 1294 #define XPAR_PSU_ADMA_5_HIGHADDR 0xFFADFFFF 1295 #define XPAR_PSU_ADMA_5_ZDMA_CLK_FREQ_HZ 0 1296 1297 1298 /* Definitions for peripheral PSU_ADMA_6 */ 1299 #define XPAR_PSU_ADMA_6_DEVICE_ID 6 1300 #define XPAR_PSU_ADMA_6_BASEADDR 0xFFAE0000 1301 #define XPAR_PSU_ADMA_6_DMA_MODE 1 1302 #define XPAR_PSU_ADMA_6_HIGHADDR 0xFFAEFFFF 1303 #define XPAR_PSU_ADMA_6_ZDMA_CLK_FREQ_HZ 0 1304 1305 1306 /* Definitions for peripheral PSU_ADMA_7 */ 1307 #define XPAR_PSU_ADMA_7_DEVICE_ID 7 1308 #define XPAR_PSU_ADMA_7_BASEADDR 0xFFAF0000 1309 #define XPAR_PSU_ADMA_7_DMA_MODE 1 1310 #define XPAR_PSU_ADMA_7_HIGHADDR 0xFFAFFFFF 1311 #define XPAR_PSU_ADMA_7_ZDMA_CLK_FREQ_HZ 0 1312 1313 1314 /* Definitions for peripheral PSU_GDMA_0 */ 1315 #define XPAR_PSU_GDMA_0_DEVICE_ID 8 1316 #define XPAR_PSU_GDMA_0_BASEADDR 0xFD500000 1317 #define XPAR_PSU_GDMA_0_DMA_MODE 0 1318 #define XPAR_PSU_GDMA_0_HIGHADDR 0xFD50FFFF 1319 #define XPAR_PSU_GDMA_0_ZDMA_CLK_FREQ_HZ 0 1320 1321 1322 /* Definitions for peripheral PSU_GDMA_1 */ 1323 #define XPAR_PSU_GDMA_1_DEVICE_ID 9 1324 #define XPAR_PSU_GDMA_1_BASEADDR 0xFD510000 1325 #define XPAR_PSU_GDMA_1_DMA_MODE 0 1326 #define XPAR_PSU_GDMA_1_HIGHADDR 0xFD51FFFF 1327 #define XPAR_PSU_GDMA_1_ZDMA_CLK_FREQ_HZ 0 1328 1329 1330 /* Definitions for peripheral PSU_GDMA_2 */ 1331 #define XPAR_PSU_GDMA_2_DEVICE_ID 10 1332 #define XPAR_PSU_GDMA_2_BASEADDR 0xFD520000 1333 #define XPAR_PSU_GDMA_2_DMA_MODE 0 1334 #define XPAR_PSU_GDMA_2_HIGHADDR 0xFD52FFFF 1335 #define XPAR_PSU_GDMA_2_ZDMA_CLK_FREQ_HZ 0 1336 1337 1338 /* Definitions for peripheral PSU_GDMA_3 */ 1339 #define XPAR_PSU_GDMA_3_DEVICE_ID 11 1340 #define XPAR_PSU_GDMA_3_BASEADDR 0xFD530000 1341 #define XPAR_PSU_GDMA_3_DMA_MODE 0 1342 #define XPAR_PSU_GDMA_3_HIGHADDR 0xFD53FFFF 1343 #define XPAR_PSU_GDMA_3_ZDMA_CLK_FREQ_HZ 0 1344 1345 1346 /* Definitions for peripheral PSU_GDMA_4 */ 1347 #define XPAR_PSU_GDMA_4_DEVICE_ID 12 1348 #define XPAR_PSU_GDMA_4_BASEADDR 0xFD540000 1349 #define XPAR_PSU_GDMA_4_DMA_MODE 0 1350 #define XPAR_PSU_GDMA_4_HIGHADDR 0xFD54FFFF 1351 #define XPAR_PSU_GDMA_4_ZDMA_CLK_FREQ_HZ 0 1352 1353 1354 /* Definitions for peripheral PSU_GDMA_5 */ 1355 #define XPAR_PSU_GDMA_5_DEVICE_ID 13 1356 #define XPAR_PSU_GDMA_5_BASEADDR 0xFD550000 1357 #define XPAR_PSU_GDMA_5_DMA_MODE 0 1358 #define XPAR_PSU_GDMA_5_HIGHADDR 0xFD55FFFF 1359 #define XPAR_PSU_GDMA_5_ZDMA_CLK_FREQ_HZ 0 1360 1361 1362 /* Definitions for peripheral PSU_GDMA_6 */ 1363 #define XPAR_PSU_GDMA_6_DEVICE_ID 14 1364 #define XPAR_PSU_GDMA_6_BASEADDR 0xFD560000 1365 #define XPAR_PSU_GDMA_6_DMA_MODE 0 1366 #define XPAR_PSU_GDMA_6_HIGHADDR 0xFD56FFFF 1367 #define XPAR_PSU_GDMA_6_ZDMA_CLK_FREQ_HZ 0 1368 1369 1370 /* Definitions for peripheral PSU_GDMA_7 */ 1371 #define XPAR_PSU_GDMA_7_DEVICE_ID 15 1372 #define XPAR_PSU_GDMA_7_BASEADDR 0xFD570000 1373 #define XPAR_PSU_GDMA_7_DMA_MODE 0 1374 #define XPAR_PSU_GDMA_7_HIGHADDR 0xFD57FFFF 1375 #define XPAR_PSU_GDMA_7_ZDMA_CLK_FREQ_HZ 0 1376 1377 1378 /******************************************************************/ 1379 1380 #define XPAR_PSU_ADMA_0_IS_CACHE_COHERENT 0 1381 #define XPAR_PSU_ADMA_1_IS_CACHE_COHERENT 0 1382 #define XPAR_PSU_ADMA_2_IS_CACHE_COHERENT 0 1383 #define XPAR_PSU_ADMA_3_IS_CACHE_COHERENT 0 1384 #define XPAR_PSU_ADMA_4_IS_CACHE_COHERENT 0 1385 #define XPAR_PSU_ADMA_5_IS_CACHE_COHERENT 0 1386 #define XPAR_PSU_ADMA_6_IS_CACHE_COHERENT 0 1387 #define XPAR_PSU_ADMA_7_IS_CACHE_COHERENT 0 1388 #define XPAR_PSU_GDMA_0_IS_CACHE_COHERENT 0 1389 #define XPAR_PSU_GDMA_1_IS_CACHE_COHERENT 0 1390 #define XPAR_PSU_GDMA_2_IS_CACHE_COHERENT 0 1391 #define XPAR_PSU_GDMA_3_IS_CACHE_COHERENT 0 1392 #define XPAR_PSU_GDMA_4_IS_CACHE_COHERENT 0 1393 #define XPAR_PSU_GDMA_5_IS_CACHE_COHERENT 0 1394 #define XPAR_PSU_GDMA_6_IS_CACHE_COHERENT 0 1395 #define XPAR_PSU_GDMA_7_IS_CACHE_COHERENT 0 1396 /* Canonical definitions for peripheral PSU_ADMA_0 */ 1397 #define XPAR_XZDMA_0_DEVICE_ID XPAR_PSU_ADMA_0_DEVICE_ID 1398 #define XPAR_XZDMA_0_BASEADDR 0xFFA80000 1399 #define XPAR_XZDMA_0_DMA_MODE 1 1400 #define XPAR_XZDMA_0_HIGHADDR 0xFFA8FFFF 1401 #define XPAR_XZDMA_0_ZDMA_CLK_FREQ_HZ 0 1402 1403 /* Canonical definitions for peripheral PSU_ADMA_1 */ 1404 #define XPAR_XZDMA_1_DEVICE_ID XPAR_PSU_ADMA_1_DEVICE_ID 1405 #define XPAR_XZDMA_1_BASEADDR 0xFFA90000 1406 #define XPAR_XZDMA_1_DMA_MODE 1 1407 #define XPAR_XZDMA_1_HIGHADDR 0xFFA9FFFF 1408 #define XPAR_XZDMA_1_ZDMA_CLK_FREQ_HZ 0 1409 1410 /* Canonical definitions for peripheral PSU_ADMA_2 */ 1411 #define XPAR_XZDMA_2_DEVICE_ID XPAR_PSU_ADMA_2_DEVICE_ID 1412 #define XPAR_XZDMA_2_BASEADDR 0xFFAA0000 1413 #define XPAR_XZDMA_2_DMA_MODE 1 1414 #define XPAR_XZDMA_2_HIGHADDR 0xFFAAFFFF 1415 #define XPAR_XZDMA_2_ZDMA_CLK_FREQ_HZ 0 1416 1417 /* Canonical definitions for peripheral PSU_ADMA_3 */ 1418 #define XPAR_XZDMA_3_DEVICE_ID XPAR_PSU_ADMA_3_DEVICE_ID 1419 #define XPAR_XZDMA_3_BASEADDR 0xFFAB0000 1420 #define XPAR_XZDMA_3_DMA_MODE 1 1421 #define XPAR_XZDMA_3_HIGHADDR 0xFFABFFFF 1422 #define XPAR_XZDMA_3_ZDMA_CLK_FREQ_HZ 0 1423 1424 /* Canonical definitions for peripheral PSU_ADMA_4 */ 1425 #define XPAR_XZDMA_4_DEVICE_ID XPAR_PSU_ADMA_4_DEVICE_ID 1426 #define XPAR_XZDMA_4_BASEADDR 0xFFAC0000 1427 #define XPAR_XZDMA_4_DMA_MODE 1 1428 #define XPAR_XZDMA_4_HIGHADDR 0xFFACFFFF 1429 #define XPAR_XZDMA_4_ZDMA_CLK_FREQ_HZ 0 1430 1431 /* Canonical definitions for peripheral PSU_ADMA_5 */ 1432 #define XPAR_XZDMA_5_DEVICE_ID XPAR_PSU_ADMA_5_DEVICE_ID 1433 #define XPAR_XZDMA_5_BASEADDR 0xFFAD0000 1434 #define XPAR_XZDMA_5_DMA_MODE 1 1435 #define XPAR_XZDMA_5_HIGHADDR 0xFFADFFFF 1436 #define XPAR_XZDMA_5_ZDMA_CLK_FREQ_HZ 0 1437 1438 /* Canonical definitions for peripheral PSU_ADMA_6 */ 1439 #define XPAR_XZDMA_6_DEVICE_ID XPAR_PSU_ADMA_6_DEVICE_ID 1440 #define XPAR_XZDMA_6_BASEADDR 0xFFAE0000 1441 #define XPAR_XZDMA_6_DMA_MODE 1 1442 #define XPAR_XZDMA_6_HIGHADDR 0xFFAEFFFF 1443 #define XPAR_XZDMA_6_ZDMA_CLK_FREQ_HZ 0 1444 1445 /* Canonical definitions for peripheral PSU_ADMA_7 */ 1446 #define XPAR_XZDMA_7_DEVICE_ID XPAR_PSU_ADMA_7_DEVICE_ID 1447 #define XPAR_XZDMA_7_BASEADDR 0xFFAF0000 1448 #define XPAR_XZDMA_7_DMA_MODE 1 1449 #define XPAR_XZDMA_7_HIGHADDR 0xFFAFFFFF 1450 #define XPAR_XZDMA_7_ZDMA_CLK_FREQ_HZ 0 1451 1452 /* Canonical definitions for peripheral PSU_GDMA_0 */ 1453 #define XPAR_XZDMA_8_DEVICE_ID XPAR_PSU_GDMA_0_DEVICE_ID 1454 #define XPAR_XZDMA_8_BASEADDR 0xFD500000 1455 #define XPAR_XZDMA_8_DMA_MODE 0 1456 #define XPAR_XZDMA_8_HIGHADDR 0xFD50FFFF 1457 #define XPAR_XZDMA_8_ZDMA_CLK_FREQ_HZ 0 1458 1459 /* Canonical definitions for peripheral PSU_GDMA_1 */ 1460 #define XPAR_XZDMA_9_DEVICE_ID XPAR_PSU_GDMA_1_DEVICE_ID 1461 #define XPAR_XZDMA_9_BASEADDR 0xFD510000 1462 #define XPAR_XZDMA_9_DMA_MODE 0 1463 #define XPAR_XZDMA_9_HIGHADDR 0xFD51FFFF 1464 #define XPAR_XZDMA_9_ZDMA_CLK_FREQ_HZ 0 1465 1466 /* Canonical definitions for peripheral PSU_GDMA_2 */ 1467 #define XPAR_XZDMA_10_DEVICE_ID XPAR_PSU_GDMA_2_DEVICE_ID 1468 #define XPAR_XZDMA_10_BASEADDR 0xFD520000 1469 #define XPAR_XZDMA_10_DMA_MODE 0 1470 #define XPAR_XZDMA_10_HIGHADDR 0xFD52FFFF 1471 #define XPAR_XZDMA_10_ZDMA_CLK_FREQ_HZ 0 1472 1473 /* Canonical definitions for peripheral PSU_GDMA_3 */ 1474 #define XPAR_XZDMA_11_DEVICE_ID XPAR_PSU_GDMA_3_DEVICE_ID 1475 #define XPAR_XZDMA_11_BASEADDR 0xFD530000 1476 #define XPAR_XZDMA_11_DMA_MODE 0 1477 #define XPAR_XZDMA_11_HIGHADDR 0xFD53FFFF 1478 #define XPAR_XZDMA_11_ZDMA_CLK_FREQ_HZ 0 1479 1480 /* Canonical definitions for peripheral PSU_GDMA_4 */ 1481 #define XPAR_XZDMA_12_DEVICE_ID XPAR_PSU_GDMA_4_DEVICE_ID 1482 #define XPAR_XZDMA_12_BASEADDR 0xFD540000 1483 #define XPAR_XZDMA_12_DMA_MODE 0 1484 #define XPAR_XZDMA_12_HIGHADDR 0xFD54FFFF 1485 #define XPAR_XZDMA_12_ZDMA_CLK_FREQ_HZ 0 1486 1487 /* Canonical definitions for peripheral PSU_GDMA_5 */ 1488 #define XPAR_XZDMA_13_DEVICE_ID XPAR_PSU_GDMA_5_DEVICE_ID 1489 #define XPAR_XZDMA_13_BASEADDR 0xFD550000 1490 #define XPAR_XZDMA_13_DMA_MODE 0 1491 #define XPAR_XZDMA_13_HIGHADDR 0xFD55FFFF 1492 #define XPAR_XZDMA_13_ZDMA_CLK_FREQ_HZ 0 1493 1494 /* Canonical definitions for peripheral PSU_GDMA_6 */ 1495 #define XPAR_XZDMA_14_DEVICE_ID XPAR_PSU_GDMA_6_DEVICE_ID 1496 #define XPAR_XZDMA_14_BASEADDR 0xFD560000 1497 #define XPAR_XZDMA_14_DMA_MODE 0 1498 #define XPAR_XZDMA_14_HIGHADDR 0xFD56FFFF 1499 #define XPAR_XZDMA_14_ZDMA_CLK_FREQ_HZ 0 1500 1501 /* Canonical definitions for peripheral PSU_GDMA_7 */ 1502 #define XPAR_XZDMA_15_DEVICE_ID XPAR_PSU_GDMA_7_DEVICE_ID 1503 #define XPAR_XZDMA_15_BASEADDR 0xFD570000 1504 #define XPAR_XZDMA_15_DMA_MODE 0 1505 #define XPAR_XZDMA_15_HIGHADDR 0xFD57FFFF 1506 #define XPAR_XZDMA_15_ZDMA_CLK_FREQ_HZ 0 1507 1508 1509 /******************************************************************/ 1510 1511 #endif /* end of protection macro */ 1512