1 /****************************************************************************** 2 * Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 ******************************************************************************/ 5 6 /*****************************************************************************/ 7 /** 8 * 9 * @file xreg_cortexr5.h 10 * 11 * This header file contains definitions for using inline assembler code. It is 12 * written specifically for the GNU, IAR, ARMCC compiler. 13 * 14 * All of the ARM Cortex R5 GPRs, SPRs, and Debug Registers are defined along 15 * with the positions of the bits within the registers. 16 * 17 * <pre> 18 * MODIFICATION HISTORY: 19 * 20 * Ver Who Date Changes 21 * ----- -------- -------- ----------------------------------------------- 22 * 5.00 pkp 02/10/14 Initial version 23 * </pre> 24 * 25 ******************************************************************************/ 26 #ifndef XREG_CORTEXR5_H /* prevent circular inclusions */ 27 #define XREG_CORTEXR5_H /* by using protection macros */ 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif /* __cplusplus */ 32 33 /* GPRs */ 34 #define XREG_GPR0 r0 35 #define XREG_GPR1 r1 36 #define XREG_GPR2 r2 37 #define XREG_GPR3 r3 38 #define XREG_GPR4 r4 39 #define XREG_GPR5 r5 40 #define XREG_GPR6 r6 41 #define XREG_GPR7 r7 42 #define XREG_GPR8 r8 43 #define XREG_GPR9 r9 44 #define XREG_GPR10 r10 45 #define XREG_GPR11 r11 46 #define XREG_GPR12 r12 47 #define XREG_GPR13 r13 48 #define XREG_GPR14 r14 49 #define XREG_GPR15 r15 50 #define XREG_CPSR cpsr 51 52 /* Coprocessor number defines */ 53 #define XREG_CP0 0 54 #define XREG_CP1 1 55 #define XREG_CP2 2 56 #define XREG_CP3 3 57 #define XREG_CP4 4 58 #define XREG_CP5 5 59 #define XREG_CP6 6 60 #define XREG_CP7 7 61 #define XREG_CP8 8 62 #define XREG_CP9 9 63 #define XREG_CP10 10 64 #define XREG_CP11 11 65 #define XREG_CP12 12 66 #define XREG_CP13 13 67 #define XREG_CP14 14 68 #define XREG_CP15 15 69 70 /* Coprocessor control register defines */ 71 #define XREG_CR0 cr0 72 #define XREG_CR1 cr1 73 #define XREG_CR2 cr2 74 #define XREG_CR3 cr3 75 #define XREG_CR4 cr4 76 #define XREG_CR5 cr5 77 #define XREG_CR6 cr6 78 #define XREG_CR7 cr7 79 #define XREG_CR8 cr8 80 #define XREG_CR9 cr9 81 #define XREG_CR10 cr10 82 #define XREG_CR11 cr11 83 #define XREG_CR12 cr12 84 #define XREG_CR13 cr13 85 #define XREG_CR14 cr14 86 #define XREG_CR15 cr15 87 88 /* Current Processor Status Register (CPSR) Bits */ 89 #define XREG_CPSR_THUMB_MODE 0x20U 90 #define XREG_CPSR_MODE_BITS 0x1FU 91 #define XREG_CPSR_SYSTEM_MODE 0x1FU 92 #define XREG_CPSR_UNDEFINED_MODE 0x1BU 93 #define XREG_CPSR_DATA_ABORT_MODE 0x17U 94 #define XREG_CPSR_SVC_MODE 0x13U 95 #define XREG_CPSR_IRQ_MODE 0x12U 96 #define XREG_CPSR_FIQ_MODE 0x11U 97 #define XREG_CPSR_USER_MODE 0x10U 98 99 #define XREG_CPSR_IRQ_ENABLE 0x80U 100 #define XREG_CPSR_FIQ_ENABLE 0x40U 101 102 #define XREG_CPSR_N_BIT 0x80000000U 103 #define XREG_CPSR_Z_BIT 0x40000000U 104 #define XREG_CPSR_C_BIT 0x20000000U 105 #define XREG_CPSR_V_BIT 0x10000000U 106 107 /*MPU region definitions*/ 108 #define REGION_32B 0x00000004U 109 #define REGION_64B 0x00000005U 110 #define REGION_128B 0x00000006U 111 #define REGION_256B 0x00000007U 112 #define REGION_512B 0x00000008U 113 #define REGION_1K 0x00000009U 114 #define REGION_2K 0x0000000AU 115 #define REGION_4K 0x0000000BU 116 #define REGION_8K 0x0000000CU 117 #define REGION_16K 0x0000000DU 118 #define REGION_32K 0x0000000EU 119 #define REGION_64K 0x0000000FU 120 #define REGION_128K 0x00000010U 121 #define REGION_256K 0x00000011U 122 #define REGION_512K 0x00000012U 123 #define REGION_1M 0x00000013U 124 #define REGION_2M 0x00000014U 125 #define REGION_4M 0x00000015U 126 #define REGION_8M 0x00000016U 127 #define REGION_16M 0x00000017U 128 #define REGION_32M 0x00000018U 129 #define REGION_64M 0x00000019U 130 #define REGION_128M 0x0000001AU 131 #define REGION_256M 0x0000001BU 132 #define REGION_512M 0x0000001CU 133 #define REGION_1G 0x0000001DU 134 #define REGION_2G 0x0000001EU 135 #define REGION_4G 0x0000001FU 136 137 #define REGION_EN 0x00000001U 138 139 140 141 #define SHAREABLE 0x00000004U /*shareable */ 142 #define STRONG_ORDERD_SHARED 0x00000000U /*strongly ordered, always shareable*/ 143 144 #define DEVICE_SHARED 0x00000001U /*device, shareable*/ 145 #define DEVICE_NONSHARED 0x00000010U /*device, non shareable*/ 146 147 #define NORM_NSHARED_WT_NWA 0x00000002U /*Outer and Inner write-through, no write-allocate non-shareable*/ 148 #define NORM_SHARED_WT_NWA 0x00000006U /*Outer and Inner write-through, no write-allocate shareable*/ 149 150 #define NORM_NSHARED_WB_NWA 0x00000003U /*Outer and Inner write-back, no write-allocate non shareable*/ 151 #define NORM_SHARED_WB_NWA 0x00000007U /*Outer and Inner write-back, no write-allocate shareable*/ 152 153 #define NORM_NSHARED_NCACHE 0x00000008U /*Outer and Inner Non cacheable non shareable*/ 154 #define NORM_SHARED_NCACHE 0x0000000CU /*Outer and Inner Non cacheable shareable*/ 155 156 #define NORM_NSHARED_WB_WA 0x0000000BU /*Outer and Inner write-back non shared*/ 157 #define NORM_SHARED_WB_WA 0x0000000FU /*Outer and Inner write-back shared*/ 158 159 /* inner and outer cache policies can be combined for different combinations */ 160 161 #define NORM_IN_POLICY_NCACHE 0x00000020U /*inner non cacheable*/ 162 #define NORM_IN_POLICY_WB_WA 0x00000021U /*inner write back write allocate*/ 163 #define NORM_IN_POLICY_WT_NWA 0x00000022U /*inner write through no write allocate*/ 164 #define NORM_IN_POLICY_WB_NWA 0x00000023U /*inner write back no write allocate*/ 165 166 #define NORM_OUT_POLICY_NCACHE 0x00000020U /*outer non cacheable*/ 167 #define NORM_OUT_POLICY_WB_WA 0x00000028U /*outer write back write allocate*/ 168 #define NORM_OUT_POLICY_WT_NWA 0x00000030U /*outer write through no write allocate*/ 169 #define NORM_OUT_POLICY_WB_NWA 0x00000038U /*outer write back no write allocate*/ 170 171 #define NO_ACCESS (0x00000000U<<8U) /*No access*/ 172 #define PRIV_RW_USER_NA (0x00000001U<<8U) /*Privileged access only*/ 173 #define PRIV_RW_USER_RO (0x00000002U<<8U) /*Writes in User mode generate permission faults*/ 174 #define PRIV_RW_USER_RW (0x00000003U<<8U) /*Full Access*/ 175 #define PRIV_RO_USER_NA (0x00000005U<<8U) /*Privileged eead only*/ 176 #define PRIV_RO_USER_RO (0x00000006U<<8U) /*Privileged/User read-only*/ 177 178 #define EXECUTE_NEVER (0x00000001U<<12U) /* Bit 12*/ 179 180 181 /* CP15 defines */ 182 183 /* C0 Register defines */ 184 #define XREG_CP15_MAIN_ID "p15, 0, %0, c0, c0, 0" 185 #define XREG_CP15_CACHE_TYPE "p15, 0, %0, c0, c0, 1" 186 #define XREG_CP15_TCM_TYPE "p15, 0, %0, c0, c0, 2" 187 #define XREG_CP15_TLB_TYPE "p15, 0, %0, c0, c0, 3" 188 #define XREG_CP15_MPU_TYPE "p15, 0, %0, c0, c0, 4" 189 #define XREG_CP15_MULTI_PROC_AFFINITY "p15, 0, %0, c0, c0, 5" 190 191 #define XREG_CP15_PROC_FEATURE_0 "p15, 0, %0, c0, c1, 0" 192 #define XREG_CP15_PROC_FEATURE_1 "p15, 0, %0, c0, c1, 1" 193 #define XREG_CP15_DEBUG_FEATURE_0 "p15, 0, %0, c0, c1, 2" 194 #define XREG_CP15_MEMORY_FEATURE_0 "p15, 0, %0, c0, c1, 4" 195 #define XREG_CP15_MEMORY_FEATURE_1 "p15, 0, %0, c0, c1, 5" 196 #define XREG_CP15_MEMORY_FEATURE_2 "p15, 0, %0, c0, c1, 6" 197 #define XREG_CP15_MEMORY_FEATURE_3 "p15, 0, %0, c0, c1, 7" 198 199 #define XREG_CP15_INST_FEATURE_0 "p15, 0, %0, c0, c2, 0" 200 #define XREG_CP15_INST_FEATURE_1 "p15, 0, %0, c0, c2, 1" 201 #define XREG_CP15_INST_FEATURE_2 "p15, 0, %0, c0, c2, 2" 202 #define XREG_CP15_INST_FEATURE_3 "p15, 0, %0, c0, c2, 3" 203 #define XREG_CP15_INST_FEATURE_4 "p15, 0, %0, c0, c2, 4" 204 #define XREG_CP15_INST_FEATURE_5 "p15, 0, %0, c0, c2, 5" 205 206 #define XREG_CP15_CACHE_SIZE_ID "p15, 1, %0, c0, c0, 0" 207 #define XREG_CP15_CACHE_LEVEL_ID "p15, 1, %0, c0, c0, 1" 208 #define XREG_CP15_AUXILARY_ID "p15, 1, %0, c0, c0, 7" 209 210 #define XREG_CP15_CACHE_SIZE_SEL "p15, 2, %0, c0, c0, 0" 211 212 /* C1 Register Defines */ 213 #define XREG_CP15_SYS_CONTROL "p15, 0, %0, c1, c0, 0" 214 #define XREG_CP15_AUX_CONTROL "p15, 0, %0, c1, c0, 1" 215 #define XREG_CP15_CP_ACCESS_CONTROL "p15, 0, %0, c1, c0, 2" 216 217 218 /* XREG_CP15_CONTROL bit defines */ 219 #define XREG_CP15_CONTROL_TE_BIT 0x40000000U 220 #define XREG_CP15_CONTROL_AFE_BIT 0x20000000U 221 #define XREG_CP15_CONTROL_TRE_BIT 0x10000000U 222 #define XREG_CP15_CONTROL_NMFI_BIT 0x08000000U 223 #define XREG_CP15_CONTROL_EE_BIT 0x02000000U 224 #define XREG_CP15_CONTROL_HA_BIT 0x00020000U 225 #define XREG_CP15_CONTROL_RR_BIT 0x00004000U 226 #define XREG_CP15_CONTROL_V_BIT 0x00002000U 227 #define XREG_CP15_CONTROL_I_BIT 0x00001000U 228 #define XREG_CP15_CONTROL_Z_BIT 0x00000800U 229 #define XREG_CP15_CONTROL_SW_BIT 0x00000400U 230 #define XREG_CP15_CONTROL_B_BIT 0x00000080U 231 #define XREG_CP15_CONTROL_C_BIT 0x00000004U 232 #define XREG_CP15_CONTROL_A_BIT 0x00000002U 233 #define XREG_CP15_CONTROL_M_BIT 0x00000001U 234 /* C2 Register Defines */ 235 /* Not Used */ 236 237 /* C3 Register Defines */ 238 /* Not Used */ 239 240 /* C4 Register Defines */ 241 /* Not Used */ 242 243 /* C5 Register Defines */ 244 #define XREG_CP15_DATA_FAULT_STATUS "p15, 0, %0, c5, c0, 0" 245 #define XREG_CP15_INST_FAULT_STATUS "p15, 0, %0, c5, c0, 1" 246 247 #define XREG_CP15_AUX_DATA_FAULT_STATUS "p15, 0, %0, c5, c1, 0" 248 #define XREG_CP15_AUX_INST_FAULT_STATUS "p15, 0, %0, c5, c1, 1" 249 250 /* C6 Register Defines */ 251 #define XREG_CP15_DATA_FAULT_ADDRESS "p15, 0, %0, c6, c0, 0" 252 #define XREG_CP15_INST_FAULT_ADDRESS "p15, 0, %0, c6, c0, 2" 253 254 #define XREG_CP15_MPU_REG_BASEADDR "p15, 0, %0, c6, c1, 0" 255 #define XREG_CP15_MPU_REG_SIZE_EN "p15, 0, %0, c6, c1, 2" 256 #define XREG_CP15_MPU_REG_ACCESS_CTRL "p15, 0, %0, c6, c1, 4" 257 258 #define XREG_CP15_MPU_MEMORY_REG_NUMBER "p15, 0, %0, c6, c2, 0" 259 260 /* C7 Register Defines */ 261 #define XREG_CP15_NOP "p15, 0, %0, c7, c0, 4" 262 263 #define XREG_CP15_INVAL_IC_POU "p15, 0, %0, c7, c5, 0" 264 #define XREG_CP15_INVAL_IC_LINE_MVA_POU "p15, 0, %0, c7, c5, 1" 265 266 /* The CP15 register access below has been deprecated in favor of the new 267 * isb instruction in Cortex R5. 268 */ 269 #define XREG_CP15_INST_SYNC_BARRIER "p15, 0, %0, c7, c5, 4" 270 #define XREG_CP15_INVAL_BRANCH_ARRAY "p15, 0, %0, c7, c5, 6" 271 #define XREG_CP15_INVAL_BRANCH_ARRAY_LINE "p15, 0, %0, c7, c5, 7" 272 273 #define XREG_CP15_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c6, 1" 274 #define XREG_CP15_INVAL_DC_LINE_SW "p15, 0, %0, c7, c6, 2" 275 276 277 #define XREG_CP15_CLEAN_DC_LINE_MVA_POC "p15, 0, %0, c7, c10, 1" 278 #define XREG_CP15_CLEAN_DC_LINE_SW "p15, 0, %0, c7, c10, 2" 279 280 #define XREG_CP15_INVAL_DC_ALL "p15, 0, %0, c15, c5, 0" 281 /* The next two CP15 register accesses below have been deprecated in favor 282 * of the new dsb and dmb instructions in Cortex R5. 283 */ 284 #define XREG_CP15_DATA_SYNC_BARRIER "p15, 0, %0, c7, c10, 4" 285 #define XREG_CP15_DATA_MEMORY_BARRIER "p15, 0, %0, c7, c10, 5" 286 287 #define XREG_CP15_CLEAN_DC_LINE_MVA_POU "p15, 0, %0, c7, c11, 1" 288 289 #define XREG_CP15_NOP2 "p15, 0, %0, c7, c13, 1" 290 291 #define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c14, 1" 292 #define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "p15, 0, %0, c7, c14, 2" 293 294 /* C8 Register Defines */ 295 /* Not Used */ 296 297 298 /* C9 Register Defines */ 299 300 #define XREG_CP15_ATCM_REG_SIZE_ADDR "p15, 0, %0, c9, c1, 1" 301 #define XREG_CP15_BTCM_REG_SIZE_ADDR "p15, 0, %0, c9, c1, 0" 302 #define XREG_CP15_TCM_SELECTION "p15, 0, %0, c9, c2, 0" 303 304 #define XREG_CP15_PERF_MONITOR_CTRL "p15, 0, %0, c9, c12, 0" 305 #define XREG_CP15_COUNT_ENABLE_SET "p15, 0, %0, c9, c12, 1" 306 #define XREG_CP15_COUNT_ENABLE_CLR "p15, 0, %0, c9, c12, 2" 307 #define XREG_CP15_V_FLAG_STATUS "p15, 0, %0, c9, c12, 3" 308 #define XREG_CP15_SW_INC "p15, 0, %0, c9, c12, 4" 309 #define XREG_CP15_EVENT_CNTR_SEL "p15, 0, %0, c9, c12, 5" 310 311 #define XREG_CP15_PERF_CYCLE_COUNTER "p15, 0, %0, c9, c13, 0" 312 #define XREG_CP15_EVENT_TYPE_SEL "p15, 0, %0, c9, c13, 1" 313 #define XREG_CP15_PERF_MONITOR_COUNT "p15, 0, %0, c9, c13, 2" 314 315 #define XREG_CP15_USER_ENABLE "p15, 0, %0, c9, c14, 0" 316 #define XREG_CP15_INTR_ENABLE_SET "p15, 0, %0, c9, c14, 1" 317 #define XREG_CP15_INTR_ENABLE_CLR "p15, 0, %0, c9, c14, 2" 318 319 /* C10 Register Defines */ 320 /* Not used */ 321 322 /* C11 Register Defines */ 323 /* Not used */ 324 325 /* C12 Register Defines */ 326 /* Not used */ 327 328 /* C13 Register Defines */ 329 #define XREG_CP15_CONTEXT_ID "p15, 0, %0, c13, c0, 1" 330 #define USER_RW_THREAD_PID "p15, 0, %0, c13, c0, 2" 331 #define USER_RO_THREAD_PID "p15, 0, %0, c13, c0, 3" 332 #define USER_PRIV_THREAD_PID "p15, 0, %0, c13, c0, 4" 333 334 /* C14 Register Defines */ 335 /* not used */ 336 337 /* C15 Register Defines */ 338 #define XREG_CP15_SEC_AUX_CTRL "p15, 0, %0, c15, c0, 0" 339 340 341 342 343 /* MPE register definitions */ 344 #define XREG_FPSID c0 345 #define XREG_FPSCR c1 346 #define XREG_MVFR1 c6 347 #define XREG_MVFR0 c7 348 #define XREG_FPEXC c8 349 #define XREG_FPINST c9 350 #define XREG_FPINST2 c10 351 352 /* FPSID bits */ 353 #define XREG_FPSID_IMPLEMENTER_BIT (24U) 354 #define XREG_FPSID_IMPLEMENTER_MASK (0x000000FFU << FPSID_IMPLEMENTER_BIT) 355 #define XREG_FPSID_SOFTWARE (0X00000001U << 23U) 356 #define XREG_FPSID_ARCH_BIT (16U) 357 #define XREG_FPSID_ARCH_MASK (0x0000000FU << FPSID_ARCH_BIT) 358 #define XREG_FPSID_PART_BIT (8U) 359 #define XREG_FPSID_PART_MASK (0x000000FFU << FPSID_PART_BIT) 360 #define XREG_FPSID_VARIANT_BIT (4U) 361 #define XREG_FPSID_VARIANT_MASK (0x0000000FU << FPSID_VARIANT_BIT) 362 #define XREG_FPSID_REV_BIT (0U) 363 #define XREG_FPSID_REV_MASK (0x0000000FU << FPSID_REV_BIT) 364 365 /* FPSCR bits */ 366 #define XREG_FPSCR_N_BIT (0X00000001U << 31U) 367 #define XREG_FPSCR_Z_BIT (0X00000001U << 30U) 368 #define XREG_FPSCR_C_BIT (0X00000001U << 29U) 369 #define XREG_FPSCR_V_BIT (0X00000001U << 28U) 370 #define XREG_FPSCR_QC (0X00000001U << 27U) 371 #define XREG_FPSCR_AHP (0X00000001U << 26U) 372 #define XREG_FPSCR_DEFAULT_NAN (0X00000001U << 25U) 373 #define XREG_FPSCR_FLUSHTOZERO (0X00000001U << 24U) 374 #define XREG_FPSCR_ROUND_NEAREST (0X00000000U << 22U) 375 #define XREG_FPSCR_ROUND_PLUSINF (0X00000001U << 22U) 376 #define XREG_FPSCR_ROUND_MINUSINF (0X00000002U << 22U) 377 #define XREG_FPSCR_ROUND_TOZERO (0X00000003U << 22U) 378 #define XREG_FPSCR_RMODE_BIT (22U) 379 #define XREG_FPSCR_RMODE_MASK (0X00000003U << FPSCR_RMODE_BIT) 380 #define XREG_FPSCR_STRIDE_BIT (20U) 381 #define XREG_FPSCR_STRIDE_MASK (0X00000003U << FPSCR_STRIDE_BIT) 382 #define XREG_FPSCR_LENGTH_BIT (16U) 383 #define XREG_FPSCR_LENGTH_MASK (0X00000007U << FPSCR_LENGTH_BIT) 384 #define XREG_FPSCR_IDC (0X00000001U << 7U) 385 #define XREG_FPSCR_IXC (0X00000001U << 4U) 386 #define XREG_FPSCR_UFC (0X00000001U << 3U) 387 #define XREG_FPSCR_OFC (0X00000001U << 2U) 388 #define XREG_FPSCR_DZC (0X00000001U << 1U) 389 #define XREG_FPSCR_IOC (0X00000001U << 0U) 390 391 /* MVFR0 bits */ 392 #define XREG_MVFR0_RMODE_BIT (28U) 393 #define XREG_MVFR0_RMODE_MASK (0x0000000FU << XREG_MVFR0_RMODE_BIT) 394 #define XREG_MVFR0_SHORT_VEC_BIT (24U) 395 #define XREG_MVFR0_SHORT_VEC_MASK (0x0000000FU << XREG_MVFR0_SHORT_VEC_BIT) 396 #define XREG_MVFR0_SQRT_BIT (20U) 397 #define XREG_MVFR0_SQRT_MASK (0x0000000FU << XREG_MVFR0_SQRT_BIT) 398 #define XREG_MVFR0_DIVIDE_BIT (16U) 399 #define XREG_MVFR0_DIVIDE_MASK (0x0000000FU << XREG_MVFR0_DIVIDE_BIT) 400 #define XREG_MVFR0_EXEC_TRAP_BIT (12U) 401 #define XREG_MVFR0_EXEC_TRAP_MASK (0x0000000FU << XREG_MVFR0_EXEC_TRAP_BIT) 402 #define XREG_MVFR0_DP_BIT (8U) 403 #define XREG_MVFR0_DP_MASK (0x0000000FU << XREG_MVFR0_DP_BIT) 404 #define XREG_MVFR0_SP_BIT (4U) 405 #define XREG_MVFR0_SP_MASK (0x0000000FU << XREG_MVFR0_SP_BIT) 406 #define XREG_MVFR0_A_SIMD_BIT (0U) 407 #define XREG_MVFR0_A_SIMD_MASK (0x0000000FU << MVFR0_A_SIMD_BIT) 408 409 /* FPEXC bits */ 410 #define XREG_FPEXC_EX (0X00000001U << 31U) 411 #define XREG_FPEXC_EN (0X00000001U << 30U) 412 #define XREG_FPEXC_DEX (0X00000001U << 29U) 413 414 415 #ifdef __cplusplus 416 } 417 #endif /* __cplusplus */ 418 419 #endif /* XREG_CORTEXR5_H */ 420