1 /*
2  * Copyright (c) 2006-2024, RT-Thread Development Team
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  *
6  * Change Logs:
7  * Date           Author       Notes
8  * 2024-04-11     liYony       the first version
9  */
10 
11 #ifndef __ZYNQMP_H__
12 #define __ZYNQMP_H__
13 
14 #include <rtdef.h>
15 #include <ioremap.h>
16 
17 #ifdef RT_USING_SMART
18 #include <mmu.h>
19 #endif
20 
21 #define __REG32(x)          (*((volatile unsigned int *)(x)))
22 #define __REG16(x)          (*((volatile unsigned short *)(x)))
23 
24 /* UART */
25 #define ZYNQMP_UART0_BASE    0xFF000000
26 #define ZYNQMP_UART0_SIZE    0x00010000
27 #define ZYNQMP_UART0_IRQNUM  (32 + 21)
28 #define ZYNQMP_UART0_CLK_FREQ_HZ (99999001)
29 
30 /* GIC */
31 #define MAX_HANDLERS        195
32 #define GIC_IRQ_START       0
33 #define ARM_GIC_NR_IRQS     195
34 #define ARM_GIC_MAX_NR      1
35 
36 /* GICv2 */
37 #define GIC400_DISTRIBUTOR_PPTR      0xF9010000U
38 #define GIC400_CONTROLLER_PPTR       0xF9020000U
39 #define GIC400_SIZE                  0x00001000U
40 
41 /* the basic constants and interfaces needed by gic */
platform_get_gic_dist_base(void)42 rt_inline rt_ubase_t platform_get_gic_dist_base(void)
43 {
44     return GIC400_DISTRIBUTOR_PPTR;
45 }
46 
platform_get_gic_cpu_base(void)47 rt_inline rt_ubase_t platform_get_gic_cpu_base(void)
48 {
49     return GIC400_CONTROLLER_PPTR;
50 }
51 
52 #endif /* __ZYNQMP_H__ */
53