1 /* 2 ****************************************************************************** 3 * @file ACM32F4.h 4 * @brief CMSIS ACM32F4 Device Peripheral Access Layer Header File. 5 * 6 * This file contains: 7 * - Data structures and the address mapping for all peripherals 8 * - Peripheral's registers declarations and bits definition 9 * - Macros to access peripheral's registers hardware 10 * 11 ****************************************************************************** 12 */ 13 #ifndef __ACM32F4_H__ 14 #define __ACM32F4_H__ 15 16 #ifdef __cplusplus 17 extern "C" 18 { 19 #endif 20 21 ///*------------------- Interrupt Number Definition ----------------------*/ 22 typedef enum IRQn 23 { 24 /* ---------------------------------- Cortex-M33 Processor Exceptions Numbers ----------------------------------- */ 25 Reset_IRQn = -15, /* -15 Reset Vector, invoked on Power up and warm reset */ 26 NonMaskableInt_IRQn = -14, /* -14 Non maskable Interrupt, cannot be stopped or preempted */ 27 HardFault_IRQn = -13, /* -13 Hard Fault, all classes of Fault */ 28 MemoryManagement_IRQn = -12, /* -12 Memory Management, MPU mismatch, including Access Violation 29 and No Match */ 30 BusFault_IRQn = -11, /* -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory 31 related Fault */ 32 UsageFault_IRQn = -10, /* -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ 33 SVCall_IRQn = -5, /* -5 System Service Call via SVC instruction */ 34 DebugMonitor_IRQn = -4, /* -4 Debug Monitor */ 35 PendSV_IRQn = -2, /* -2 Pendable request for system service */ 36 SysTick_IRQn = -1, /* -1 System Tick Timer */ 37 38 /* ------------------------------------- ARMCM0 Specific Interrupt Numbers -------------------------------------- */ 39 WDT_IRQn = 0, /* 0: WDT_IRQHandler */ 40 RTC_IRQn = 1, /* 1: RTC_IRQHandler */ 41 EFC_IRQn = 2, /* 2: EFC_IRQHandler */ 42 GPIOAB_IRQn = 3, /* 3: GPIOAB_IRQHandler */ 43 GPIOCD_IRQn = 4, /* 4: GPIOCD_IRQHandler */ 44 EXTI_IRQn = 5, /* 5: EXTI_IRQHandler */ 45 SRAM_PARITY_IRQn = 6, /* 6: SRAM_PARITY_IRQHandler */ 46 CLKRDY_IRQn = 7, /* 7: CLKRDY_IRQHandler */ 47 UART4_IRQn = 8, /* 8: UART4_IRQHandler */ 48 DMA_IRQn = 9, /* 9: DMA_IRQHandler */ 49 UART3_IRQn = 10, /* 10: UART3_IRQHandler */ 50 ADC_IRQn = 12, /* 12: ADC_IRQHandler */ 51 TIM1_BRK_UP_TRG_COM_IRQn = 13, /* 13: TIM1_BRK_UP_TRG_COM_IRQHandler */ 52 TIM1_CC_IRQn = 14, /* 14: TIM1_CC_IRQHandler */ 53 TIM2_IRQn = 15, /* 15: TIM2_IRQHandler */ 54 TIM3_IRQn = 16, /* 16: TIM3_IRQHandler */ 55 TIM6_IRQn = 17, /* 17: TIM6_IRQHandler */ 56 TIM7_IRQn = 18, /* 18: TIM7_IRQHandler */ 57 TIM14_IRQn = 19, /* 19: TIM14_IRQHandler */ 58 TIM15_IRQn = 20, /* 20: TIM15_IRQHandler */ 59 TIM16_IRQn = 21, /* 21: TIM16_IRQHandler */ 60 TIM17_IRQn = 22, /* 22: TIM17_IRQHandler */ 61 I2C1_IRQn = 23, /* 23: I2C1_IRQHandler */ 62 I2C2_IRQn = 24, /* 24: I2C2_IRQHandler */ 63 SPI1_IRQn = 25, /* 25: SPI1_IRQHandler */ 64 SPI2_IRQn = 26, /* 26: SPI2_IRQHandler */ 65 UART1_IRQn = 27, /* 27: UART1_IRQHandler */ 66 UART2_IRQn = 28, /* 28: UART2_IRQHandler */ 67 LPUART_IRQn = 29, /* 29: LPUART_IRQHandler */ 68 SPI3_IRQn = 30, /* 30: SPI3_IRQHandler */ 69 AES_IRQn = 31, /* 31: AES_IRQHandler */ 70 USB_IRQn = 32, /* 32: USB_IRQHandler */ 71 DAC_IRQn = 33, /* 33: DAC_IRQHandler */ 72 I2S_IRQn = 34, /* 34: I2S_IRQHandler */ 73 GPIOEF_IRQ = 35, /* 35: GPIOEF_IRQHandler */ 74 CAN1_IRQn = 36, /* 36: CAN1_IRQHandler */ 75 CAN2_IRQn = 37, /* 37: CAN2_IRQHandler */ 76 FPU_IRQn = 38, /* 38: FPU_IRQHandler */ 77 TIM4_IRQn = 39, /* 39: TIM4_IRQHandler */ 78 SPI4_IRQn = 40, /* 40: SPI4_IRQHandler */ 79 } IRQn_Type; 80 81 /* ================================================================================ */ 82 /* ================ Processor and Core Peripheral Section ================ */ 83 /* ================================================================================ */ 84 85 /* Configuration of the Cortex-M33 Processor and Core Peripherals */ 86 #define __MPU_PRESENT 1 /*!< mcu does not provide a MPU present or not */ 87 #define __NVIC_PRIO_BITS 3 /*!< mcu Supports 3 Bits for the Priority Levels */ 88 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 89 90 #define ARM_MATH_CM4 1 91 #define __TARGET_FPU_VFP 1 92 #define __FPU_PRESENT 1 93 #define __DSP_PRESENT 1 94 #define __ARM_COMPAT_H 1 95 #define __ACCELERATE_PRESENT 1 96 #define __ACCELERATE_EH_PRESENT 0 97 98 #include "core_cm33.h" /* Processor and core peripherals */ 99 100 #include "stdio.h" 101 #include "stdint.h" 102 #include "stdbool.h" 103 #include "string.h" 104 105 ///*------------------- Bit Opertions ----------------------*/ 106 #define BIT0 (1U << 0) 107 #define BIT1 (1U << 1) 108 #define BIT2 (1U << 2) 109 #define BIT3 (1U << 3) 110 #define BIT4 (1U << 4) 111 #define BIT5 (1U << 5) 112 #define BIT6 (1U << 6) 113 #define BIT7 (1U << 7) 114 #define BIT8 (1U << 8) 115 #define BIT9 (1U << 9) 116 #define BIT10 (1U << 10) 117 #define BIT11 (1U << 11) 118 #define BIT12 (1U << 12) 119 #define BIT13 (1U << 13) 120 #define BIT14 (1U << 14) 121 #define BIT15 (1U << 15) 122 #define BIT16 (1U << 16) 123 #define BIT17 (1U << 17) 124 #define BIT18 (1U << 18) 125 #define BIT19 (1U << 19) 126 #define BIT20 (1U << 20) 127 #define BIT21 (1U << 21) 128 #define BIT22 (1U << 22) 129 #define BIT23 (1U << 23) 130 #define BIT24 (1U << 24) 131 #define BIT25 (1U << 25) 132 #define BIT26 (1U << 26) 133 #define BIT27 (1U << 27) 134 #define BIT28 (1U << 28) 135 #define BIT29 (1U << 29) 136 #define BIT30 (1U << 30) 137 #define BIT31 (1U << 31) 138 139 140 /** @Addtogroup Peripheral_Registers_Structures 141 * @{ 142 */ 143 144 ///*------------------- FLASH Registers ----------------------*/ 145 typedef struct 146 { 147 __IO uint32_t CTRL; 148 __IO uint32_t SEC; 149 __IO uint32_t ADCT; 150 __IO uint32_t TERASE; 151 __IO uint32_t TPROG; 152 __IO uint32_t STATUS; 153 __IO uint32_t INTSTATUS; 154 __IO uint32_t INTEN; 155 __IO uint32_t CONFIG; 156 __IO uint32_t EDCTRL; 157 __IO uint32_t RDN0; 158 __IO uint32_t RDN1; 159 __IO uint32_t RDN2; 160 __IO uint32_t RDN3; 161 __IO uint32_t TNVS; 162 __IO uint32_t TMODE_SEC; 163 __IO uint32_t TDOUT; 164 __IO uint32_t TDIN; 165 __IO uint32_t TCTRL; 166 }EFC_TypeDef; 167 168 169 ///*------------------- Timer Registers ----------------------*/ 170 typedef struct 171 { 172 __IO uint32_t CR1; 173 __IO uint32_t CR2; 174 __IO uint32_t SMCR; 175 __IO uint32_t DIER; 176 __IO uint32_t SR; 177 __IO uint32_t EGR; 178 __IO uint32_t CCMR1; 179 __IO uint32_t CCMR2; 180 __IO uint32_t CCER; 181 __IO uint32_t CNT; 182 __IO uint32_t PSC; 183 __IO uint32_t ARR; 184 __IO uint32_t RCR; 185 __IO uint32_t CCR1; 186 __IO uint32_t CCR2; 187 __IO uint32_t CCR3; 188 __IO uint32_t CCR4; 189 __IO uint32_t BDTR; 190 __IO uint32_t DCR; 191 __IO uint32_t DMAR; 192 __IO uint32_t RSV0[4]; 193 __IO uint32_t AF1; 194 __IO uint32_t RSV1; 195 __IO uint32_t TISEL; 196 __IO uint32_t DBER; 197 }TIM_TypeDef; 198 199 200 ///*------------------- RTC和PMU Registers ----------------------*/ 201 typedef struct 202 { 203 __IO uint32_t WP; 204 __IO uint32_t IE; 205 __IO uint32_t SR; 206 __IO uint32_t SEC; 207 __IO uint32_t MIN; 208 __IO uint32_t HOUR; 209 __IO uint32_t DATE; 210 __IO uint32_t WEEK; 211 __IO uint32_t MONTH; 212 __IO uint32_t YEAR; 213 __IO uint32_t ALM; 214 __IO uint32_t CR; 215 __IO uint32_t ADJUST; 216 __IO uint32_t RSV0[4]; 217 __IO uint32_t CLKSTAMP1_TIME; 218 __IO uint32_t CALSTAMP1_DATE; 219 __IO uint32_t CLKSTAMP2_TIME; 220 __IO uint32_t CALSTAMP2_DATE; 221 __IO uint32_t RSV2[7]; 222 __IO uint32_t BAKUP[5]; 223 }RTC_TypeDef; 224 225 typedef struct 226 { 227 __IO uint32_t CR1; 228 __IO uint32_t SR; 229 __IO uint32_t IOSEL; 230 __IO uint32_t IOCR; 231 __IO uint32_t ANACR; 232 __IO uint32_t CR2; 233 }PMU_TypeDef; 234 235 236 ///*------------------- WDT Registers ----------------------*/ 237 typedef struct 238 { 239 __IO uint32_t LOAD; 240 __IO uint32_t COUNT; 241 __IO uint32_t CTRL; 242 __IO uint32_t FEED; 243 __IO uint32_t INTCLRTIME; 244 __IO uint32_t RIS; 245 }WDT_TypeDef; 246 247 248 ///*------------------- IWDT Registers ----------------------*/ 249 typedef struct 250 { 251 __IO uint32_t CMDR; 252 __IO uint32_t PR; 253 __IO uint32_t RLR; 254 __IO uint32_t SR; 255 __IO uint32_t WINR; 256 __IO uint32_t WUTR; 257 }IWDT_TypeDef; 258 259 260 ///*------------------- UART Registers ----------------------*/ 261 typedef struct 262 { 263 __IO uint32_t DR; 264 __IO uint32_t RSR; 265 __IO uint32_t RSV0[4]; 266 __IO uint32_t FR; 267 __IO uint32_t RSV1; 268 __IO uint32_t ILPR; 269 __IO uint32_t IBRD; 270 __IO uint32_t FBRD; 271 __IO uint32_t LCRH; 272 __IO uint32_t CR; 273 __IO uint32_t IFLS; 274 __IO uint32_t IE; 275 __IO uint32_t RIS; 276 __IO uint32_t MIS; 277 __IO uint32_t ICR; 278 __IO uint32_t DMACR; 279 __IO uint32_t RSV2[2]; 280 __IO uint32_t CR2; 281 __IO uint32_t BCNT; 282 }UART_TypeDef; 283 284 285 ///*------------------- I2C Registers ----------------------*/ 286 typedef struct 287 { 288 __IO uint32_t SLAVE_ADDR1; 289 __IO uint32_t CLK_DIV; 290 __IO uint32_t CR; 291 __IO uint32_t SR; 292 __IO uint32_t DR; 293 __IO uint32_t SLAVE_ADDR2_3; 294 __IO uint32_t RSV[3]; 295 __IO uint32_t TIMEOUT; 296 }I2C_TypeDef; 297 298 299 ///*------------------- CAN Registers ----------------------*/ 300 typedef struct 301 { 302 __IO uint32_t ACR[4]; 303 __IO uint32_t AMR[4]; 304 __IO uint32_t RSV[5]; 305 }Filter_typedef; 306 307 typedef union 308 { 309 __IO uint32_t DATABUF[13]; 310 Filter_typedef FILTER; 311 }DF_typedef; 312 313 typedef struct 314 { 315 __IO uint32_t MOD; 316 __IO uint32_t CMR; 317 __IO uint32_t SR; 318 __IO uint32_t IR; 319 __IO uint32_t IER; 320 __IO uint32_t RSV0; 321 __IO uint32_t BTR0; 322 __IO uint32_t BTR1; 323 __IO uint32_t OCR; 324 __IO uint32_t RSV1; 325 __IO uint32_t RSV2; 326 __IO uint32_t ALC; 327 __IO uint32_t ECC; 328 __IO uint32_t EWLR; 329 __IO uint32_t RXERR; 330 __IO uint32_t TXERR; 331 __IO DF_typedef DF; 332 __IO uint32_t RMC; 333 __IO uint32_t RBSA; 334 __IO uint32_t CDR; 335 __IO uint32_t RXFIFO[64]; 336 __IO uint32_t TXFIFO[13]; 337 }CAN_TypeDef; 338 339 340 ///*------------------- DAC Registers ----------------------*/ 341 typedef struct 342 { 343 __IO uint32_t CR; 344 __IO uint32_t SWTRIGR; 345 __IO uint32_t DHR12R1; 346 __IO uint32_t DHR12L1; 347 __IO uint32_t DHR8R1; 348 __IO uint32_t DHR12R2; 349 __IO uint32_t DHR12L2; 350 __IO uint32_t DHR8R2; 351 __IO uint32_t DHR12RD; 352 __IO uint32_t DHR12LD; 353 __IO uint32_t DHR8RD; 354 __IO uint32_t DOR1; 355 __IO uint32_t DOR2; 356 __IO uint32_t SR; 357 __IO uint32_t CCR; 358 __IO uint32_t MCR; 359 __IO uint32_t SHSR1; 360 __IO uint32_t SHSR2; 361 __IO uint32_t SHHR; 362 __IO uint32_t SHRR; 363 }DAC_TypeDef; 364 365 366 ///*------------------- LPUART Registers ----------------------*/ 367 typedef struct 368 { 369 __IO uint32_t RXDR; 370 __IO uint32_t TXDR; 371 __IO uint32_t LCR; 372 __IO uint32_t CR; 373 __IO uint32_t IBAUD; 374 __IO uint32_t FBAUD; 375 __IO uint32_t IE; 376 __IO uint32_t SR; 377 __IO uint32_t ADDR; 378 }LPUART_TypeDef; 379 380 381 ///*------------------- COMP Registers ----------------------*/ 382 typedef struct 383 { 384 __IO uint32_t CR1; 385 __IO uint32_t CR2; 386 __IO uint32_t SR; 387 }COMP_TypeDef; 388 389 390 ///*------------------- OPA Registers ----------------------*/ 391 typedef struct 392 { 393 __IO uint32_t OPA1_CSR; 394 __IO uint32_t OPA2_CSR; 395 __IO uint32_t OPA3_CSR; 396 }OPA_TypeDef; 397 398 399 ///*------------------- EXTI Registers ----------------------*/ 400 typedef struct 401 { 402 __IO uint32_t IENR; 403 __IO uint32_t EENR; 404 __IO uint32_t RTENR; 405 __IO uint32_t FTENR; 406 __IO uint32_t SWIER; 407 __IO uint32_t PDR; 408 __IO uint32_t EXTICR1; 409 __IO uint32_t EXTICR2; 410 }EXTI_TypeDef; 411 412 413 ///*------------------- SCU Registers ----------------------*/ 414 typedef struct 415 { 416 __IO uint32_t RCR; 417 __IO uint32_t RSR; 418 __IO uint32_t IPRST2; 419 __IO uint32_t IPRST1; 420 __IO uint32_t CCR1; 421 __IO uint32_t CCR2; 422 __IO uint32_t CIR; 423 __IO uint32_t IPCKENR1; 424 __IO uint32_t IPCKENR2; 425 __IO uint32_t RCHCR; 426 __IO uint32_t XTHCR; 427 __IO uint32_t PLLCR; 428 __IO uint32_t LDOCR; 429 __IO uint32_t RSV0; 430 __IO uint32_t WMR; 431 __IO uint32_t CLKOCR; 432 __IO uint32_t VER; 433 __IO uint32_t SYSCFG1; 434 __IO uint32_t LVDCFG; 435 __IO uint32_t STOPCFG; 436 __IO uint32_t RSV1; 437 __IO uint32_t PHYCR; 438 __IO uint32_t MEMCFG; 439 __IO uint32_t DUMMY; 440 __IO uint32_t PASEL1; 441 __IO uint32_t PASEL2; 442 __IO uint32_t PBSEL1; 443 __IO uint32_t PBSEL2; 444 __IO uint32_t PABPUR; 445 __IO uint32_t PABPDR; 446 __IO uint32_t PASTR; 447 __IO uint32_t PBSTR; 448 __IO uint32_t PABSMTR; 449 __IO uint32_t PABODR; 450 __IO uint32_t PABADS; 451 __IO uint32_t RSV2; 452 __IO uint32_t PCSEL1; 453 __IO uint32_t PCSEL2; 454 __IO uint32_t PDSEL1; 455 __IO uint32_t PDSEL2; 456 __IO uint32_t PCDPUR; 457 __IO uint32_t PCDPDR; 458 __IO uint32_t PCSTR; 459 __IO uint32_t PDSTR; 460 __IO uint32_t PCDSMTR; 461 __IO uint32_t PCDODR; 462 __IO uint32_t PCDADS; 463 __IO uint32_t RSV3; 464 __IO uint32_t PESEL1; 465 __IO uint32_t PESEL2; 466 __IO uint32_t PFSEL1; 467 __IO uint32_t RSV4; 468 __IO uint32_t PEFPUR; 469 __IO uint32_t PEFPDR; 470 __IO uint32_t PESTR; 471 __IO uint32_t PFSTR; 472 __IO uint32_t PEFSMTR; 473 __IO uint32_t PEFODR; 474 __IO uint32_t PEFADS; 475 }SCU_TypeDef; 476 477 478 ///*------------------- CRC Registers ----------------------*/ 479 typedef struct 480 { 481 __IO uint32_t DATA; 482 __IO uint32_t CTRL; 483 __IO uint32_t INIT; 484 __IO uint32_t RSV0; 485 __IO uint32_t OUTXOR; 486 __IO uint32_t POLY; 487 __IO uint32_t FDATA; 488 }CRC_TypeDef; 489 490 491 ///*------------------- ADC Registers ----------------------*/ 492 typedef struct 493 { 494 __IO uint32_t SR; 495 __IO uint32_t IE; 496 __IO uint32_t CR1; 497 __IO uint32_t CR2; 498 __IO uint32_t SMPR1; 499 __IO uint32_t SMPR2; 500 __IO uint32_t HTR; 501 __IO uint32_t LTR; 502 __IO uint32_t SQR1; 503 __IO uint32_t SQR2; 504 __IO uint32_t SQR3; 505 __IO uint32_t JSQR; 506 __IO uint32_t JDR; 507 __IO uint32_t DR; 508 __IO uint32_t DIFF; 509 __IO uint32_t SIGN; 510 __IO uint32_t TSREF; 511 __IO uint32_t SMPR3; 512 }ADC_TypeDef; 513 514 515 ///*------------------- I2S Registers ----------------------*/ 516 typedef struct 517 { 518 __IO uint32_t DAT; 519 __IO uint32_t CTL; 520 __IO uint32_t PSC; 521 __IO uint32_t IE; 522 __IO uint32_t STATUS; 523 }I2S_TypeDef; 524 525 526 ///*------------------- GPIO Registers ----------------------*/ 527 typedef struct 528 { 529 __IO uint32_t DIR; 530 __IO uint32_t RSV0; 531 __IO uint32_t SET; 532 __IO uint32_t CLR; 533 __IO uint32_t ODATA; 534 __IO uint32_t IDATA; 535 __IO uint32_t IEN; 536 __IO uint32_t IS; 537 __IO uint32_t IBE; 538 __IO uint32_t IEV; 539 __IO uint32_t IC; 540 __IO uint32_t RIS; 541 __IO uint32_t MIS; 542 }GPIO_TypeDef; 543 544 545 ///*------------------- SPI Registers ----------------------*/ 546 typedef struct 547 { 548 __IO uint32_t DAT; 549 __IO uint32_t BAUD; 550 __IO uint32_t CTL; 551 __IO uint32_t TX_CTL; 552 __IO uint32_t RX_CTL; 553 __IO uint32_t IE; 554 __IO uint32_t STATUS; 555 __IO uint32_t TX_DELAY; 556 __IO uint32_t BATCH; 557 __IO uint32_t CS; 558 __IO uint32_t OUT_EN; 559 __IO uint32_t MEMO_ACC; 560 __IO uint32_t CMD; 561 __IO uint32_t PARA; 562 }SPI_TypeDef; 563 564 565 ///*------------------- DMA Registers ----------------------*/ 566 typedef struct 567 { 568 __IO uint32_t INT_STATUS; 569 __IO uint32_t INT_TC_STATUS; 570 __IO uint32_t INT_TC_CLR; 571 __IO uint32_t INT_ERR_STATUS; 572 __IO uint32_t INT_ERR_CLR; 573 __IO uint32_t RAW_INT_TC_STATUS; 574 __IO uint32_t RAW_INT_ERR_STATUS; 575 __IO uint32_t EN_CH_STATUS; 576 __IO uint32_t RSV0[4]; 577 __IO uint32_t CONFIG; 578 __IO uint32_t SYNCLO; 579 __IO uint32_t SYNCHI; 580 }DMA_TypeDef; 581 582 typedef struct 583 { 584 __IO uint32_t SRC_ADDR; 585 __IO uint32_t DEST_ADDR; 586 __IO uint32_t LLI; 587 __IO uint32_t CTRL; 588 __IO uint32_t CONFIG; 589 }DMA_Channel_TypeDef; 590 591 592 ///*------------------- AES Registers ----------------------*/ 593 typedef struct 594 { 595 __IO uint32_t DATAIN; 596 __IO uint32_t KEYIN; 597 __IO uint32_t RSV0; 598 __IO uint32_t CONTROL; 599 __IO uint32_t STATE; 600 __IO uint32_t DATAOUT; 601 }AES_TypeDef; 602 603 604 ///*------------------- FAU Registers ----------------------*/ 605 typedef struct 606 { 607 __IO uint32_t CTRL1; //0x00 608 __IO uint32_t STAUTS; //0x04 609 610 __IO uint32_t CORDIC_X_DATAIN; //0x08 611 __IO uint32_t CORDIC_Y_DATAIN; //0x0c 612 __IO uint32_t RESULT1; //0x10 613 __IO uint32_t RESULT2; //0x14 614 }FAU_TypeDef; 615 616 617 ///*------------------- HRNG Registers ----------------------*/ 618 typedef struct 619 { 620 __IO uint32_t CTRL; 621 __IO uint32_t LFSR; 622 }HRNG_TypeDef; 623 624 625 ///*------------------- HASH Registers ----------------------*/ 626 typedef struct 627 { 628 __IO uint32_t DATAIN; 629 __IO uint32_t MIDDATA; 630 __IO uint32_t CTRL; 631 __IO uint32_t DATAOUT; 632 }HASH_TypeDef; 633 634 635 ///*------------------- USB Registers ----------------------*/ 636 typedef struct 637 { 638 __IO uint32_t WORKING_MODE; 639 __IO uint32_t EPxCSR[5]; 640 __IO uint32_t USB_ADDR; 641 __IO uint32_t SETIP_0_3_DATA; 642 __IO uint32_t SETIP_4_7_DATA; 643 __IO uint32_t EPADDR_CFG; 644 __IO uint32_t CURRENT_PID; 645 __IO uint32_t CURRENT_FRAME_NUMBER; 646 __IO uint32_t CRC_ERROR_CNT; 647 __IO uint32_t USB_STATUS_DETECT_CNT; 648 __IO uint32_t RSV0; 649 __IO uint32_t RSV1; 650 __IO uint32_t EPxSENDBN[5]; 651 }USB_CTRLTypeDef; 652 653 ///*------------------- USB interrupt access Registers ----------------------*/ 654 typedef struct 655 { 656 __IO uint32_t INT_STAT_RAW; 657 __IO uint32_t INT_EN; 658 __IO uint32_t RSV; 659 __IO uint32_t INT_CLR; 660 }USB_INTTypeDef; 661 662 /** 663 * @} 664 */ 665 666 667 668 /** @addtogroup Peripheral_memory_map 669 * @{ 670 */ 671 672 ///*------------------- Peripheral memory map ----------------------*/ 673 #define EFLASH_BASE (0x00000000UL) 674 #define SRAM_BASE (0x20000000UL) 675 #define PERIPH_BASE (0x40000000UL) 676 #define QSPI_BASE (0x90000000UL) 677 678 #define APB1PERIPH_BASE (PERIPH_BASE) 679 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) 680 #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL) 681 682 ///*---------------------- EFC peripherals ------------------------*/ 683 #define EFLASH_REG_BASE (EFLASH_BASE + 0x00100000) 684 685 ///*---------------------- APB1 peripherals ------------------------*/ 686 #define TIM2_BASE (APB1PERIPH_BASE + 0x00000000UL) 687 #define TIM3_BASE (APB1PERIPH_BASE + 0x00000400UL) 688 #define TIM4_BASE (APB1PERIPH_BASE + 0x00000800UL) 689 #define TIM6_BASE (APB1PERIPH_BASE + 0x00001000UL) 690 #define TIM7_BASE (APB1PERIPH_BASE + 0x00001400UL) 691 #define TIM14_BASE (APB1PERIPH_BASE + 0x00002000UL) 692 #define PMU_BASE (APB1PERIPH_BASE + 0x00002400UL) 693 #define RTC_BASE (APB1PERIPH_BASE + 0x00002800UL) 694 #define WDT_BASE (APB1PERIPH_BASE + 0x00002C00UL) 695 #define IWDT_BASE (APB1PERIPH_BASE + 0x00003000UL) 696 #define UART2_BASE (APB1PERIPH_BASE + 0x00004400UL) 697 #define UART3_BASE (APB1PERIPH_BASE + 0x00004800UL) 698 #define UART4_BASE (APB1PERIPH_BASE + 0x00004C00UL) 699 #define I2C1_BASE (APB1PERIPH_BASE + 0x00005400UL) 700 #define I2C2_BASE (APB1PERIPH_BASE + 0x00005800UL) 701 #define CAN1_BASE (APB1PERIPH_BASE + 0x00006400UL) 702 #define CAN2_BASE (APB1PERIPH_BASE + 0x00006800UL) 703 #define DAC_BASE (APB1PERIPH_BASE + 0x00007400UL) 704 #define LPUART_BASE (APB1PERIPH_BASE + 0x00008000UL) 705 706 ///*---------------------- APB2 peripherals ------------------------*/ 707 #define COMP_BASE (APB2PERIPH_BASE + 0x00000200UL) 708 #define OPA_BASE (APB2PERIPH_BASE + 0x00000300UL) 709 #define EXTI_BASE (APB2PERIPH_BASE + 0x00000400UL) 710 #define SCU_BASE (APB2PERIPH_BASE + 0x00000800UL) 711 #define CRC_BASE (APB2PERIPH_BASE + 0x00000C00UL) 712 #define ADC_BASE (APB2PERIPH_BASE + 0x00002400UL) 713 #define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00UL) 714 #define I2S1_BASE (APB2PERIPH_BASE + 0x00003000UL) 715 #define UART1_BASE (APB2PERIPH_BASE + 0x00003800UL) 716 #define TIM15_BASE (APB2PERIPH_BASE + 0x00004000UL) 717 #define TIM16_BASE (APB2PERIPH_BASE + 0x00004400UL) 718 #define TIM17_BASE (APB2PERIPH_BASE + 0x00004800UL) 719 #define GPIOAB_BASE (APB2PERIPH_BASE + 0x0000F000UL) 720 #define GPIOCD_BASE (APB2PERIPH_BASE + 0x0000F400UL) 721 #define GPIOEF_BASE (APB2PERIPH_BASE + 0x0000F800UL) 722 723 ///*---------------------- AHB peripherals ------------------------*/ 724 #define SPI1_BASE (AHBPERIPH_BASE) 725 #define SPI2_BASE (AHBPERIPH_BASE + 0x00000400UL) 726 #define SPI3_BASE (AHBPERIPH_BASE + 0x00000800UL) 727 #define SPI4_BASE (AHBPERIPH_BASE + 0x00000C00UL) 728 #define DMA_BASE (AHBPERIPH_BASE + 0x00001000UL) 729 #define DMA_Channel0_BASE (AHBPERIPH_BASE + 0x00001100UL) 730 #define DMA_Channel1_BASE (AHBPERIPH_BASE + 0x00001120UL) 731 #define DMA_Channel2_BASE (AHBPERIPH_BASE + 0x00001140UL) 732 #define DMA_Channel3_BASE (AHBPERIPH_BASE + 0x00001160UL) 733 #define DMA_Channel4_BASE (AHBPERIPH_BASE + 0x00001180UL) 734 #define DMA_Channel5_BASE (AHBPERIPH_BASE + 0x000011A0UL) 735 #define DMA_Channel6_BASE (AHBPERIPH_BASE + 0x000011C0UL) 736 #define DMA_Channel7_BASE (AHBPERIPH_BASE + 0x000011E0UL) 737 #define AES_BASE (AHBPERIPH_BASE + 0x00010000UL) 738 #define FAU_BASE (AHBPERIPH_BASE + 0x00010400UL) 739 #define HRNG_BASE (AHBPERIPH_BASE + 0x00010800UL) 740 #define HASH_BASE (AHBPERIPH_BASE + 0x00010C00UL) 741 #define USB_BASE (AHBPERIPH_BASE + 0x00020000UL) 742 743 ///*---------------------- QSPI Memory ------------------------*/ 744 #define QSPI3_BASE (QSPI_BASE) 745 746 /** 747 * @} 748 */ 749 750 751 752 /** @addtogroup Peripheral_declaration 753 * @{ 754 */ 755 #define EFC ((EFC_TypeDef *)EFLASH_REG_BASE) 756 #define TIM2 ((TIM_TypeDef *)TIM2_BASE) 757 #define TIM3 ((TIM_TypeDef *)TIM3_BASE) 758 #define TIM4 ((TIM_TypeDef *)TIM4_BASE) 759 #define TIM6 ((TIM_TypeDef *)TIM6_BASE) 760 #define TIM7 ((TIM_TypeDef *)TIM7_BASE) 761 #define TIM14 ((TIM_TypeDef *)TIM14_BASE) 762 #define PMU ((PMU_TypeDef *)PMU_BASE) 763 #define RTC ((RTC_TypeDef *)RTC_BASE) 764 #define WDT ((WDT_TypeDef *)WDT_BASE) 765 #define IWDT ((IWDT_TypeDef *)IWDT_BASE) 766 #define UART2 ((UART_TypeDef *)UART2_BASE) 767 #define UART3 ((UART_TypeDef *)UART3_BASE) 768 #define UART4 ((UART_TypeDef *)UART4_BASE) 769 #define I2C1 ((I2C_TypeDef *)I2C1_BASE) 770 #define I2C2 ((I2C_TypeDef *)I2C2_BASE) 771 #define CAN1 ((CAN_TypeDef *)CAN1_BASE) 772 #define CAN2 ((CAN_TypeDef *)CAN2_BASE) 773 #define DAC ((DAC_TypeDef *)DAC_BASE) 774 #define LPUART ((LPUART_TypeDef *)LPUART_BASE) 775 #define COMP ((COMP_TypeDef *)COMP_BASE) 776 #define OPA ((OPA_TypeDef *)OPA_BASE) 777 #define EXTI ((EXTI_TypeDef *)EXTI_BASE) 778 #define SCU ((SCU_TypeDef *)SCU_BASE) 779 #define CRC ((CRC_TypeDef *)CRC_BASE) 780 #define ADC ((ADC_TypeDef *)ADC_BASE) 781 #define TIM1 ((TIM_TypeDef *)TIM1_BASE) 782 #define I2S1 ((I2S_TypeDef *)I2S1_BASE) 783 #define UART1 ((UART_TypeDef *)UART1_BASE) 784 #define TIM15 ((TIM_TypeDef *)TIM15_BASE) 785 #define TIM16 ((TIM_TypeDef *)TIM16_BASE) 786 #define TIM17 ((TIM_TypeDef *)TIM17_BASE) 787 #define GPIOAB ((GPIO_TypeDef *)GPIOAB_BASE) 788 #define GPIOCD ((GPIO_TypeDef *)GPIOCD_BASE) 789 #define GPIOEF ((GPIO_TypeDef *)GPIOEF_BASE) 790 #define SPI1 ((SPI_TypeDef *)SPI1_BASE) 791 #define SPI2 ((SPI_TypeDef *)SPI2_BASE) 792 #define SPI3 ((SPI_TypeDef *)SPI3_BASE) 793 #define SPI4 ((SPI_TypeDef *)SPI4_BASE) 794 #define DMA ((DMA_TypeDef *)DMA_BASE) 795 #define DMA_Channel0 ((DMA_Channel_TypeDef *)DMA_Channel0_BASE) 796 #define DMA_Channel1 ((DMA_Channel_TypeDef *)DMA_Channel1_BASE) 797 #define DMA_Channel2 ((DMA_Channel_TypeDef *)DMA_Channel2_BASE) 798 #define DMA_Channel3 ((DMA_Channel_TypeDef *)DMA_Channel3_BASE) 799 #define DMA_Channel4 ((DMA_Channel_TypeDef *)DMA_Channel4_BASE) 800 #define DMA_Channel5 ((DMA_Channel_TypeDef *)DMA_Channel5_BASE) 801 #define DMA_Channel6 ((DMA_Channel_TypeDef *)DMA_Channel6_BASE) 802 #define DMA_Channel7 ((DMA_Channel_TypeDef *)DMA_Channel7_BASE) 803 #define AES ((AES_TypeDef *)AES_BASE) 804 #define FAU ((FAU_TypeDef *)FAU_BASE) 805 #define HRNG ((HRNG_TypeDef *)HRNG_BASE) 806 #define HASH ((HASH_TypeDef *)HASH_BASE) 807 #define USBCTRL ((USB_CTRLTypeDef *)USB_BASE) 808 #define USBINT ((USB_INTTypeDef *)(USB_BASE+0xFFE4)) 809 /** 810 * @} 811 */ 812 813 814 /** @addtogroup Exported_macros 815 * @{ 816 */ 817 #define SET_BIT(REG, BIT) ((REG) |= (BIT)) 818 819 #define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) 820 821 #define READ_BIT(REG, BIT) ((REG) & (BIT)) 822 823 #define CLEAR_REG(REG) ((REG) = (0x0)) 824 825 #define WRITE_REG(REG, VAL) ((REG) = (VAL)) 826 827 #define READ_REG(REG) ((REG)) 828 829 #define MODIFY_REG(REG,MASK,BITS) ((REG) = (((REG)&(~(MASK)))|((BITS)&(MASK)))) 830 831 typedef signed char INT8; 832 typedef signed short int INT16; 833 typedef signed int INT32; 834 835 /* exact-width unsigned integer types */ 836 typedef unsigned char UINT8; 837 typedef unsigned short int UINT16; 838 typedef unsigned int UINT32; 839 840 /** 841 * @} 842 */ 843 844 #ifdef __cplusplus 845 } 846 #endif 847 848 #endif /* ACM32F4_H */ 849