1 /*
2 * Copyright (C) 2017 ALLWINNERTECH TECHNOLOGY CO., LTD. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the
12 * distribution.
13 * 3. Neither the name of ALLWINNERTECH TECHNOLOGY CO., LTD. nor the names of
14 * its contributors may be used to endorse or promote products derived
15 * from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30 #ifndef _ROM_DRIVER_CHIP_SDMMC__SDHOST_H_
31 #define _ROM_DRIVER_CHIP_SDMMC__SDHOST_H_
32
33 #include "platform_mmc.h"
34 #include "hal_sdhost.h"
35 #include <hal_gpio.h>
36 #include "_sdhost.h"
37
38 #define CONFIG_SDC_OS_USED
39 #define __CONFIG_ARCH_APP_CORE
40
41 #ifdef SD_SUPPORT_VERSION3
42 #define CONFIG_SDC_SUPPORT_1V8 /* board not support */
43 #endif
44
45 #ifdef SD_SUPPORT_WRITEPROTECT
46 #define CONFIG_SDC_READONLY_USED /* check readonly */
47 #endif
48
49 #ifdef CONFIG_SDC_OS_USED
50 #include "os_semaphore.h"
51 #include "os_mutex.h"
52 #ifdef __CONFIG_ARCH_APP_CORE
53 #include "os_timer.h"
54 #endif
55
56 #define SDC_Semaphore OS_Semaphore_t
57 #define SDC_Mutex OS_Mutex_t
58 #ifdef __CONFIG_ARCH_APP_CORE
59 #define SDC_Timer OS_Timer_t
60 #endif
61 #endif
62
63 #ifdef CONFIG_PM
64 #define CONFIG_SD_PM
65 #endif
66
67 #ifdef __cplusplus
68 extern "C" {
69 #endif
70
71 #define CONFIG_SDC_EXCLUSIVE_HOST
72
73 /*
74 * the max length of buffer which IDMA description supported is 8192,
75 * transport data by several IDMA descriptions if data lenght more than 8192,
76 * and the max number IDMA description support is 1024.
77 * which meas the mas length transport data is 1024 * 8192 = 8MB in a signal transfer.
78 */
79 #ifdef __CONFIG_ARCH_APP_CORE
80 #define SDXC_MAX_TRANS_LEN (1 << 18 << 4) /* max len is 4M */
81 #else
82 #define SDXC_MAX_TRANS_LEN (1 << 14 << 8) /* max len is 4M */
83 #endif
84 #define SDXC_DES_NUM_SHIFT (13)
85 #define SDXC_DES_BUFFER_MAX_LEN (1 << SDXC_DES_NUM_SHIFT) /* 8192 == 1<<13; */
86 #define SDXC_MAX_DES_NUM (SDXC_MAX_TRANS_LEN >> SDXC_DES_NUM_SHIFT) /* 2 is the least */
87 #define SDXC_DES_MODE (0) /* 0-chain mode, 1-fix length skip */
88
89 struct scatterlist {
90 void *buffer;
91 uint32_t len;
92 };
93
94 /* IDMC structure */
95 typedef struct {
96 uint32_t config;
97
98 #define SDXC_IDMAC_DES0_DIC BIT(1) /* disable interrupt on completion */
99 #define SDXC_IDMAC_DES0_LD BIT(2) /* 1-this data buffer is the last buffer */
100 #define SDXC_IDMAC_DES0_FD BIT(3) /* 1-data buffer is the first buffer, 0-data buffer contained in the next descriptor is the first data buffer */
101 #define SDXC_IDMAC_DES0_CH BIT(4) /* 1-the 2nd address in the descriptor is the next descriptor address */
102 #define SDXC_IDMAC_DES0_ER BIT(5) /* 1-last descriptor flag when using dual data buffer in descriptor */
103 #define SDXC_IDMAC_DES0_CES BIT(30) /* transfer error flag */
104 #define SDXC_IDMAC_DES0_OWN BIT(31) /* des owner:1-idma owns it, 0-host owns it */
105
106 uint32_t data_buf1_sz :16,
107 data_buf2_sz :16;
108
109 uint32_t buf_addr_ptr1;
110 uint32_t buf_addr_ptr2;
111 } smc_idma_des;
112
113 #ifdef SDC_DES_ADDR_SHIFT
114 #define SDXC_IDMAC_DES_ADDR(a) ((a)>>SDC_DES_ADDR_SHIFT)
115 #else
116 #define SDXC_IDMAC_DES_ADDR(a) ((a)>>0)
117 #endif
118
119 typedef enum
120 {
121 SDC_STATE_RESET = 0x00, /* Peripheral is not yet Initialized */
122 SDC_STATE_READY = 0x02, /* Peripheral Initialized and ready for use */
123 SDC_STATE_BUSY = 0x04, /* An internal process is ongoing */
124 SDC_STATE_ERROR = 0x08 /* Error */
125 } SDC_StateTypeDef;
126
127 struct __mci_ctrl_regs {
128 uint32_t gctrl;
129 uint32_t clkc;
130 uint32_t timeout;
131 uint32_t buswid;
132 uint32_t waterlvl;
133 uint32_t funcsel;
134 uint32_t idmacc;
135 };
136
137 struct mmc_bus_ops {
138 int (*suspend)(struct mmc_host *);
139 int (*resume)(struct mmc_host *);
140 };
141
142 struct mmc_host {
143 volatile void *reg_base; /* Mapped address */
144 uint8_t sdc_id;
145 uint8_t pin_ref;
146 uint16_t ref;
147 uint16_t debug_mask;
148 uint16_t dma_use;
149 struct mmc_card *card;
150 #ifdef CONFIG_SDC_SUPPORT_1V8
151 uint32_t voltage;
152 #define SDC_WOLTAGE_3V3 (0)
153 #define SDC_WOLTAGE_1V8 (1)
154 #define SDC_WOLTAGE_1V2 (2)
155 #define SDC_WOLTAGE_OFF (3)
156 #define SDC_WOLTAGE_ON (4)
157 uint32_t voltage_switching;
158 #endif
159 volatile uint32_t present;
160 uint16_t power_on;
161 uint16_t suspend;
162 uint32_t int_err; /* for Interrupt Controller */
163
164 uint32_t int_use; /* Control */
165 uint32_t int_sum; /* interrupt summary */
166 uint16_t trans_done;
167 uint16_t dma_done;
168 uint32_t buswidth; /* current card bus width */
169 uint32_t blkcnt;
170
171 /* NOTE: define idma_des here for aligned8! */
172 smc_idma_des *idma_des;
173 smc_idma_des *dma_hdle;
174 int8_t *align_dma_buf;
175
176 /* host specific block data */
177 uint32_t max_seg_size; /* see blk_queue_max_segment_size */
178 uint32_t max_segs; /* see blk_queue_max_segments */
179 uint32_t max_req_size; /* maximum number of bytes in one req */
180 uint32_t max_blk_size; /* maximum size of one mmc block */
181 uint32_t max_blk_count; /* maximum number of blocks in one req */
182 uint32_t ocr_avail;
183
184 #define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */
185 #define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */
186 #define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */
187 #define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */
188 #define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */
189 #define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */
190 #define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */
191 #define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */
192 #define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */
193 #define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */
194 #define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */
195 #define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */
196 #define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */
197 #define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */
198 #define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */
199 #define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */
200 #define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */
201
202 uint32_t caps; /* Host capabilities */
203
204 #define MMC_CAP_4_BIT_DATA (1 << 0) /* Can the host do 4 bit transfers */
205 #define MMC_CAP_MMC_HIGHSPEED (1 << 1) /* Can do MMC high-speed timing */
206 #define MMC_CAP_SD_HIGHSPEED (1 << 2) /* Can do SD high-speed timing */
207 #define MMC_CAP_SDIO_IRQ (1 << 3) /* Can signal pending SDIO IRQs */
208 #define MMC_CAP_SPI (1 << 4) /* Talks only SPI protocols */
209 #define MMC_CAP_NEEDS_POLL (1 << 5) /* Needs polling for card-detection */
210 #define MMC_CAP_8_BIT_DATA (1 << 6) /* Can the host do 8 bit transfers */
211
212 #define MMC_CAP_NONREMOVABLE (1 << 8) /* Nonremovable e.g. eMMC */
213 #define MMC_CAP_WAIT_WHILE_BUSY (1 << 9) /* Waits while card is busy */
214 #define MMC_CAP_ERASE (1 << 10) /* Allow erase/trim commands */
215 #define MMC_CAP_1_8V_DDR (1 << 11) /* can support */
216 /* DDR mode at 1.8V */
217 #define MMC_CAP_1_2V_DDR (1 << 12) /* can support */
218 /* DDR mode at 1.2V */
219 #define MMC_CAP_POWER_OFF_CARD (1 << 13) /* Can power off after boot */
220 #define MMC_CAP_BUS_WIDTH_TEST (1 << 14) /* CMD14/CMD19 bus width ok */
221 #define MMC_CAP_UHS_SDR12 (1 << 15) /* Host supports UHS SDR12 mode */
222 #define MMC_CAP_UHS_SDR25 (1 << 16) /* Host supports UHS SDR25 mode */
223 #define MMC_CAP_UHS_SDR50 (1 << 17) /* Host supports UHS SDR50 mode */
224 #define MMC_CAP_UHS_SDR104 (1 << 18) /* Host supports UHS SDR104 mode */
225 #define MMC_CAP_UHS_DDR50 (1 << 19) /* Host supports UHS DDR50 mode */
226 #define MMC_CAP_SET_XPC_330 (1 << 20) /* Host supports >150mA current at 3.3V */
227 #define MMC_CAP_SET_XPC_300 (1 << 21) /* Host supports >150mA current at 3.0V */
228 #define MMC_CAP_SET_XPC_180 (1 << 22) /* Host supports >150mA current at 1.8V */
229 #define MMC_CAP_DRIVER_TYPE_A (1 << 23) /* Host supports Driver Type A */
230 #define MMC_CAP_DRIVER_TYPE_C (1 << 24) /* Host supports Driver Type C */
231 #define MMC_CAP_DRIVER_TYPE_D (1 << 25) /* Host supports Driver Type D */
232 #define MMC_CAP_MAX_CURRENT_200 (1 << 26) /* Host max current limit is 200mA */
233 #define MMC_CAP_MAX_CURRENT_400 (1 << 27) /* Host max current limit is 400mA */
234 #define MMC_CAP_MAX_CURRENT_600 (1 << 28) /* Host max current limit is 600mA */
235 #define MMC_CAP_MAX_CURRENT_800 (1 << 29) /* Host max current limit is 800mA */
236 #define MMC_CAP_CMD23 (1 << 30) /* CMD23 supported. */
237 #define MMC_CAP_HW_RESET (1 << 31) /* Hardware reset */
238
239 uint32_t caps2; /* More host capabilities */
240
241 #define MMC_CAP2_BOOTPART_NOACC (1 << 0) /* Boot partition no access */
242 #define MMC_CAP2_CACHE_CTRL (1 << 1) /* Allow cache control */
243 #define MMC_CAP2_POWEROFF_NOTIFY (1 << 2) /* Notify poweroff supported */
244 #define MMC_CAP2_NO_MULTI_READ (1 << 3) /* Multiblock reads don't work */
245 #define MMC_CAP2_NO_SLEEP_CMD (1 << 4) /* Don't allow sleep command */
246 #define MMC_CAP2_HS200_1_8V_SDR (1 << 5) /* can support */
247 #define MMC_CAP2_HS200_1_2V_SDR (1 << 6) /* can support */
248 #define MMC_CAP2_HS200 (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS200_1_2V_SDR)
249 #define MMC_CAP2_BROKEN_VOLTAGE (1 << 7) /* Use the broken voltage */
250 #define MMC_CAP2_DETECT_ON_ERR (1 << 8) /* On I/O err check card removal */
251 #define MMC_CAP2_HC_ERASE_SZ (1 << 9) /* High-capacity erase size */
252 #define MMC_CAP2_SDIO_IRQ_NOTHREAD (1 << 17)
253
254
255 #ifdef CONFIG_SDC_OS_USED
256 SDC_Semaphore lock;
257 SDC_Mutex thread_lock;
258 #ifdef CONFIG_DETECT_CARD
259 SDC_Timer cd_timer;
260 #endif
261 #ifdef CONFIG_SDC_EXCLUSIVE_HOST
262 SDC_Semaphore exclusive_lock; /* lock for claim and bus ops */
263 #endif
264 #endif
265
266 //uint8_t bus_width; /* data bus width */
267 uint32_t clk;
268
269 #define MMC_BUS_WIDTH_1 0
270 #define MMC_BUS_WIDTH_4 2
271 #define MMC_BUS_WIDTH_8 3
272
273 struct mmc_request *mrq;
274
275 #define SDC_WAIT_NONE BIT(0)
276 #define SDC_WAIT_CMD_DONE BIT(1)
277 #define SDC_WAIT_DATA_OVER BIT(2)
278 #define SDC_WAIT_AUTOCMD_DONE BIT(3)
279 #define SDC_WAIT_IDMA_DONE BIT(4)
280 #define SDC_WAIT_IDMA_ERR BIT(5)
281 #define SDC_WAIT_ERROR BIT(6)
282 #define SDC_WAIT_RXDATA_OVER (SDC_WAIT_DATA_OVER|SDC_WAIT_IDMA_DONE)
283 #define SDC_WAIT_RXAUTOCMD_DONE (SDC_WAIT_AUTOCMD_DONE|SDC_WAIT_IDMA_DONE)
284 #define SDC_WAIT_SWITCH1V8 BIT(7)
285 #define SDC_WAIT_FINALIZE BIT(8)
286 volatile uint32_t smc_cmd;
287
288 uint32_t wait;
289 //#ifdef CONFIG_SDIO_IRQ_SUPPORT
290 uint32_t sdio_int;
291 unsigned int sdio_irqs;
292 OS_Thread_t sdio_irq_thread;
293 uint32_t sdio_irq_pending;
294 //atomic_t sdio_irq_thread_abort;
295 uint32_t sdio_irq_thread_abort;
296 uint32_t sdio_irq_thread_stop;
297 SDC_Semaphore sdio_irq_stop_wait;
298 SDC_Semaphore sdio_irq_signal;
299 //#endif
300 #ifdef CONFIG_SD_PM
301 struct __mci_ctrl_regs regs_back;
302 const struct mmc_bus_ops *bus_ops; /* current bus driver */
303 uint32_t pm_flags; /* requested pm features */
304 uint32_t pm_caps; /* supported pm features */
305 #endif
306 #ifdef __CONFIG_ARCH_APP_CORE
307 SDC_InitTypeDef param;
308 GPIO_Port cd_port;
309 GPIO_Pin cd_pin;
310 uint32_t cd_irq;
311 gpio_pin_t cd_gpio_pin;
312 irq_handler_t cd_gpio_isr;
313 uint16_t cd_delay; /* delay interval (in ms) to wait power stable */
314 uint8_t wait_voltage_stable; /* card voltage stable*/
315 GPIO_PinState cd_pin_present_val;
316 #endif
317 #ifdef CONFIG_SDC_READONLY_USED
318 uint32_t read_only;
319 GPIO_PinMuxParam ro_gpio;
320 #endif
321 SDC_StateTypeDef State;
322 uint32_t sdio_irq_mask;
323
324 #ifdef SD_PERF_TRACE_ON
325 uint64_t start_sdio_irq_times_ns;
326 uint64_t sdio_irq_count;
327 uint64_t sdio_irq_times_ns;
328
329
330 uint64_t start_times_us;
331 uint64_t rbytes;
332 uint64_t wbytes;
333 uint64_t rcount;
334 uint64_t rtimes_us;
335 uint64_t wtimes_us;
336 uint64_t wcount;
337 #endif
338
339 };
340
341 #define SDC_MAX_CPU_TRANS_LEN (4)
342 //#define SDC_MAX_CPU_TRANS_LEN (64)
343
344 //#define SMC_LOW_POWER_MODE 0 /* 1--Close Clock when Idle, 0--Clock always on */
345 /* IDMA control */
346 #define IDMAC_DES_MODE 0 /* 0-chain mode, 1-fix skip length */
347
348 #define SMC_RX_WLEVEL 7
349 #define SMC_TX_WLEVEL 248
350 #define BURST_SIZE 2
351
352 #define IDMA_MAX_TBKNUM_ONETIME 16
353
354 /* registers define */
355 //#define SMC0_BASE (SDC0_BASE)
356 //#if defined(__CONFIG_CHIP_XR871_PLUS)
357 //#define SMC1_BASE (0xA0001000)
358 //#elif (__CONFIG_CHIP_ARCH_VER == 2)
359 //#define SMC1_BASE (SDC1_BASE)
360 //#endif
361 #define SDXC_REG_GCTRL (0x00) /* SMC Global Control Register */
362 #define SDXC_REG_CLKCR (0x04) /* SMC Clock Control Register */
363 #define SDXC_REG_TMOUT (0x08) /* SMC Time Out Register */
364 #define SDXC_REG_WIDTH (0x0C) /* SMC Bus Width Register */
365 #define SDXC_REG_BLKSZ (0x10) /* SMC Block Size Register */
366 #define SDXC_REG_BCNTR (0x14) /* SMC Byte Count Register */
367 #define SDXC_REG_CMDR (0x18) /* SMC Command Register */
368 #define SDXC_REG_CARG (0x1C) /* SMC Argument Register */
369 #define SDXC_REG_RESP0 (0x20) /* SMC Response Register 0 */
370 #define SDXC_REG_RESP1 (0x24) /* SMC Response Register 1 */
371 #define SDXC_REG_RESP2 (0x28) /* SMC Response Register 2 */
372 #define SDXC_REG_RESP3 (0x2C) /* SMC Response Register 3 */
373 #define SDXC_REG_IMASK (0x30) /* SMC Interrupt Mask Register */
374 #define SDXC_REG_MISTA (0x34) /* SMC Masked Interrupt Status Register */
375 #define SDXC_REG_RINTR (0x38) /* SMC Raw Interrupt Status Register */
376 #define SDXC_REG_STAS (0x3C) /* SMC Status Register */
377 #define SDXC_REG_FTRGL (0x40) /* SMC FIFO Threshold Watermark Register */
378 #define SDXC_REG_FUNS (0x44) /* SMC Function Select Register */
379 #define SDXC_REG_CBCR (0x48) /* SMC CIU Byte Count Register */
380 #define SDXC_REG_BBCR (0x4C) /* SMC BIU Byte Count Register */
381 #define SDXC_REG_DBGC (0x50) /* SMC Debug Enable Register */
382 #define SDXC_REG_A12A (0x58) /* SMC auto command 12 argument */
383 #define SDXC_REG_NTSR (0x5C) /* SMC NewTiming Set Register(RX TX) */
384 #define SDXC_REG_SDEG (0x60) /* SMC NewTiming Set debg */
385 #define SDXC_REG_HWST (0x78) /* SMC SMC hardware reset register */
386 #define SDXC_REG_DMAC (0x80) /* SMC IDMAC Control Register */
387 #define SDXC_REG_DLBA (0x84) /* SMC IDMAC Descriptor List Base Address Register */
388 #define SDXC_REG_IDST (0x88) /* SMC IDMAC Status Register */
389 #define SDXC_REG_IDIE (0x8C) /* SMC IDMAC Interrupt Enable Register */
390 #define SDXC_REG_CHDA (0x90) /* SMC Current Host Descriptor Address Register */
391 #define SDXC_REG_CBDA (0x94) /* SMC Current Buffer Descriptor Address Register */
392 #define SDXC_REG_THLDC (0x100) /* SMC Threshold Control Register */
393 #define SDXC_REG_DSBD (0x10C)
394 #define SDXC_REG_RESP_CRC (0x110)
395 #define SDXC_REG_DAT7_CRC (0x114)
396 #define SDXC_REG_DAT6_CRC (0x118)
397 #define SDXC_REG_DAT5_CRC (0x11C)
398 #define SDXC_REG_DAT4_CRC (0x120)
399 #define SDXC_REG_DAT3_CRC (0x124)
400 #define SDXC_REG_DAT2_CRC (0x128)
401 #define SDXC_REG_DAT1_CRC (0x12C)
402 #define SDXC_REG_DAT0_CRC (0x130)
403 #define SDXC_REG_CRC_STA (0x134)
404 #define SDXC_REG_FIFO (0x200) /* SMC FIFO Access Address */
405
406 #define SDXC_REG_FCTL (0x64) /* SMC FIFO Access Address */
407 #define SDXC_REG_FCTL_OS (0x64) /* SMC FIFO Access Address */
408
409 /* global control register */
410 #define SDXC_SoftReset BIT(0 )
411 #define SDXC_FIFOReset BIT(1 )
412 #define SDXC_DMAReset BIT(2 )
413 #define SDXC_HWReset (SDXC_SoftReset|SDXC_FIFOReset|SDXC_DMAReset)
414 #define SDXC_INTEnb BIT(4 )
415 #define SDXC_DMAEnb BIT(5 )
416 #define SDXC_DebounceEnb BIT(8 )
417 #define SDXC_DDR_MODE BIT(10)
418 #define SDXC_MemAccessDone BIT(29)
419 #define SDXC_AccessDoneDirect BIT(30)
420 #define SDXC_ACCESS_BY_AHB BIT(31)
421 #define SDXC_ACCESS_BY_DMA (0x0U << 31)
422
423 /* Clock control */
424 #define SDXC_CardClkOn (0x1U << 16)
425 #define SDXC_LowPowerOn (0x1U << 17)
426 #define SDXC_Mask_Data0 BIT(31)
427
428 /* bus width */
429 #define SDXC_WIDTH1 (0)
430 #define SDXC_WIDTH4 (1)
431 #define SDXC_WIDTH8 (2)
432
433 /* Struct for SMC Commands */
434 #define SDXC_CMD_OPCODE (0x3F ) /* 0x00000040 */
435 #define SDXC_RspExp BIT(6 ) /* 0x00000080 */
436 #define SDXC_LongRsp BIT(7 ) /* 0x00000100 */
437 #define SDXC_CheckRspCRC BIT(8 ) /* 0x00000200 */
438 #define SDXC_DataExp BIT(9 ) /* 0x00000000 */
439 #define SDXC_Read (0x0U<<10 ) /* 0x00000400 */
440 #define SDXC_Write BIT(10) /* 0x00000000 */
441 #define SDXC_Blockmod (0x0U<<11 ) /* 0x00000800 */
442 #define SDXC_Seqmod BIT(11) /* 0x00001000 */
443 #define SDXC_SendAutoStop BIT(12) /* 0x00002000 */
444 #define SDXC_WaitPreOver BIT(13) /* 0x00004000 */
445 #define SDXC_StopAbortCMD BIT(14) /* 0x00008000 */
446 #define SDXC_SendInitSeq BIT(15) /* 0x00200000 */
447 #define SDXC_UPCLKOnly BIT(21) /* 0x00400000 */
448 #define SDXC_RdCEATADev BIT(22) /* 0x00800000 */
449 #define SDXC_CCSExp BIT(23) /* 0x01000000 */
450 #define SDXC_EnbBoot BIT(24) /* 0x02000000 */
451 #define SDXC_AltBootOpt BIT(25) /* 0x00000000 */
452 #define SDXC_MandBootOpt (0x0U<<25) /* 0x04000000 */
453 #define SDXC_BootACKExp BIT(26) /* 0x08000000 */
454 #define SDXC_DisableBoot BIT(27) /* 0x10000000 */
455 #define SDXC_VolSwitch BIT(28) /* 0x80000000 */
456 #define SDXC_Start BIT(31)
457
458 /* Struct for Intrrrupt Information */
459 #define SDXC_RespErr BIT(1) /* 0x00000002 */
460 #define SDXC_CmdDone BIT(2) /* 0x00000004 */
461 #define SDXC_DataOver BIT(3) /* 0x00000008 */
462 #define SDXC_TxDataReq BIT(4) /* 0x00000010 */
463 #define SDXC_RxDataReq BIT(5) /* 0x00000020 */
464 #define SDXC_RespCRCErr BIT(6) /* 0x00000040 */
465 #define SDXC_DataCRCErr BIT(7) /* 0x00000080 */
466 #define SDXC_RespTimeout BIT(8) /* 0x00000100 */
467 #define SDXC_ACKRcv BIT(8) /* 0x00000100 */
468 #define SDXC_DataTimeout BIT(9) /* 0x00000200 */
469 #define SDXC_BootStart BIT(9) /* 0x00000200 */
470 #define SDXC_DataStarve BIT(10) /* 0x00000400 */
471 #define SDXC_VolChgDone BIT(10) /* 0x00000400 */
472 #define SDXC_FIFORunErr BIT(11) /* 0x00000800 */
473 #define SDXC_HardWLocked BIT(12) /* 0x00001000 */
474 #define SDXC_StartBitErr BIT(13) /* 0x00002000 */
475 #define SDXC_AutoCMDDone BIT(14) /* 0x00004000 */
476 #define SDXC_EndBitErr BIT(15) /* 0x00008000 */
477 #define SDXC_SDIOInt BIT(16) /* 0x00010000 */
478 #define SDXC_CardInsert BIT(30) /* 0x40000000 */
479 #define SDXC_CardRemove BIT(31) /* 0x80000000 */
480 #define SDXC_IntErrBit (SDXC_RespErr | SDXC_RespCRCErr | SDXC_DataCRCErr | SDXC_RespTimeout | SDXC_DataTimeout | \
481 SDXC_FIFORunErr | SDXC_HardWLocked | SDXC_StartBitErr | SDXC_EndBitErr) /* 0xbbc2 */
482 /* status */
483 #define SDXC_RXWLFlag BIT(0)
484 #define SDXC_TXWLFlag BIT(1)
485 #define SDXC_FIFOEmpty BIT(2)
486 #define SDXC_FIFOFull BIT(3)
487 #define SDXC_CardPresent BIT(8)
488 #define SDXC_CardDataBusy BIT(9)
489 #define SDXC_DataFSMBusy BIT(10)
490 #define SDXC_DMAReq BIT(31)
491
492 /* Function select */
493 #define SDXC_CEATAOn (0xceaaU << 16)
494 #define SDXC_SendIrqRsp BIT(0)
495 #define SDXC_SDIORdWait BIT(1)
496 #define SDXC_AbtRdData BIT(2)
497 #define SDXC_SendCCSD BIT(8)
498 #define SDXC_SendAutoStopCCSD BIT(9)
499 #define SDXC_CEATADevIntEnb BIT(10)
500 /* status bit */
501 #define SDXC_CardBusy BIT(9)
502 /* IDMA controller bus mod bit field */
503 #define SDXC_IDMACSoftRST BIT(0)
504 #define SDXC_IDMACFixBurst BIT(1)
505 #define SDXC_IDMACIDMAOn BIT(7)
506 #define SDXC_IDMACRefetchDES BIT(31)
507
508 /* IDMA status bit field */
509 #define SDXC_IDMACTransmitInt BIT(0)
510 #define SDXC_IDMACReceiveInt BIT(1)
511 #define SDXC_IDMACFatalBusErr BIT(2)
512 #define SDXC_IDMACDesInvalid BIT(4)
513 #define SDXC_IDMACCardErrSum BIT(5)
514 #define SDXC_IDMACNormalIntSum BIT(8)
515 #define SDXC_IDMACAbnormalIntSum BIT(9)
516 #define SDXC_IDMACHostAbtInTx BIT(10)
517 #define SDXC_IDMACHostAbtInRx BIT(10)
518 #define SDXC_IDMACIdle (0x0U << 13)
519 #define SDXC_IDMACSuspend (0x1U << 13)
520 #define SDXC_IDMACDESCRd (0x2U << 13)
521 #define SDXC_IDMACDESCCheck (0x3U << 13)
522 #define SDXC_IDMACRdReqWait (0x4U << 13)
523 #define SDXC_IDMACWrReqWait (0x5U << 13)
524 #define SDXC_IDMACRd (0x6U << 13)
525 #define SDXC_IDMACWr (0x7U << 13)
526 #define SDXC_IDMACDESCClose (0x8U << 13)
527
528 #define SDXC_IDMA_OVER (SDXC_IDMACTransmitInt|SDXC_IDMACReceiveInt|SDXC_IDMACNormalIntSum)
529 #define SDXC_IDMA_ERR (SDXC_IDMACFatalBusErr|SDXC_IDMACDesInvalid|SDXC_IDMACCardErrSum|SDXC_IDMACAbnormalIntSum)
530
531 /*
532 * These flags are used to describe power management features that
533 * some cards (typically SDIO cards) might wish to benefit from when
534 * the host system is being suspended. There are several layers of
535 * abstractions involved, from the host controller driver, to the MMC core
536 * code, to the SDIO core code, to finally get to the actual SDIO function
537 * driver. This file is therefore used for common definitions shared across
538 * all those layers.
539 */
540
541 #define MMC_PM_KEEP_POWER (1 << 0) /* preserve card power during suspend */
542 #define MMC_PM_WAKE_SDIO_IRQ (1 << 1) /* wake up host system on SDIO IRQ assertion */
543 #define MMC_PM_IGNORE_PM_NOTIFY (1 << 2) /* ignore mmc pm notify */
544
545 #ifdef CONFIG_SD_PM
mmc_card_keep_power(struct mmc_host * host)546 static inline int mmc_card_keep_power(struct mmc_host *host)
547 {
548 return host->pm_flags & MMC_PM_KEEP_POWER;
549 }
550
mmc_card_wake_sdio_irq(struct mmc_host * host)551 static inline int mmc_card_wake_sdio_irq(struct mmc_host *host)
552 {
553 return host->pm_flags & MMC_PM_WAKE_SDIO_IRQ;
554 }
555 #endif
556
557 #ifdef CONFIG_SDC_READONLY_USED
558 extern int32_t HAL_SDC_Get_ReadOnly(struct mmc_host *host);
559 #endif
560 extern void HAL_SDC_Set_BusWidth(struct mmc_host *host, uint32_t width);
561 extern uint32_t HAL_SDC_Is_Busy(struct mmc_host *host);
562 #ifdef CONFIG_SDC_EXCLUSIVE_HOST
563 extern int32_t HAL_SDC_Claim_Host(struct mmc_host *host);
564 extern void HAL_SDC_Release_Host(struct mmc_host *host);
565 #else
HAL_SDC_Claim_Host(struct mmc_host * host)566 static inline int32_t HAL_SDC_Claim_Host(struct mmc_host *host) { return 0; }
HAL_SDC_Release_Host(struct mmc_host * host)567 static inline void HAL_SDC_Release_Host(struct mmc_host *host) { ; }
568 #endif
569
570 #ifdef __CONFIG_ROM
571
572 #include "rom/ram_table.h"
573
574 #define HAL_SDC_Update_Clk \
575 RAM_TBL_FUN(int32_t (*)(struct mmc_host *host, uint32_t clk), HAL_SDC_Update_Clk)
576
577 #define HAL_SDC_Clk_PWR_Opt \
578 RAM_TBL_FUN(int32_t (*)(struct mmc_host *host, uint32_t oclk_en, uint32_t pwr_save), HAL_SDC_Clk_PWR_Opt)
579
580 #define HAL_SDC_PowerOn \
581 RAM_TBL_FUN(int32_t (*)(struct mmc_host *host), HAL_SDC_PowerOn)
582
583 #define HAL_SDC_PowerOff \
584 RAM_TBL_FUN(int32_t (*)(struct mmc_host *host), HAL_SDC_PowerOff)
585
586 #define HAL_SDC_Request \
587 RAM_TBL_FUN(int32_t (*)(struct mmc_host *host, struct mmc_request *mrq), HAL_SDC_Request)
588
589 #define HAL_SDC_Enable_Sdio_Irq \
590 RAM_TBL_FUN(void (*)(struct mmc_host *host, int enable), HAL_SDC_Enable_Sdio_Irq)
591
592 #else
593
594 extern int32_t HAL_SDC_Update_Clk(struct mmc_host *host, uint32_t clk);
595 extern int32_t HAL_SDC_Clk_PWR_Opt(struct mmc_host *host, uint32_t oclk_en, uint32_t pwr_save);
596 extern int32_t HAL_SDC_PowerOn(struct mmc_host *host);
597 extern int32_t HAL_SDC_PowerOff(struct mmc_host *host);
598 extern int32_t HAL_SDC_Request(struct mmc_host *host, struct mmc_request *mrq);
599 extern void HAL_SDC_Enable_Sdio_Irq(struct mmc_host *host, int enable);
600
601
602
603
604 #define rom_HAL_SDC_Update_Clk HAL_SDC_Update_Clk
605 #define rom_HAL_SDC_Clk_PWR_Opt HAL_SDC_Clk_PWR_Opt
606 #define rom_HAL_SDC_PowerOn HAL_SDC_PowerOn
607 #define rom_HAL_SDC_PowerOff HAL_SDC_PowerOff
608 #define rom_HAL_SDC_Request HAL_SDC_Request
609 #define rom_HAL_SDC_Enable_Sdio_Irq HAL_SDC_Enable_Sdio_Irq
610
611 #endif /* __CONFIG_ROM */
612
613 #ifdef __cplusplus
614 }
615 #endif
616
617 #endif /* _ROM_DRIVER_CHIP_SDMMC__SDHOST_H_ */
618