1 /** 2 ****************************************************************************** 3 * @file tae32f53xx_ll_dma.h 4 * @author MCD Application Team 5 * @brief Header file for DMA LL module. 6 * 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2020 Tai-Action. 11 * All rights reserved.</center></h2> 12 * 13 * This software is licensed by Tai-Action under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef _TAE32F53XX_LL_DMA_H_ 23 #define _TAE32F53XX_LL_DMA_H_ 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif /* __cplusplus */ 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include "tae32f53xx_ll_def.h" 31 32 33 /** @addtogroup TAE32F53xx_LL_Driver 34 * @{ 35 */ 36 37 /** @addtogroup DMA_LL 38 * @{ 39 */ 40 41 42 /* Exported constants --------------------------------------------------------*/ 43 /** @defgroup DMA_LL_Exported_Constants DMA LL Exported Constants 44 * @brief DMA LL Exported Constants 45 * @{ 46 */ 47 48 /** 49 * @brief DMA block size max 50 */ 51 #define LL_DMA_BLOCK_SIZE_MAX (0xfffU) 52 53 /** 54 * @brief SRAMBC address start 55 */ 56 #define LL_DMA_SRMBC_ADDR_START (0x20004000UL) 57 58 /** 59 * @brief SRAMBC address end 60 */ 61 #define LL_DMA_SRMBC_ADDR_END (0x20006000UL - 1) 62 63 /** 64 * @} 65 */ 66 67 68 /* Exported types ------------------------------------------------------------*/ 69 /** @defgroup DMA_LL_Exported_Types DMA LL Exported Types 70 * @brief DMA LL Exported Types 71 * @{ 72 */ 73 74 /** 75 * @brief DMA Source Peripheral bus type definition 76 */ 77 typedef enum { 78 DMA_SRC_PERIPH_BUS_AHB_MST1 = DMA_CH_CR0_SMS_AHB_MST1, /*!< Source Peripheral bus AHB Master1 */ 79 DMA_SRC_PERIPH_BUS_AHB_MST2 = DMA_CH_CR0_SMS_AHB_MST2, /*!< Source Peripheral bus AHB Master2 */ 80 } DMA_SrcPeriphBusETypeDef; 81 82 /** 83 * @brief DMA Destination Peripheral bus type definition 84 */ 85 typedef enum { 86 DMA_DST_PERIPH_BUS_AHB_MST1 = DMA_CH_CR0_DMS_AHB_MST1, /*!< Destination Peripheral bus AHB Master1 */ 87 DMA_DST_PERIPH_BUS_AHB_MST2 = DMA_CH_CR0_DMS_AHB_MST2, /*!< Destination Peripheral bus AHB Master2 */ 88 } DMA_DstPeriphBusETypeDef; 89 90 /** 91 * brief DMA transfer type type definition 92 */ 93 typedef enum { 94 DMA_TRANS_TYPE_M2M = DMA_CH_CR0_TTC_M2M, /*!< Transfer type M2M */ 95 DMA_TRANS_TYPE_M2P = DMA_CH_CR0_TTC_M2P, /*!< Transfer type M2P */ 96 DMA_TRANS_TYPE_P2M = DMA_CH_CR0_TTC_P2M, /*!< Transfer type P2M */ 97 DMA_TRANS_TYPE_P2P = DMA_CH_CR0_TTC_P2P, /*!< Transfer type P2P */ 98 } DMA_TransTypeETypeDef; 99 100 /** 101 * @brief DMA Source burst length type definition 102 */ 103 typedef enum { 104 DMA_SRC_BURST_LEN_1 = DMA_CH_CR0_SBTL_1, /*!< Source burst length 1 */ 105 DMA_SRC_BURST_LEN_4 = DMA_CH_CR0_SBTL_4, /*!< Source burst length 4 */ 106 DMA_SRC_BURST_LEN_8 = DMA_CH_CR0_SBTL_8, /*!< Source burst length 8 */ 107 } DMA_SrcBurstLenETypeDef; 108 109 /** 110 * @brief DMA Destination burst length type definition 111 */ 112 typedef enum { 113 DMA_DST_BURST_LEN_1 = DMA_CH_CR0_DBTL_1, /*!< Destination burst length 1 */ 114 DMA_DST_BURST_LEN_4 = DMA_CH_CR0_DBTL_4, /*!< Destination burst length 4 */ 115 DMA_DST_BURST_LEN_8 = DMA_CH_CR0_DBTL_8, /*!< Destination burst length 8 */ 116 } DMA_DstBurstLenETypeDef; 117 118 /** 119 * @brief DMA Source address mode type definition 120 */ 121 typedef enum { 122 DMA_SRC_ADDR_MODE_INC = DMA_CH_CR0_SINC_INC, /*!< Source address mode Increase */ 123 DMA_SRC_ADDR_MODE_DEC = DMA_CH_CR0_SINC_DEC, /*!< Source address mode Decrease */ 124 DMA_SRC_ADDR_MODE_FIX = DMA_CH_CR0_SINC_FIX, /*!< Source address mode Fixed */ 125 } DMA_SrcAddrModeETypeDef; 126 127 /** 128 * @brief DMA Destination address mode type definition 129 */ 130 typedef enum { 131 DMA_DST_ADDR_MODE_INC = DMA_CH_CR0_DINC_INC, /*!< Destination address mode Increase */ 132 DMA_DST_ADDR_MODE_DEC = DMA_CH_CR0_DINC_DEC, /*!< Destination address mode Decrease */ 133 DMA_DST_ADDR_MODE_FIX = DMA_CH_CR0_DINC_FIX, /*!< Destination address mode Fixed */ 134 } DMA_DstAddrModeETypeDef; 135 136 /** 137 * @brief DMA Source transfer width type definition 138 */ 139 typedef enum { 140 DMA_SRC_TRANS_WIDTH_8b = DMA_CH_CR0_STW_8b, /*!< Source transfer width 8bit */ 141 DMA_SRC_TRANS_WIDTH_16b = DMA_CH_CR0_STW_16b, /*!< Source transfer width 16bit */ 142 DMA_SRC_TRANS_WIDTH_32b = DMA_CH_CR0_STW_32b, /*!< Source transfer width 32bit */ 143 } DMA_SrcTransWidthETypeDef; 144 145 /** 146 * @brief DMA Destination transfer width type definition 147 */ 148 typedef enum { 149 DMA_DST_TRANS_WIDTH_8b = DMA_CH_CR0_DTW_8b, /*!< Destination transfer width 8bit */ 150 DMA_DST_TRANS_WIDTH_16b = DMA_CH_CR0_DTW_16b, /*!< Destination transfer width 16bit */ 151 DMA_DST_TRANS_WIDTH_32b = DMA_CH_CR0_DTW_32b, /*!< Destination transfer width 32bit */ 152 } DMA_DstTransWidthETypeDef; 153 154 /** 155 * @brief DMA Source handshaking interface type definition 156 */ 157 typedef enum { 158 DMA_SRC_HANDSHAKE_IFC_MEMORY = 0, /*!< Source handshaking interface MEMORY */ 159 DMA_SRC_HANDSHAKE_IFC_I2C0_TX = DMA_CH_CR3_SHSIF_I2C0_TX, /*!< Source handshaking interface I2C0_TX */ 160 DMA_SRC_HANDSHAKE_IFC_I2C0_RX = DMA_CH_CR3_SHSIF_I2C0_RX, /*!< Source handshaking interface I2C0_RX */ 161 DMA_SRC_HANDSHAKE_IFC_I2C1_TX = DMA_CH_CR3_SHSIF_I2C1_TX, /*!< Source handshaking interface I2C1_TX */ 162 DMA_SRC_HANDSHAKE_IFC_I2C1_RX = DMA_CH_CR3_SHSIF_I2C1_RX, /*!< Source handshaking interface I2C1_RX */ 163 DMA_SRC_HANDSHAKE_IFC_UART0_TX = DMA_CH_CR3_SHSIF_UART0_TX, /*!< Source handshaking interface UART0_TX */ 164 DMA_SRC_HANDSHAKE_IFC_UART0_RX = DMA_CH_CR3_SHSIF_UART0_RX, /*!< Source handshaking interface UART0_RX */ 165 DMA_SRC_HANDSHAKE_IFC_UART1_TX = DMA_CH_CR3_SHSIF_UART1_TX, /*!< Source handshaking interface UART1_TX */ 166 DMA_SRC_HANDSHAKE_IFC_UART1_RX = DMA_CH_CR3_SHSIF_UART1_RX, /*!< Source handshaking interface UART1_RX */ 167 } DMA_SrcHandshakeIfcETypeDef; 168 169 /** 170 * @brief DMA Destination handshaking interface type definition 171 */ 172 typedef enum { 173 DMA_DST_HANDSHAKE_IFC_MEMORY = 0, /*!< Destination handshaking interface MEMORY */ 174 DMA_DST_HANDSHAKE_IFC_I2C0_TX = DMA_CH_CR3_DHSIF_I2C0_TX, /*!< Destination handshaking interface I2C0_TX */ 175 DMA_DST_HANDSHAKE_IFC_I2C0_RX = DMA_CH_CR3_DHSIF_I2C0_RX, /*!< Destination handshaking interface I2C0_RX */ 176 DMA_DST_HANDSHAKE_IFC_I2C1_TX = DMA_CH_CR3_DHSIF_I2C1_TX, /*!< Destination handshaking interface I2C1_TX */ 177 DMA_DST_HANDSHAKE_IFC_I2C1_RX = DMA_CH_CR3_DHSIF_I2C1_RX, /*!< Destination handshaking interface I2C1_RX */ 178 DMA_DST_HANDSHAKE_IFC_UART0_TX = DMA_CH_CR3_DHSIF_UART0_TX, /*!< Destination handshaking interface UART0_TX */ 179 DMA_DST_HANDSHAKE_IFC_UART0_RX = DMA_CH_CR3_DHSIF_UART0_RX, /*!< Destination handshaking interface UART0_RX */ 180 DMA_DST_HANDSHAKE_IFC_UART1_TX = DMA_CH_CR3_DHSIF_UART1_TX, /*!< Destination handshaking interface UART1_TX */ 181 DMA_DST_HANDSHAKE_IFC_UART1_RX = DMA_CH_CR3_DHSIF_UART1_RX, /*!< Destination handshaking interface UART1_RX */ 182 } DMA_DstHandshakeIfcETypeDef; 183 184 /** 185 * @brief DMA channel type definition 186 */ 187 typedef enum { 188 DMA_CHANNEL_0 = 0U, /*!< DMA Channel 0 */ 189 DMA_CHANNEL_1 = 1U, /*!< DMA Channel 1 */ 190 DMA_CHANNEL_NUM = 2U, /*!< DMA Channel Number */ 191 DMA_CHANNEL_INVALID = 0xFFU, /*!< DMA Channel Invalid */ 192 } DMA_ChannelETypeDef; 193 194 /** 195 * @brief DMA State type definition 196 */ 197 typedef enum { 198 DMA_STATE_RESET = 0, /*!< DMA State Reset: not yet initialized or disabled */ 199 DMA_STATE_READY, /*!< DMA State Ready: initialized and ready for use */ 200 DMA_STATE_BUSY, /*!< DMA State Busy: process is ongoing */ 201 } DMA_StateETypeDef; 202 203 204 /** 205 * @brief DMA IRQ callback function type definition 206 */ 207 typedef void (*DMA_IRQCallback)(void *arg); 208 209 210 /** 211 * @brief DMA user config type definition 212 */ 213 typedef struct __DMA_UserCfgTypeDef { 214 DMA_TransTypeETypeDef trans_type; /*!< transfer type */ 215 DMA_SrcAddrModeETypeDef src_addr_mode; /*!< source address mode */ 216 DMA_DstAddrModeETypeDef dst_addr_mode; /*!< destination address mode */ 217 DMA_SrcTransWidthETypeDef src_data_width; /*!< source data width */ 218 DMA_DstTransWidthETypeDef dst_data_width; /*!< destination data width */ 219 DMA_SrcHandshakeIfcETypeDef src_hs_ifc; /*!< source handshake interface */ 220 DMA_DstHandshakeIfcETypeDef dst_hs_ifc; /*!< destination handshake interface */ 221 222 void *end_arg; /*!< argument of transfer complete callback fucntion */ 223 DMA_IRQCallback end_callback; /*!< transfer complete callback fucntion */ 224 void *err_arg; /*!< argument of transfer error callback fucntion */ 225 DMA_IRQCallback err_callback; /*!< transfer error callback fucntion */ 226 } DMA_UserCfgTypeDef; 227 228 /** 229 * @} 230 */ 231 232 233 /* Exported macro ------------------------------------------------------------*/ 234 /** @defgroup DMA_LL_Exported_Macros DMA LL Exported Macros 235 * @brief DMA LL Exported Macros 236 * @{ 237 */ 238 239 /** 240 * @brief Source address set 241 * @param __DMA__ Specifies DMA peripheral 242 * @param ch DMA channel 243 * @param addr Source address 244 * @return None 245 */ 246 #define __LL_DMA_SrcAddr_Set(__DMA__, ch, addr) WRITE_REG((__DMA__)->CH[(ch)].SAR, addr) 247 248 249 /** 250 * @brief Destination address set 251 * @param __DMA__ Specifies DMA peripheral 252 * @param ch DMA channel 253 * @param addr Destination address 254 * @return None 255 */ 256 #define __LL_DMA_DstAddr_Set(__DMA__, ch, addr) WRITE_REG((__DMA__)->CH[(ch)].DAR, addr) 257 258 259 /** 260 * @brief Source peripheral bus set 261 * @param __DMA__ Specifies DMA peripheral 262 * @param ch DMA channel 263 * @param bus Source peripheral bus 264 * @return None 265 */ 266 #define __LL_DMA_SrcPeriphBus_Set(__DMA__, ch, bus) MODIFY_REG((__DMA__)->CH[(ch)].CR0, DMA_CH_CR0_SMS_Msk, bus) 267 268 /** 269 * @brief Destination peripheral bus set 270 * @param __DMA__ Specifies DMA peripheral 271 * @param ch DMA channel 272 * @param bus Destination peripheral bus 273 * @return None 274 */ 275 #define __LL_DMA_DstPeriphBus_Set(__DMA__, ch, bus) MODIFY_REG((__DMA__)->CH[(ch)].CR0, DMA_CH_CR0_DMS_Msk, bus) 276 277 /** 278 * @brief Transfer type set 279 * @param __DMA__ Specifies DMA peripheral 280 * @param ch DMA channel 281 * @param type Transfer type 282 * @return None 283 */ 284 #define __LL_DMA_TransType_Set(__DMA__, ch, type) MODIFY_REG((__DMA__)->CH[(ch)].CR0, DMA_CH_CR0_TTC_Msk, type) 285 286 /** 287 * @brief Source burst length set 288 * @param __DMA__ Specifies DMA peripheral 289 * @param ch DMA channel 290 * @param len Source burst length 291 * @return None 292 */ 293 #define __LL_DMA_SrcBurstLen_Set(__DMA__, ch, len) MODIFY_REG((__DMA__)->CH[(ch)].CR0, DMA_CH_CR0_SBTL_Msk, len) 294 295 /** 296 * @brief Destination burst length set 297 * @param __DMA__ Specifies DMA peripheral 298 * @param ch DMA channel 299 * @param len Destination burst length 300 * @return None 301 */ 302 #define __LL_DMA_DstBurstLen_Set(__DMA__, ch, len) MODIFY_REG((__DMA__)->CH[(ch)].CR0, DMA_CH_CR0_DBTL_Msk, len) 303 304 /** 305 * @brief Source address mode set 306 * @param __DMA__ Specifies DMA peripheral 307 * @param ch DMA channel 308 * @param mode Source address mode 309 * @return None 310 */ 311 #define __LL_DMA_SrcAddrMode_Set(__DMA__, ch, mode) MODIFY_REG((__DMA__)->CH[(ch)].CR0, DMA_CH_CR0_SINC_Msk, mode) 312 313 /** 314 * @brief Destination address mode set 315 * @param __DMA__ Specifies DMA peripheral 316 * @param ch DMA channel 317 * @param mode Destination address mode 318 * @return None 319 */ 320 #define __LL_DMA_DstAddrMode_Set(__DMA__, ch, mode) MODIFY_REG((__DMA__)->CH[(ch)].CR0, DMA_CH_CR0_DINC_Msk, mode) 321 322 /** 323 * @brief Source transfer width set 324 * @param __DMA__ Specifies DMA peripheral 325 * @param ch DMA channel 326 * @param width Source transfer width 327 * @return None 328 */ 329 #define __LL_DMA_SrcTransWidth_Set(__DMA__, ch, width) MODIFY_REG((__DMA__)->CH[(ch)].CR0, DMA_CH_CR0_STW_Msk, width) 330 331 /** 332 * @brief Source transfer width get 333 * @param __DMA__ Specifies DMA peripheral 334 * @param ch DMA channel 335 * @retval 0 8 bits 336 * @retval 1 16 bits 337 * @retval 2 32 bits 338 */ 339 #define __LL_DMA_SrcTransWidth_Get(__DMA__, ch) (READ_BIT((__DMA__)->CH[(ch)].CR0, DMA_CH_CR0_STW_Msk) >> DMA_CH_CR0_STW_Pos) 340 341 /** 342 * @brief Destination transfer width set 343 * @param __DMA__ Specifies DMA peripheral 344 * @param ch DMA channel 345 * @param width Destination transfer width 346 * @return None 347 */ 348 #define __LL_DMA_DstTransWidth_Set(__DMA__, ch, width) MODIFY_REG((__DMA__)->CH[(ch)].CR0, DMA_CH_CR0_DTW_Msk, width) 349 350 /** 351 * @brief Channel interrupt enable 352 * @param __DMA__ Specifies DMA peripheral 353 * @param ch DMA channel 354 * @return None 355 */ 356 #define __LL_DMA_Channel_Int_En(__DMA__, ch) SET_BIT((__DMA__)->CH[(ch)].CR0, DMA_CH_CR0_CHIE_Msk) 357 358 /** 359 * @brief Channel interrupt disable 360 * @param __DMA__ Specifies DMA peripheral 361 * @param ch DMA channel 362 * @return None 363 */ 364 #define __LL_DMA_Channel_Int_Dis(__DMA__, ch) CLEAR_BIT((__DMA__)->CH[(ch)].CR0, DMA_CH_CR0_CHIE_Msk) 365 366 /** 367 * @brief Channel register CR0 write 368 * @param __DMA__ Specifies DMA peripheral 369 * @param ch DMA channel 370 * @param val write value 371 * @return None 372 */ 373 #define __LL_DMA_ChannelRegCR0_Write(__DMA__, ch, val) WRITE_REG((__DMA__)->CH[(ch)].CR0, val) 374 375 376 /** 377 * @brief Judge is block transfer done or not 378 * @param __DMA__ Specifies DMA peripheral 379 * @param ch DMA channel 380 * @retval 0 isn't block transfer done 381 * @retval 1 is block transfer done 382 */ 383 #define __LL_DMA_IsBlockTransDone(__DMA__, ch) (READ_BIT((__DMA__)->CH[(ch)].CR1, DMA_CH_CR1_DONE_Msk) >> DMA_CH_CR1_DONE_Pos) 384 385 /** 386 * @brief Block transfer done clear 387 * @param __DMA__ Specifies DMA peripheral 388 * @param ch DMA channel 389 * @return None 390 */ 391 #define __LL_DMA_BlockTransDone_Clr(__DMA__, ch) CLEAR_BIT((__DMA__)->CH[(ch)].CR1, DMA_CH_CR1_DONE_Msk) 392 393 /** 394 * @brief Block transfer count set 395 * @param __DMA__ Specifies DMA peripheral 396 * @param ch DMA channel 397 * @param cnt Block transfer count 398 * @return None 399 */ 400 #define __LL_DMA_BlockTransCnt_Set(__DMA__, ch, cnt) \ 401 MODIFY_REG((__DMA__)->CH[(ch)].CR1, DMA_CH_CR1_BTCNT_Msk, (((cnt) & 0xfffUL) << DMA_CH_CR1_BTCNT_Pos)) 402 403 /** 404 * @brief Channel register CR1 write 405 * @param __DMA__ Specifies DMA peripheral 406 * @param ch DMA channel 407 * @param val write value 408 * @return None 409 */ 410 #define __LL_DAM_ChannelRegCR1_Write(__DMA__, ch, val) WRITE_REG((__DMA__)->CH[(ch)].CR1, val) 411 412 413 /** 414 * @brief Burst length max set 415 * @param __DMA__ Specifies DMA peripheral 416 * @param ch DMA channel 417 * @param max Burst length max 418 * @return None 419 */ 420 #define __LL_DMA_BurstLenMax_Set(__DMA__, ch, max) \ 421 MODIFY_REG((__DMA__)->CH[(ch)].CR2, DMA_CH_CR2_MBL_Msk, (((max) & 0x3ffUL) << DMA_CH_CR2_MBL_Pos)) 422 423 /** 424 * @brief Source handshake mode set 425 * @param __DMA__ Specifies DMA peripheral 426 * @param ch DMA channel 427 * @return None 428 */ 429 #define __LL_DMA_SrcHandshakeMode_Set(__DMA__, ch) SET_BIT((__DMA__)->CH[(ch)].CR2, DMA_CH_CR2_SHSM_Msk) 430 431 /** 432 * @brief Source handshake mode clear 433 * @param __DMA__ Specifies DMA peripheral 434 * @param ch DMA channel 435 * @return None 436 */ 437 #define __LL_DMA_SrcHandshakeMode_Clr(__DMA__, ch) CLEAR_BIT((__DMA__)->CH[(ch)].CR2, DMA_CH_CR2_SHSM_Msk) 438 439 /** 440 * @brief Destination handshake mode set 441 * @param __DMA__ Specifies DMA peripheral 442 * @param ch DMA channel 443 * @return None 444 */ 445 #define __LL_DMA_DstHandshakeMode_Set(__DMA__, ch) SET_BIT((__DMA__)->CH[(ch)].CR2, DMA_CH_CR2_DHSM_Msk) 446 447 /** 448 * @brief Destination handshake mode clear 449 * @param __DMA__ Specifies DMA peripheral 450 * @param ch DMA channel 451 * @return None 452 */ 453 #define __LL_DMA_DstHandshakeMode_Clr(__DMA__, ch) CLEAR_BIT((__DMA__)->CH[(ch)].CR2, DMA_CH_CR2_DHSM_Msk) 454 455 /** 456 * @brief Judge is channel FIFO empty or not 457 * @param __DMA__ Specifies DMA peripheral 458 * @param ch DMA channel 459 * @retval 0 isn't channel FIFO empty 460 * @retval 1 is channel FIFO empty 461 */ 462 #define __LL_DMA_IsChannelFIFOEmpty(__DMA__, ch) \ 463 (READ_BIT((__DMA__)->CH[(ch)].CR2, DMA_CH_CR2_FIFO_EF_Msk) >> DMA_CH_CR2_FIFO_EF_Pos) 464 465 /** 466 * @brief Channel suspend set 467 * @param __DMA__ Specifies DMA peripheral 468 * @param ch DMA channel 469 * @return None 470 */ 471 #define __LL_DMA_ChannelSuspend_Set(__DMA__, ch) SET_BIT((__DMA__)->CH[(ch)].CR2, DMA_CH_CR2_SUSP_Msk) 472 473 /** 474 * @brief Channel suspend clear 475 * @param __DMA__ Specifies DMA peripheral 476 * @param ch DMA channel 477 * @return None 478 */ 479 #define __LL_DMA_ChannelSuspend_Clr(__DMA__, ch) CLEAR_BIT((__DMA__)->CH[(ch)].CR2, DMA_CH_CR2_SUSP_Msk) 480 481 /** 482 * @brief Channel priority set high 483 * @param __DMA__ Specifies DMA peripheral 484 * @param ch DMA channel 485 * @return None 486 */ 487 #define __LL_DMA_ChannelPriHigh_Set(__DMA__, ch) SET_BIT((__DMA__)->CH[(ch)].CR2, DMA_CH_CR2_PRI_Msk) 488 489 /** 490 * @brief Channel priority set low 491 * @param __DMA__ Specifies DMA peripheral 492 * @param ch DMA channel 493 * @return None 494 */ 495 #define __LL_DMA_ChannelPriLow_Set(__DMA__, ch) CLEAR_BIT((__DMA__)->CH[(ch)].CR2, DMA_CH_CR2_PRI_Msk) 496 497 /** 498 * @brief Channel register CR2 write 499 * @param __DMA__ Specifies DMA peripheral 500 * @param ch DMA channel 501 * @param val write value 502 * @return None 503 */ 504 #define __LL_DAM_ChannelRegCR2_Write(__DMA__, ch, val) WRITE_REG((__DMA__)->CH[(ch)].CR2, val) 505 506 507 /** 508 * @brief Destination handshake interface set 509 * @param __DMA__ Specifies DMA peripheral 510 * @param ch DMA channel 511 * @param ifc Destination handshake interface 512 * @return None 513 */ 514 #define __LL_DMA_DstHandshakeIfc_Set(__DMA__, ch, ifc) MODIFY_REG((__DMA__)->CH[(ch)].CR3, DMA_CH_CR3_DHSIF_Msk, ifc) 515 516 /** 517 * @brief Source handshake interface set 518 * @param __DMA__ Specifies DMA peripheral 519 * @param ch DMA channel 520 * @param ifc Source handshake interface 521 * @return None 522 */ 523 #define __LL_DMA_SrcHandshakeIfc_Set(__DMA__, ch, ifc) MODIFY_REG((__DMA__)->CH[(ch)].CR3, DMA_CH_CR3_SHSIF_Msk, ifc) 524 525 /** 526 * @brief FIFO mode half set 527 * @param __DMA__ Specifies DMA peripheral 528 * @param ch DMA channel 529 * @return None 530 */ 531 #define __LL_DMA_FIFOModeHalf_Set(__DMA__, ch) SET_BIT((__DMA__)->CH[(ch)].CR3, DMA_CH_CR3_FMD_Msk) 532 533 /** 534 * @brief FIFO mode once set 535 * @param __DMA__ Specifies DMA peripheral 536 * @param ch DMA channel 537 * @return None 538 */ 539 #define __LL_DMA_FIFOModeOnce_Set(__DMA__, ch) CLEAR_BIT((__DMA__)->CH[(ch)].CR3, DMA_CH_CR3_FMD_Msk) 540 541 /** 542 * @brief Channel folw control mode source request set 543 * @param __DMA__ Specifies DMA peripheral 544 * @param ch DMA channel 545 * @return None 546 */ 547 #define __LL_DMA_ChFlowModeSrcReq_Set(__DMA__, ch) CLEAR_BIT((__DMA__)->CH[(ch)].CR3, DMA_CH_CR3_FCMD_Msk) 548 549 /** 550 * @brief Channel folw control mode destination request set 551 * @param __DMA__ Specifies DMA peripheral 552 * @param ch DMA channel 553 * @return None 554 */ 555 #define __LL_DMA_ChFlowModeDstReq_Set(__DMA__, ch) SET_BIT((__DMA__)->CH[(ch)].CR3, DMA_CH_CR3_FCMD_Msk) 556 557 /** 558 * @brief Channel register CR3 write 559 * @param __DMA__ Specifies DMA peripheral 560 * @param ch DMA channel 561 * @param val write value 562 * @return None 563 */ 564 #define __LL_DAM_ChannelRegCR3_Write(__DMA__, ch, val) WRITE_REG((__DMA__)->CH[(ch)].CR3, val) 565 566 567 /** 568 * @brief Channel 1 transfer complete status get 569 * @param __DMA__ Specifies DMA peripheral 570 * @retval 0 Channel 1 transfer hasn't completed 571 * @retval 1 Channel 1 transfer has completed 572 */ 573 #define __LL_DMA_Ch1TransComSta_Get(__DMA__) (READ_BIT((__DMA__)->TSR, DMA_TSR_TS_CH1_Msk) >> DMA_TSR_TS_CH1_Pos) 574 575 /** 576 * @brief Channel 0 transfer complete status get 577 * @param __DMA__ Specifies DMA peripheral 578 * @retval 0 Channel 0 transfer hasn't completed 579 * @retval 1 Channel 0 transfer has completed 580 */ 581 #define __LL_DMA_Ch0TransComSta_Get(__DMA__) (READ_BIT((__DMA__)->TSR, DMA_TSR_TS_CH0_Msk) >> DMA_TSR_TS_CH0_Pos) 582 583 584 /** 585 * @brief Channel 1 block transfer complete status get 586 * @param __DMA__ Specifies DMA peripheral 587 * @retval 0 Channel 1 block transfer hasn't completed 588 * @retval 1 Channel 1 block transfer has completed 589 */ 590 #define __LL_DMA_Ch1BlockTransComSta_Get(__DMA__) (READ_BIT((__DMA__)->BTSR, DMA_BTSR_BTS_CH1_Msk) >> DMA_BTSR_BTS_CH1_Pos) 591 592 /** 593 * @brief Channel 0 block transfer complete status get 594 * @param __DMA__ Specifies DMA peripheral 595 * @retval 0 Channel 0 block transfer hasn't completed 596 * @retval 1 Channel 0 block transfer has completed 597 */ 598 #define __LL_DMA_Ch0BlockTransComSta_Get(__DMA__) (READ_BIT((__DMA__)->BTSR, DMA_BTSR_BTS_CH0_Msk) >> DMA_BTSR_BTS_CH0_Pos) 599 600 601 /** 602 * @brief Channel 1 source transfer complete status get 603 * @param __DMA__ Specifies DMA peripheral 604 * @retval 0 Channel 1 source transfer hasn't completed 605 * @retval 1 Channel 1 source transfer has completed 606 */ 607 #define __LL_DMA_Ch1SrcTransComSta_Get(__DMA__) (READ_BIT((__DMA__)->STSR, DMA_STSR_STS_CH1_Msk) >> DMA_STSR_STS_CH1_Pos) 608 609 /** 610 * @brief Channel 0 source transfer complete status get 611 * @param __DMA__ Specifies DMA peripheral 612 * @retval 0 Channel 0 source transfer hasn't completed 613 * @retval 1 Channel 0 source transfer has completed 614 */ 615 #define __LL_DMA_Ch0SrcTransComSta_Get(__DMA__) (READ_BIT((__DMA__)->STSR, DMA_STSR_STS_CH0_Msk) >> DMA_STSR_STS_CH0_Pos) 616 617 618 /** 619 * @brief Channel 1 destination transfer complete status get 620 * @param __DMA__ Specifies DMA peripheral 621 * @retval 0 Channel 1 destination transfer hasn't completed 622 * @retval 1 Channel 1 destination transfer has completed 623 */ 624 #define __LL_DMA_Ch1DstTransComSta_Get(__DMA__) (READ_BIT((__DMA__)->DTSR, DMA_DTSR_DTS_CH1_Msk) >> DMA_DTSR_DTS_CH1_Pos) 625 626 /** 627 * @brief Channel 0 destination transfer complete status get 628 * @param __DMA__ Specifies DMA peripheral 629 * @retval 0 Channel 0 destination transfer hasn't completed 630 * @retval 1 Channel 0 destination transfer has completed 631 */ 632 #define __LL_DMA_Ch0DstTransComSta_Get(__DMA__) (READ_BIT((__DMA__)->DTSR, DMA_DTSR_DTS_CH0_Msk) >> DMA_DTSR_DTS_CH0_Pos) 633 634 635 /** 636 * @brief Channel 1 transfer error status get 637 * @param __DMA__ Specifies DMA peripheral 638 * @retval 0 Channel 1 transfer normal 639 * @retval 1 Channel 1 transfer error 640 */ 641 #define __LL_DMA_Ch1TransErrSta_Get(__DMA__) (READ_BIT((__DMA__)->TESR, DMA_TESR_TES_CH1_Msk) >> DMA_TESR_TES_CH1_Pos) 642 643 /** 644 * @brief Channel 0 transfer error status get 645 * @param __DMA__ Specifies DMA peripheral 646 * @retval 0 Channel 0 transfer normal 647 * @retval 1 Channel 0 transfer error 648 */ 649 #define __LL_DMA_Ch0TransErrSta_Get(__DMA__) (READ_BIT((__DMA__)->TESR, DMA_TESR_TES_CH0_Msk) >> DMA_TESR_TES_CH0_Pos) 650 651 652 /** 653 * @brief Channel 1 transfer complete interrupt pending get 654 * @param __DMA__ Specifies DMA peripheral 655 * @retval 0 no pending 656 * @retval 1 pending 657 */ 658 #define __LL_DMA_Ch1TransComIntSta_Get(__DMA__) (READ_BIT((__DMA__)->TIPR, DMA_TIPR_TIP_CH1_Msk) >> DMA_TIPR_TIP_CH1_Pos) 659 660 /** 661 * @brief Channel 0 transfer complete interrupt pending get 662 * @param __DMA__ Specifies DMA peripheral 663 * @retval 0 no pending 664 * @retval 1 pending 665 */ 666 #define __LL_DMA_Ch0TransComIntSta_Get(__DMA__) (READ_BIT((__DMA__)->TIPR, DMA_TIPR_TIP_CH0_Msk) >> DMA_TIPR_TIP_CH0_Pos) 667 668 669 /** 670 * @brief Channel 1 block transfer complete interrupt pending get 671 * @param __DMA__ Specifies DMA peripheral 672 * @retval 0 no pending 673 * @retval 1 pending 674 */ 675 #define __LL_DMA_Ch1BlockTransComIntSta_Get(__DMA__) (READ_BIT((__DMA__)->BTIPR, DMA_BTIPR_BTIF_CH1_Msk) >> DMA_BTIPR_BTIF_CH1_Pos) 676 677 /** 678 * @brief Channel 0 block transfer complete interrupt pending get 679 * @param __DMA__ Specifies DMA peripheral 680 * @retval 0 no pending 681 * @retval 1 pending 682 */ 683 #define __LL_DMA_Ch0BlockTransComIntSta_Get(__DMA__) (READ_BIT((__DMA__)->BTIPR, DMA_BTIPR_BTIF_CH0_Msk) >> DMA_BTIPR_BTIF_CH0_Pos) 684 685 686 /** 687 * @brief Channel 1 source transfer complete interrupt pending get 688 * @param __DMA__ Specifies DMA peripheral 689 * @retval 0 no pending 690 * @retval 1 pending 691 */ 692 #define __LL_DMA_Ch1SrcTransComIntSta_Get(__DMA__) (READ_BIT((__DMA__)->STIPR, DMA_STIPR_STIF_CH1_Msk) >> DMA_STIPR_STIF_CH1_Pos) 693 694 /** 695 * @brief Channel 0 source transfer complete interrupt pending get 696 * @param __DMA__ Specifies DMA peripheral 697 * @retval 0 no pending 698 * @retval 1 pending 699 */ 700 #define __LL_DMA_Ch0SrcTransComIntSta_Get(__DMA__) (READ_BIT((__DMA__)->STIPR, DMA_STIPR_STIF_CH0_Msk) >> DMA_STIPR_STIF_CH0_Pos) 701 702 703 /** 704 * @brief Channel 1 destination transfer complete interrupt pending get 705 * @param __DMA__ Specifies DMA peripheral 706 * @retval 0 no pending 707 * @retval 1 pending 708 */ 709 #define __LL_DMA_Ch1DstTransComIntSta_Get(__DMA__) (READ_BIT((__DMA__)->DTIPR, DMA_DTIPR_DTIF_CH1_Msk) >> DMA_DTIPR_DTIF_CH1_Pos) 710 711 /** 712 * @brief Channel 0 destination transfer complete interrupt pending get 713 * @param __DMA__ Specifies DMA peripheral 714 * @retval 0 no pending 715 * @retval 1 pending 716 */ 717 #define __LL_DMA_Ch0DstTransComIntSta_Get(__DMA__) (READ_BIT((__DMA__)->DTIPR, DMA_DTIPR_DTIF_CH0_Msk) >> DMA_DTIPR_DTIF_CH0_Pos) 718 719 720 /** 721 * @brief Channel 1 transfer error interrupt pending get 722 * @param __DMA__ Specifies DMA peripheral 723 * @retval 0 no pending 724 * @retval 1 pending 725 */ 726 #define __LL_DMA_Ch1TransErrIntSta_Get(__DMA__) (READ_BIT((__DMA__)->TEIPR, DMA_TEIPR_TEIF_CH1_Msk) >> DMA_TEIPR_TEIF_CH1_Pos) 727 728 /** 729 * @brief Channel 0 transfer error interrupt pending get 730 * @param __DMA__ Specifies DMA peripheral 731 * @retval 0 no pending 732 * @retval 1 pending 733 */ 734 #define __LL_DMA_Ch0TransErrIntSta_Get(__DMA__) (READ_BIT((__DMA__)->TEIPR, DMA_TEIPR_TEIF_CH0_Msk) >> DMA_TEIPR_TEIF_CH0_Pos) 735 736 737 /** 738 * @brief Channel 1 transfer complete interrupt enable 739 * @param __DMA__ Specifies DMA peripheral 740 * @return None 741 */ 742 #define __LL_DMA_Ch1TransCom_Int_En(__DMA__) SET_BIT((__DMA__)->TIMR, DMA_TIMR_TIWE_CH1_Msk | DMA_TIMR_TIE_CH1_Msk) 743 744 /** 745 * @brief Channel 1 transfer complete interrupt disable 746 * @param __DMA__ Specifies DMA peripheral 747 * @return None 748 */ 749 #define __LL_DMA_Ch1TransCom_Int_Dis(__DMA__) \ 750 MODIFY_REG((__DMA__)->TIMR, DMA_TIMR_TIWE_CH1_Msk | DMA_TIMR_TIE_CH1_Msk, DMA_TIMR_TIWE_CH1_Msk | (0x0 << DMA_TIMR_TIE_CH1_Pos)) 751 752 /** 753 * @brief Channel 0 transfer complete interrupt enable 754 * @param __DMA__ Specifies DMA peripheral 755 * @return None 756 */ 757 #define __LL_DMA_Ch0TransCom_Int_En(__DMA__) SET_BIT((__DMA__)->TIMR, DMA_TIMR_TIWE_CH0_Msk | DMA_TIMR_TIE_CH0_Msk) 758 759 /** 760 * @brief Channel 0 transfer complete interrupt disable 761 * @param __DMA__ Specifies DMA peripheral 762 * @return None 763 */ 764 #define __LL_DMA_Ch0TransCom_Int_Dis(__DMA__) \ 765 MODIFY_REG((__DMA__)->TIMR, DMA_TIMR_TIWE_CH0_Msk | DMA_TIMR_TIE_CH0_Msk, DMA_TIMR_TIWE_CH0_Msk | (0x0 << DMA_TIMR_TIE_CH0_Pos)) 766 767 /** 768 * @brief Reg TIMR Write 769 * @param __DMA__ Specifies DMA peripheral 770 * @param val write value 771 * @return None 772 */ 773 #define __LL_DMA_RegTIMR_Write(__DMA__, val) WRITE_REG((__DMA__)->TIMR, val) 774 775 776 /** 777 * @brief Channel 1 block transfer complete interrupt enable 778 * @param __DMA__ Specifies DMA peripheral 779 * @return None 780 */ 781 #define __LL_DMA_Ch1BlockTransCom_Int_En(__DMA__) SET_BIT((__DMA__)->BTIMR, DMA_BTIMR_BTIWE_CH1_Msk | DMA_BTIMR_BTIE_CH1_Msk) 782 783 /** 784 * @brief Channel 1 block transfer complete interrupt disable 785 * @param __DMA__ Specifies DMA peripheral 786 * @return None 787 */ 788 #define __LL_DMA_Ch1BlockTransCom_Int_Dis(__DMA__) \ 789 MODIFY_REG((__DMA__)->BTIMR, DMA_BTIMR_BTIWE_CH1_Msk | DMA_BTIMR_BTIE_CH1_Msk, DMA_BTIMR_BTIWE_CH1_Msk | (0x0 << DMA_BTIMR_BTIE_CH1_Pos)) 790 791 /** 792 * @brief Channel 0 block transfer complete interrupt enable 793 * @param __DMA__ Specifies DMA peripheral 794 * @return None 795 */ 796 #define __LL_DMA_Ch0BlockTransCom_Int_En(__DMA__) SET_BIT((__DMA__)->BTIMR, DMA_BTIMR_BTIWE_CH0_Msk | DMA_BTIMR_BTIE_CH0_Msk) 797 798 /** 799 * @brief Channel 0 block transfer complete interrupt disable 800 * @param __DMA__ Specifies DMA peripheral 801 * @return None 802 */ 803 #define __LL_DMA_Ch0BlockTransCom_Int_Dis(__DMA__) \ 804 MODIFY_REG((__DMA__)->BTIMR, DMA_BTIMR_BTIWE_CH0_Msk | DMA_BTIMR_BTIE_CH0_Msk, DMA_BTIMR_BTIWE_CH0_Msk | (0x0 << DMA_BTIMR_BTIE_CH0_Pos)) 805 806 /** 807 * @brief Reg BTIMR Write 808 * @param __DMA__ Specifies DMA peripheral 809 * @param val write value 810 * @return None 811 */ 812 #define __LL_DMA_RegBTIMR_Write(__DMA__, val) WRITE_REG((__DMA__)->BTIMR, val) 813 814 815 /** 816 * @brief Channel 1 source transfer complete interrupt enable 817 * @param __DMA__ Specifies DMA peripheral 818 * @return None 819 */ 820 #define __LL_DMA_Ch1SrcTransCom_Int_En(__DMA__) SET_BIT((__DMA__)->STIMR, DMA_STIMR_STIWE_CH1_Msk | DMA_STIMR_STIE_CH1_Msk) 821 822 /** 823 * @brief Channel 1 source transfer complete interrupt disable 824 * @param __DMA__ Specifies DMA peripheral 825 * @return None 826 */ 827 #define __LL_DMA_Ch1SrcTransCom_Int_Dis(__DMA__) \ 828 MODIFY_REG((__DMA__)->STIMR, DMA_STIMR_STIWE_CH1_Msk | DMA_STIMR_STIE_CH1_Msk, DMA_STIMR_STIWE_CH1_Msk | (0x0 << DMA_STIMR_STIE_CH1_Pos)) 829 830 /** 831 * @brief Channel 0 source transfer complete interrupt enable 832 * @param __DMA__ Specifies DMA peripheral 833 * @return None 834 */ 835 #define __LL_DMA_Ch0SrcTransCom_Int_En(__DMA__) SET_BIT((__DMA__)->STIMR, DMA_STIMR_STIWE_CH0_Msk | DMA_STIMR_STIE_CH0_Msk) 836 837 /** 838 * @brief Channel 0 source transfer complete interrupt disable 839 * @param __DMA__ Specifies DMA peripheral 840 * @return None 841 */ 842 #define __LL_DMA_Ch0SrcTransCom_Int_Dis(__DMA__) \ 843 MODIFY_REG((__DMA__)->STIMR, DMA_STIMR_STIWE_CH0_Msk | DMA_STIMR_STIE_CH0_Msk, DMA_STIMR_STIWE_CH0_Msk | (0x0 << DMA_STIMR_STIE_CH0_Pos)) 844 845 /** 846 * @brief Reg STIMR Write 847 * @param __DMA__ Specifies DMA peripheral 848 * @param val write value 849 * @return None 850 */ 851 #define __LL_DMA_RegSTIMR_Write(__DMA__, val) WRITE_REG((__DMA__)->STIMR, val) 852 853 854 /** 855 * @brief Channel 1 destination transfer complete interrupt enable 856 * @param __DMA__ Specifies DMA peripheral 857 * @return None 858 */ 859 #define __LL_DMA_Ch1DstTransCom_Int_En(__DMA__) SET_BIT((__DMA__)->DTIMR, DMA_DTIMR_DTIWE_CH1_Msk | DMA_DTIMR_DTIE_CH1_Msk) 860 861 /** 862 * @brief Channel 1 destination transfer complete interrupt disable 863 * @param __DMA__ Specifies DMA peripheral 864 * @return None 865 */ 866 #define __LL_DMA_Ch1DstTransCom_Int_Dis(__DMA__) \ 867 MODIFY_REG((__DMA__)->DTIMR, DMA_DTIMR_DTIWE_CH1_Msk | DMA_DTIMR_DTIE_CH1_Msk, DMA_DTIMR_DTIWE_CH1_Msk | (0x0 << DMA_DTIMR_DTIE_CH1_Pos)) 868 869 /** 870 * @brief Channel 0 destination transfer complete interrupt enable 871 * @param __DMA__ Specifies DMA peripheral 872 * @return None 873 */ 874 #define __LL_DMA_Ch0DstTransCom_Int_En(__DMA__) SET_BIT((__DMA__)->DTIMR, DMA_DTIMR_DTIWE_CH0_Msk | DMA_DTIMR_DTIE_CH0_Msk) 875 876 /** 877 * @brief Channel 0 destination transfer complete interrupt disable 878 * @param __DMA__ Specifies DMA peripheral 879 * @return None 880 */ 881 #define __LL_DMA_Ch0DstTransCom_Int_Dis(__DMA__) \ 882 MODIFY_REG((__DMA__)->DTIMR, DMA_DTIMR_DTIWE_CH0_Msk | DMA_DTIMR_DTIE_CH0_Msk, DMA_DTIMR_DTIWE_CH0_Msk | (0x0 << DMA_DTIMR_DTIE_CH0_Pos)) 883 884 /** 885 * @brief Reg DTIMR Write 886 * @param __DMA__ Specifies DMA peripheral 887 * @param val write value 888 * @return None 889 */ 890 #define __LL_DMA_RegDTIMR_Write(__DMA__, val) WRITE_REG((__DMA__)->DTIMR, val) 891 892 893 /** 894 * @brief Channel 1 transfer error interrupt enable 895 * @param __DMA__ Specifies DMA peripheral 896 * @return None 897 */ 898 #define __LL_DMA_Ch1TransErr_Int_En(__DMA__) SET_BIT((__DMA__)->TEIMR, DMA_TEIMR_TEIWE_CH1_Msk | DMA_TEIMR_TEIE_CH1_Msk) 899 900 /** 901 * @brief Channel 1 transfer error interrupt disable 902 * @param __DMA__ Specifies DMA peripheral 903 * @return None 904 */ 905 #define __LL_DMA_Ch1TransErr_Int_Dis(__DMA__) \ 906 MODIFY_REG((__DMA__)->TEIMR, DMA_TEIMR_TEIWE_CH1_Msk | DMA_TEIMR_TEIE_CH1_Msk, DMA_TEIMR_TEIWE_CH1_Msk | (0x0 << DMA_TEIMR_TEIE_CH1_Pos)) 907 908 /** 909 * @brief Channel 0 transfer error interrupt enable 910 * @param __DMA__ Specifies DMA peripheral 911 * @return None 912 */ 913 #define __LL_DMA_Ch0TransErr_Int_En(__DMA__) SET_BIT((__DMA__)->TEIMR, DMA_TEIMR_TEIWE_CH0_Msk | DMA_TEIMR_TEIE_CH0_Msk) 914 915 /** 916 * @brief Channel 0 transfer error interrupt disable 917 * @param __DMA__ Specifies DMA peripheral 918 * @return None 919 */ 920 #define __LL_DMA_Ch0TransErr_Int_Dis(__DMA__) \ 921 MODIFY_REG((__DMA__)->TEIMR, DMA_TEIMR_TEIWE_CH0_Msk | DMA_TEIMR_TEIE_CH0_Msk, DMA_TEIMR_TEIWE_CH0_Msk | (0x0 << DMA_TEIMR_TEIE_CH0_Pos)) 922 923 /** 924 * @brief Reg TEIMR Write 925 * @param __DMA__ Specifies DMA peripheral 926 * @param val write value 927 * @return None 928 */ 929 #define __LL_DMA_RegTEIMR_Write(__DMA__, val) WRITE_REG((__DMA__)->TEIMR, val) 930 931 932 /** 933 * @brief Channel 1 transfer complete status clear 934 * @param __DMA__ Specifies DMA peripheral 935 * @return None 936 */ 937 #define __LL_DMA_Ch1TransComSta_Clr(__DMA__) WRITE_REG((__DMA__)->TCR, DMA_TCR_TC_CH1_Msk) 938 939 /** 940 * @brief Channel 0 transfer complete status clear 941 * @param __DMA__ Specifies DMA peripheral 942 * @return None 943 */ 944 #define __LL_DMA_Ch0TransComSta_Clr(__DMA__) WRITE_REG((__DMA__)->TCR, DMA_TCR_TC_CH0_Msk) 945 946 /** 947 * @brief Reg TCR Write 948 * @param __DMA__ Specifies DMA peripheral 949 * @param val write value 950 * @return None 951 */ 952 #define __LL_DMA_RegTCR_Write(__DMA__, val) WRITE_REG((__DMA__)->TCR, val) 953 954 955 /** 956 * @brief Channel 1 block transfer complete status clear 957 * @param __DMA__ Specifies DMA peripheral 958 * @return None 959 */ 960 #define __LL_DMA_Ch1BlockTransComSta_Clr(__DMA__) WRITE_REG((__DMA__)->BTCR, DMA_BTCR_BTC_CH1_Msk) 961 962 /** 963 * @brief Channel 0 block transfer complete status clear 964 * @param __DMA__ Specifies DMA peripheral 965 * @return None 966 */ 967 #define __LL_DMA_Ch0BlockTransComSta_Clr(__DMA__) WRITE_REG((__DMA__)->BTCR, DMA_BTCR_BTC_CH0_Msk) 968 969 /** 970 * @brief Reg BTCR Write 971 * @param __DMA__ Specifies DMA peripheral 972 * @param val write value 973 * @return None 974 */ 975 #define __LL_DMA_RegBTCR_Write(__DMA__, val) WRITE_REG((__DMA__)->BTCR, val) 976 977 978 /** 979 * @brief Channel 1 source transfer complete status clear 980 * @param __DMA__ Specifies DMA peripheral 981 * @return None 982 */ 983 #define __LL_DMA_Ch1SrcTransComSta_Clr(__DMA__) WRITE_REG((__DMA__)->STCR, DMA_STCR_STC_CH1_Msk) 984 985 /** 986 * @brief Channel 0 source transfer complete status clear 987 * @param __DMA__ Specifies DMA peripheral 988 * @return None 989 */ 990 #define __LL_DMA_Ch0SrcTransComSta_Clr(__DMA__) WRITE_REG((__DMA__)->STCR, DMA_STCR_STC_CH0_Msk) 991 992 /** 993 * @brief Reg STCR Write 994 * @param __DMA__ Specifies DMA peripheral 995 * @param val write value 996 * @return None 997 */ 998 #define __LL_DMA_RegSTCR_Write(__DMA__, val) WRITE_REG((__DMA__)->STCR, val) 999 1000 1001 /** 1002 * @brief Channel 1 destination transfer complete status clear 1003 * @param __DMA__ Specifies DMA peripheral 1004 * @return None 1005 */ 1006 #define __LL_DMA_Ch1DstTransComSta_Clr(__DMA__) WRITE_REG((__DMA__)->DTCR, DMA_DTCR_DTC_CH1_Msk) 1007 1008 /** 1009 * @brief Channel 0 destination transfer complete status clear 1010 * @param __DMA__ Specifies DMA peripheral 1011 * @return None 1012 */ 1013 #define __LL_DMA_Ch0DstTransComSta_Clr(__DMA__) WRITE_REG((__DMA__)->DTCR, DMA_DTCR_DTC_CH0_Msk) 1014 1015 /** 1016 * @brief Reg DTCR Write 1017 * @param __DMA__ Specifies DMA peripheral 1018 * @param val write value 1019 * @return None 1020 */ 1021 #define __LL_DMA_RegDTCR_Write(__DMA__, val) WRITE_REG((__DMA__)->DTCR, val) 1022 1023 1024 /** 1025 * @brief Channel 1 transfer error status clear 1026 * @param __DMA__ Specifies DMA peripheral 1027 * @return None 1028 */ 1029 #define __LL_DMA_Ch1TransErrSta_Clr(__DMA__) WRITE_REG((__DMA__)->TECR, DMA_TECR_TEC_CH1_Msk) 1030 1031 /** 1032 * @brief Channel 0 transfer error status clear 1033 * @param __DMA__ Specifies DMA peripheral 1034 * @return None 1035 */ 1036 #define __LL_DMA_Ch0TransErrSta_Clr(__DMA__) WRITE_REG((__DMA__)->TECR, DMA_TECR_TEC_CH0_Msk) 1037 1038 /** 1039 * @brief Reg TECR Write 1040 * @param __DMA__ Specifies DMA peripheral 1041 * @param val write value 1042 * @return None 1043 */ 1044 #define __LL_DMA_RegTECR_Write(__DMA__, val) WRITE_REG((__DMA__)->TECR, val) 1045 1046 1047 /** 1048 * @brief Peripheral enable 1049 * @param __DMA__ Specifies DMA peripheral 1050 * @return None 1051 */ 1052 #define __LL_DMA_Periph_En(__DMA__) SET_BIT((__DMA__)->CR0, DMA_CR0_PEN_Msk) 1053 1054 /** 1055 * @brief Peripheral disable 1056 * @param __DMA__ Specifies DMA peripheral 1057 * @return None 1058 */ 1059 #define __LL_DMA_Periph_Dis(__DMA__) CLEAR_BIT((__DMA__)->CR0, DMA_CR0_PEN_Msk) 1060 1061 /** 1062 * @brief Reg CR0 Write 1063 * @param __DMA__ Specifies DMA peripheral 1064 * @param val write value 1065 * @return None 1066 */ 1067 #define __LL_DMA_RegCR0_Write(__DMA__, val) WRITE_REG((__DMA__)->CR0, val) 1068 1069 1070 /** 1071 * @brief Channel 1 enable 1072 * @param __DMA__ Specifies DMA peripheral 1073 * @return None 1074 */ 1075 #define __LL_DMA_Ch1_En(__DMA__) SET_BIT((__DMA__)->CR1, DMA_CR1_CHWE_CH1_Msk | DMA_CR1_CHEN_CH1_Msk) 1076 1077 /** 1078 * @brief Channel 1 disable 1079 * @param __DMA__ Specifies DMA peripheral 1080 * @return None 1081 */ 1082 #define __LL_DMA_Ch1_Dis(__DMA__) \ 1083 MODIFY_REG((__DMA__)->CR1, DMA_CR1_CHWE_CH1_Msk | DMA_CR1_CHEN_CH1_Msk, DMA_CR1_CHWE_CH1_Msk | (0x0 << DMA_CR1_CHEN_CH1_Pos)) 1084 1085 /** 1086 * @brief Channel 0 enable 1087 * @param __DMA__ Specifies DMA peripheral 1088 * @return None 1089 */ 1090 #define __LL_DMA_Ch0_En(__DMA__) SET_BIT((__DMA__)->CR1, DMA_CR1_CHWE_CH0_Msk | DMA_CR1_CHEN_CH0_Msk) 1091 1092 /** 1093 * @brief Channel 0 disable 1094 * @param __DMA__ Specifies DMA peripheral 1095 * @return None 1096 */ 1097 #define __LL_DMA_Ch0_Dis(__DMA__) \ 1098 MODIFY_REG((__DMA__)->CR1, DMA_CR1_CHWE_CH0_Msk | DMA_CR1_CHEN_CH0_Msk, DMA_CR1_CHWE_CH0_Msk | (0x0 << DMA_CR1_CHEN_CH0_Pos)) 1099 1100 /** 1101 * @brief Reg CR1 Write 1102 * @param __DMA__ Specifies DMA peripheral 1103 * @param val write value 1104 * @return None 1105 */ 1106 #define __LL_DMA_RegCR1_Write(__DMA__, val) WRITE_REG((__DMA__)->CR1, val) 1107 1108 /** 1109 * @} 1110 */ 1111 1112 1113 /* Exported functions --------------------------------------------------------*/ 1114 /** @addtogroup DMA_LL_Exported_Functions 1115 * @{ 1116 */ 1117 1118 /** @addtogroup DMA_LL_Exported_Functions_Group1 1119 * @{ 1120 */ 1121 LL_StatusETypeDef LL_DMA_Init(DMA_TypeDef *Instance, DMA_ChannelETypeDef ch, DMA_UserCfgTypeDef *user_cfg); 1122 LL_StatusETypeDef LL_DMA_DeInit(DMA_TypeDef *Instance, DMA_ChannelETypeDef ch); 1123 /** 1124 * @} 1125 */ 1126 1127 1128 /** @addtogroup DMA_LL_Exported_Functions_Group2 1129 * @{ 1130 */ 1131 DMA_ChannelETypeDef LL_DMA_ChannelRequest(void); 1132 DMA_ChannelETypeDef LL_DMA_ChReqSpecific(DMA_ChannelETypeDef ch); 1133 void LL_DMA_ChannelRelease(DMA_ChannelETypeDef ch); 1134 /** 1135 * @} 1136 */ 1137 1138 1139 /** @addtogroup DMA_LL_Exported_Functions_Group3 1140 * @{ 1141 */ 1142 LL_StatusETypeDef LL_DMA_Start_CPU(DMA_TypeDef *Instance, DMA_ChannelETypeDef ch, 1143 uint32_t src_addr, uint32_t dst_addr, uint32_t data_len); 1144 LL_StatusETypeDef LL_DMA_Start_IT(DMA_TypeDef *Instance, DMA_ChannelETypeDef ch, 1145 uint32_t src_addr, uint32_t dst_addr, uint32_t data_len); 1146 LL_StatusETypeDef LL_DMA_Stop_CPU(DMA_TypeDef *Instance, DMA_ChannelETypeDef ch); 1147 LL_StatusETypeDef LL_DMA_Stop_IT(DMA_TypeDef *Instance, DMA_ChannelETypeDef ch); 1148 LL_StatusETypeDef LL_DMA_WaitComplete_CPU(DMA_TypeDef *Instance, DMA_ChannelETypeDef ch, uint32_t timeout); 1149 /** 1150 * @} 1151 */ 1152 1153 1154 /** @addtogroup DMA_LL_Exported_Functions_Interrupt 1155 * @{ 1156 */ 1157 void LL_DMA_IRQHandler(DMA_TypeDef *Instance); 1158 /** 1159 * @} 1160 */ 1161 1162 1163 /** 1164 * @} 1165 */ 1166 1167 1168 /* Private constants ---------------------------------------------------------*/ 1169 /* Private variables ---------------------------------------------------------*/ 1170 /* Private types -------------------------------------------------------------*/ 1171 /* Private macros ------------------------------------------------------------*/ 1172 /* Private functions ---------------------------------------------------------*/ 1173 1174 1175 /** 1176 * @} 1177 */ 1178 1179 /** 1180 * @} 1181 */ 1182 1183 1184 #ifdef __cplusplus 1185 } 1186 #endif /* __cplusplus */ 1187 1188 1189 #endif /* _TAE32F53XX_LL_DMA_H_ */ 1190 1191 1192 /************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/ 1193 1194