| /bsp/allwinner/libraries/sunxi-hal/hal/source/ccmu/sunxi-ng/ |
| A D | ccu_gate.h | 20 #define SUNXI_CCU_GATE_WITH_FIXED_RATE(_struct, _name, _parent, _reg, \ argument
35 #define SUNXI_CCU_GATE_WITH_PREDIV(_struct, _name, _parent, _reg, \ argument
50 #define SUNXI_CCU_GATE_WITH_KEY(_struct, _name, _parent, _reg, \ argument
65 #define SUNXI_CCU_GATE(_struct, _name, _parent, _reg, _gate, _flags) \ argument
77 #define SUNXI_CCU_GATE_HW(_struct, _name, _parent, _reg, _gate, _flags) \ argument
89 #define SUNXI_CCU_GATE_FW(_struct, _name, _parent, _reg, _gate, _flags) \ argument
105 #define SUNXI_CCU_GATE_HWS(_struct, _name, _parent, _reg, _gate, _flags) \ argument
117 #define SUNXI_CCU_GATE_DATA(_struct, _name, _data, _reg, _gate, _flags) \ argument
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| A D | ccu_mp.h | 33 #define SUNXI_CCU_MP_WITH_MUX_GATE_NO_INDEX(_struct, _name, _parents, _reg, \ argument
53 #define SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(_struct, _name, _parents, _reg, \ argument
74 #define SUNXI_CCU_MP_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ argument
93 #define SUNXI_CCU_MP_WITH_MUX(_struct, _name, _parents, _reg, \ argument
122 #define SUNXI_CCU_MP_MMC_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ argument
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| A D | ccu_div.h | 88 #define SUNXI_CCU_DIV_TABLE_WITH_GATE(_struct, _name, _parent, _reg, \ argument
105 #define SUNXI_CCU_DIV_TABLE(_struct, _name, _parent, _reg, \ argument
112 #define SUNXI_CCU_M_WITH_MUX_TABLE_GATE(_struct, _name, \ argument
131 #define SUNXI_CCU_M_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ argument
140 #define SUNXI_CCU_M_WITH_MUX(_struct, _name, _parents, _reg, \ argument
150 #define SUNXI_CCU_M_WITH_GATE(_struct, _name, _parent, _reg, \ argument
165 #define SUNXI_CCU_M(_struct, _name, _parent, _reg, _mshift, _mwidth, \ argument
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| A D | ccu.h | 625 #define CLK_HW_INIT(_name, _parent, _ops, _flags) \ argument
634 #define CLK_HW_INIT_HW(_name, _parent, _ops, _flags) \ argument
648 #define CLK_HW_INIT_HWS(_name, _parent, _ops, _flags) \ argument
657 #define CLK_HW_INIT_FW_NAME(_name, _parent, _ops, _flags) \ argument
668 #define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags) \ argument
677 #define CLK_HW_INIT_PARENTS_HW(_name, _parents, _ops, _flags) \ argument
686 #define CLK_HW_INIT_PARENTS_DATA(_name, _parents, _ops, _flags) \ argument
695 #define CLK_HW_INIT_NO_PARENT(_name, _ops, _flags) \ argument
704 #define CLK_FIXED_FACTOR(_struct, _name, _parent, \ argument
715 #define CLK_FIXED_FACTOR_HW(_struct, _name, _parent, \ argument
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| A D | ccu_nm.h | 38 #define SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(_struct, _name, _parent, _reg, \ argument
61 #define SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(_struct, _name, _parent, _reg, \ argument
85 #define SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(_struct, _name, _parent, \ argument
111 #define SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(_struct, _name, \ argument
140 #define SUNXI_CCU_NM_WITH_GATE_LOCK(_struct, _name, _parent, _reg, \ argument
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| A D | ccu_mux.h | 59 #define SUNXI_CCU_MUX_WITH_GATE_KEY(_struct, _name, _parents, \ argument
76 #define SUNXI_CCU_MUX_TABLE_WITH_GATE(_struct, _name, _parents, _table, \ argument
91 #define SUNXI_CCU_MUX_WITH_GATE(_struct, _name, _parents, _reg, \ argument
97 #define SUNXI_CCU_MUX(_struct, _name, _parents, _reg, _shift, _width, \ argument
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| A D | ccu_nkm.h | 34 #define SUNXI_CCU_NKM_WITH_MUX_GATE_LOCK(_struct, _name, _parents, _reg, \ argument
56 #define SUNXI_CCU_NKM_WITH_GATE_LOCK(_struct, _name, _parent, _reg, \ argument
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| A D | ccu_phase.h | 20 #define SUNXI_CCU_PHASE(_struct, _name, _parent, _reg, _shift, _width, _flags) \ argument
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| A D | ccu_nk.h | 33 #define SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(_struct, _name, _parent, _reg, \ argument
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| A D | ccu_nkmp.h | 35 #define SUNXI_CCU_NKMP_WITH_GATE_LOCK(_struct, _name, _parent, _reg, \ argument
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| A D | ccu_mult.h | 47 #define SUNXI_CCU_N_WITH_GATE_LOCK(_struct, _name, _parent, _reg, \ argument
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| /bsp/allwinner/libraries/sunxi-hal/hal/source/ccmu/sunxi/ |
| A D | clk.h | 105 #define SUNXI_CLK_FIXED_SRC(_name, _clk, _current_parent, _current_parent_type, _clk_rate, _parent_… argument
120 #define SUNXI_CLK_FIXED_FACTOR(_name, _clk, _current_parent, _current_parent_type, _mult, _div) \ argument
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| A D | clk_periph.h | 71 #define SUNXI_CLK_PERIPH(_name, _clk, _parent_arry) \ argument
87 #define SUNXI_PERIPH_INIT(_name, _clk, _parent_clk, _clk_rate) \ argument
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| A D | clk_factors.h | 96 #define SUNXI_CLK_FACTORS_INIT(_name, _reg, _lock_reg, _lock_bit, _pll_lock_ctrl_reg, _lock_en_bit … argument
109 #define SUNXI_CLK_FACTOR(_name, _clk, _current_parent, _current_parent_type, _clk_rate, _parent_ra… argument
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| /bsp/allwinner/libraries/sunxi-hal/hal/test/ccmu/ |
| A D | test_ccmu.c | 222 #define ccmuapi_test(_func, _id, _name, _result) \ argument
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| /bsp/rockchip/rk3500/driver/clk/ |
| A D | clk-rk3568.h | 69 #define GATE(_id, _name, \ argument
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| A D | clk-rk3588.h | 94 #define GATE(_id, _name, \ argument
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| A D | clk-rk3588.c | 518 #define GATE(_id, _name, \ argument
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| /bsp/allwinner/libraries/sunxi-hal/hal/source/sdmmc/ |
| A D | _core.h | 200 #define _FIXUP_EXT(_name, _manfid, _oemid, _rev_start, _rev_end, \ argument
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