1 //*****************************************************************************
2 //
3 // am_hal_pwrctrl.c
4 //! @file
5 //!
6 //! @brief Functions for enabling and disabling power domains.
7 //!
8 //! @addtogroup pwrctrl2 Power Control
9 //! @ingroup apollo2hal
10 //! @{
11 //
12 //*****************************************************************************
13
14 //*****************************************************************************
15 //
16 // Copyright (c) 2017, Ambiq Micro
17 // All rights reserved.
18 //
19 // Redistribution and use in source and binary forms, with or without
20 // modification, are permitted provided that the following conditions are met:
21 //
22 // 1. Redistributions of source code must retain the above copyright notice,
23 // this list of conditions and the following disclaimer.
24 //
25 // 2. Redistributions in binary form must reproduce the above copyright
26 // notice, this list of conditions and the following disclaimer in the
27 // documentation and/or other materials provided with the distribution.
28 //
29 // 3. Neither the name of the copyright holder nor the names of its
30 // contributors may be used to endorse or promote products derived from this
31 // software without specific prior written permission.
32 //
33 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
34 // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
35 // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
36 // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
37 // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
38 // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
39 // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
40 // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
41 // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
42 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
43 // POSSIBILITY OF SUCH DAMAGE.
44 //
45 // This is part of revision 1.2.11 of the AmbiqSuite Development Package.
46 //
47 //*****************************************************************************
48
49 #include <stdint.h>
50 #include <stdbool.h>
51 #include "am_mcu_apollo.h"
52
53 //*****************************************************************************
54 //
55 // ONE_BIT - true iff value has exactly 1 bit set.
56 //
57 //*****************************************************************************
58 #define ONE_BIT(ui32Value) (ui32Value && !(ui32Value & (ui32Value - 1)))
59
60 //*****************************************************************************
61 //
62 // Determine if this is an Apollo2 revision that requires additional handling
63 // of the BUCK to LDO transition when only the ADC is in use and going to
64 // deepsleep.
65 //
66 //*****************************************************************************
67 static bool
isRev_ADC(void)68 isRev_ADC(void)
69 {
70 return AM_BFM(MCUCTRL, CHIPREV, REVMAJ) == AM_REG_MCUCTRL_CHIPREV_REVMAJ_B ?
71 true : false;
72 }
73
74 //*****************************************************************************
75 //
76 //! @brief Enable power for a peripheral.
77 //!
78 //! @param ui32Peripheral - The peripheral to enable
79 //!
80 //! This function directly enables or disables power for the chosen peripheral.
81 //!
82 //! @note Unpowered peripherals may lose their configuration information. This
83 //! function does not save or restore peripheral configuration registers.
84 //!
85 //! @return None.
86 //
87 //*****************************************************************************
88 void
am_hal_pwrctrl_periph_enable(uint32_t ui32Peripheral)89 am_hal_pwrctrl_periph_enable(uint32_t ui32Peripheral)
90 {
91
92 am_hal_debug_assert_msg(ONE_BIT(ui32Peripheral),
93 "Cannot enable more than one peripheral at a time.");
94
95 //
96 // Begin critical section.
97 //
98 AM_CRITICAL_BEGIN_ASM
99
100 //
101 // Enable power control for the given device.
102 //
103 AM_REG(PWRCTRL, DEVICEEN) |= ui32Peripheral;
104
105 //
106 // End Critical Section.
107 //
108 AM_CRITICAL_END_ASM
109
110 //
111 // Wait for the power to stablize. Using a simple delay loop is more
112 // power efficient than a polling loop.
113 //
114 am_hal_flash_delay(AM_HAL_PWRCTRL_DEVICEEN_DELAYCYCLES / 3);
115
116 //
117 // Quick check to guarantee we're good (should never be more than 1 read).
118 //
119 POLL_PWRSTATUS(ui32Peripheral);
120 }
121
122 //*****************************************************************************
123 //
124 //! @brief Disable power for a peripheral.
125 //!
126 //! @param ui32Peripheral - The peripheral to disable
127 //!
128 //! This function directly disables or disables power for the chosen peripheral.
129 //!
130 //! @note Unpowered peripherals may lose their configuration information. This
131 //! function does not save or restore peripheral configuration registers.
132 //!
133 //! @return None.
134 //
135 //*****************************************************************************
136 void
am_hal_pwrctrl_periph_disable(uint32_t ui32Peripheral)137 am_hal_pwrctrl_periph_disable(uint32_t ui32Peripheral)
138 {
139
140 am_hal_debug_assert_msg(ONE_BIT(ui32Peripheral),
141 "Cannot enable more than one peripheral at a time.");
142
143 //
144 // Begin critical section.
145 //
146 AM_CRITICAL_BEGIN_ASM
147
148 //
149 // Disable power control for the given device.
150 //
151 AM_REG(PWRCTRL, DEVICEEN) &= ~ui32Peripheral;
152
153 //
154 // End critical section.
155 //
156 AM_CRITICAL_END_ASM
157
158 //
159 // Wait for the power to stablize
160 //
161 am_hal_flash_delay(AM_HAL_PWRCTRL_DEVICEDIS_DELAYCYCLES / 3);
162 }
163
164 //*****************************************************************************
165 //
166 //! @brief Enable and disable power for memory devices (SRAM, flash, cache).
167 //!
168 //! @param ui32MemEn - The memory and amount to be enabled.
169 //! Must be one of the following:
170 //! AM_HAL_PWRCTRL_MEMEN_CACHE
171 //! AM_HAL_PWRCTRL_MEMEN_CACHE_DIS
172 //! AM_HAL_PWRCTRL_MEMEN_FLASH512K
173 //! AM_HAL_PWRCTRL_MEMEN_FLASH1M
174 //! AM_HAL_PWRCTRL_MEMEN_SRAM8K
175 //! AM_HAL_PWRCTRL_MEMEN_SRAM16K
176 //! AM_HAL_PWRCTRL_MEMEN_SRAM24K
177 //! AM_HAL_PWRCTRL_MEMEN_SRAM32K
178 //! AM_HAL_PWRCTRL_MEMEN_SRAM64K
179 //! AM_HAL_PWRCTRL_MEMEN_SRAM96K
180 //! AM_HAL_PWRCTRL_MEMEN_SRAM128K
181 //! AM_HAL_PWRCTRL_MEMEN_SRAM160K
182 //! AM_HAL_PWRCTRL_MEMEN_SRAM192K
183 //! AM_HAL_PWRCTRL_MEMEN_SRAM224K
184 //! AM_HAL_PWRCTRL_MEMEN_SRAM256K
185 //! AM_HAL_PWRCTRL_MEMEN_ALL (the default, power-up state)
186 //!
187 //! This function enables/disables power to provide only the given amount of
188 //! the type of memory specified.
189 //!
190 //! Only the type of memory specified is affected. Therefore separate calls
191 //! are required to affect power settings for FLASH, SRAM, or CACHE.
192 //!
193 //! Settings for zero SRAM or FLASH are not provided as device behavior under
194 //! either of those conditions is undefined.
195 //!
196 //! @note Unpowered memory devices may lose their configuration information.
197 //! This function does not save or restore peripheral configuration registers.
198 //!
199 //! @return None.
200 //
201 //*****************************************************************************
202 bool
am_hal_pwrctrl_memory_enable(uint32_t ui32MemEn)203 am_hal_pwrctrl_memory_enable(uint32_t ui32MemEn)
204 {
205 uint32_t ui32MemEnMask, ui32MemDisMask;
206 uint32_t ui32PwrStatEnMask, ui32PwrStatDisMask;
207 int32_t i32TOcnt;
208
209 if ( ui32MemEn == AM_HAL_PWRCTRL_MEMEN_FLASH512K )
210 {
211 ui32MemEnMask = AM_REG_PWRCTRL_MEMEN_FLASH0_EN;
212 ui32MemDisMask = AM_REG_PWRCTRL_MEMEN_FLASH1_EN;
213 ui32PwrStatEnMask = AM_REG_PWRCTRL_PWRONSTATUS_PD_FLAM0_M;
214 ui32PwrStatDisMask = AM_REG_PWRCTRL_PWRONSTATUS_PD_FLAM1_M;
215 }
216 else if ( ui32MemEn == AM_HAL_PWRCTRL_MEMEN_FLASH1M )
217 {
218 ui32MemEnMask = AM_REG_PWRCTRL_MEMEN_FLASH0_EN |
219 AM_REG_PWRCTRL_MEMEN_FLASH1_EN;
220 ui32MemDisMask = 0;
221 ui32PwrStatEnMask = AM_REG_PWRCTRL_PWRONSTATUS_PD_FLAM0_M |
222 AM_REG_PWRCTRL_PWRONSTATUS_PD_FLAM1_M;
223 ui32PwrStatDisMask = 0;
224 }
225 else if ( ui32MemEn == AM_HAL_PWRCTRL_MEMEN_SRAM8K )
226 {
227 ui32MemEnMask = AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM8K;
228 ui32MemDisMask = AM_REG_PWRCTRL_MEMEN_SRAMEN_ALL &
229 ~AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM8K;
230 ui32PwrStatEnMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_8K;
231 ui32PwrStatDisMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_ALL &
232 ~AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_8K;
233 }
234 else if ( ui32MemEn == AM_HAL_PWRCTRL_MEMEN_SRAM16K )
235 {
236 ui32MemEnMask = AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM16K;
237 ui32MemDisMask = AM_REG_PWRCTRL_MEMEN_SRAMEN_ALL &
238 ~AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM16K;
239 ui32PwrStatEnMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_16K;
240 ui32PwrStatDisMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_ALL &
241 ~AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_16K;
242 }
243 else if ( ui32MemEn == AM_HAL_PWRCTRL_MEMEN_SRAM24K )
244 {
245 ui32MemEnMask = AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP0_SRAM0 |
246 AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP0_SRAM1 |
247 AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP0_SRAM2;
248 ui32MemDisMask = AM_REG_PWRCTRL_MEMEN_SRAMEN_ALL &
249 ~(AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP0_SRAM0 |
250 AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP0_SRAM1 |
251 AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP0_SRAM2);
252 ui32PwrStatEnMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_24K;
253 ui32PwrStatDisMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_ALL &
254 ~AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_24K;
255 }
256 else if ( ui32MemEn == AM_HAL_PWRCTRL_MEMEN_SRAM32K )
257 {
258 ui32MemEnMask = AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM32K;
259 ui32MemDisMask = AM_REG_PWRCTRL_MEMEN_SRAMEN_ALL &
260 ~AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM32K;
261 ui32PwrStatEnMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_32K;
262 ui32PwrStatDisMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_ALL &
263 ~AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_32K;
264 }
265 else if ( ui32MemEn == AM_HAL_PWRCTRL_MEMEN_SRAM64K )
266 {
267 ui32MemEnMask = AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM64K;
268 ui32MemDisMask = AM_REG_PWRCTRL_MEMEN_SRAMEN_ALL &
269 ~AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM64K;
270 ui32PwrStatEnMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_64K;
271 ui32PwrStatDisMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_ALL &
272 ~AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_64K;
273 }
274 else if ( ui32MemEn == AM_HAL_PWRCTRL_MEMEN_SRAM96K )
275 {
276 ui32MemEnMask = AM_HAL_PWRCTRL_MEMEN_SRAM96K;
277 ui32MemDisMask = AM_REG_PWRCTRL_MEMEN_SRAMEN_ALL &
278 ~AM_HAL_PWRCTRL_MEMEN_SRAM96K;
279 ui32PwrStatEnMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_96K;
280 ui32PwrStatDisMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_ALL &
281 ~AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_96K;
282 }
283 else if ( ui32MemEn == AM_HAL_PWRCTRL_MEMEN_SRAM128K )
284 {
285 ui32MemEnMask = AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM128K;
286 ui32MemDisMask = AM_REG_PWRCTRL_MEMEN_SRAMEN_ALL &
287 ~AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM128K;
288 ui32PwrStatEnMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_128K;
289 ui32PwrStatDisMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_ALL &
290 ~AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_128K;
291 }
292 else if ( ui32MemEn == AM_HAL_PWRCTRL_MEMEN_SRAM160K )
293 {
294 ui32MemEnMask = AM_HAL_PWRCTRL_MEMEN_SRAM160K;
295 ui32MemDisMask = AM_REG_PWRCTRL_MEMEN_SRAMEN_ALL &
296 ~AM_HAL_PWRCTRL_MEMEN_SRAM160K;
297 ui32PwrStatEnMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_160K;
298 ui32PwrStatDisMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_ALL &
299 ~AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_160K;
300 }
301 else if ( ui32MemEn == AM_HAL_PWRCTRL_MEMEN_SRAM192K )
302 {
303 ui32MemEnMask = AM_HAL_PWRCTRL_MEMEN_SRAM192K;
304 ui32MemDisMask = AM_REG_PWRCTRL_MEMEN_SRAMEN_ALL &
305 ~AM_HAL_PWRCTRL_MEMEN_SRAM192K;
306 ui32PwrStatEnMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_192K;
307 ui32PwrStatDisMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_ALL &
308 ~AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_192K;
309 }
310 else if ( ui32MemEn == AM_HAL_PWRCTRL_MEMEN_SRAM224K )
311 {
312 ui32MemEnMask = AM_HAL_PWRCTRL_MEMEN_SRAM224K;
313 ui32MemDisMask = AM_REG_PWRCTRL_MEMEN_SRAMEN_ALL &
314 ~AM_HAL_PWRCTRL_MEMEN_SRAM224K;
315 ui32PwrStatEnMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_224K;
316 ui32PwrStatDisMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_ALL &
317 ~AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_224K;
318 }
319 else if ( ui32MemEn == AM_HAL_PWRCTRL_MEMEN_SRAM256K )
320 {
321 ui32MemEnMask = AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM256K;
322 ui32MemDisMask = AM_REG_PWRCTRL_MEMEN_SRAMEN_ALL &
323 ~AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM256K;
324 ui32PwrStatEnMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_256K;
325 ui32PwrStatDisMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_ALL &
326 ~AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_256K;
327 }
328 else if ( ui32MemEn == AM_HAL_PWRCTRL_MEMEN_CACHE )
329 {
330 ui32MemEnMask = AM_REG_PWRCTRL_MEMEN_CACHEB0_EN |
331 AM_REG_PWRCTRL_MEMEN_CACHEB2_EN;
332 ui32MemDisMask = 0;
333 ui32PwrStatEnMask = AM_REG_PWRCTRL_PWRONSTATUS_PD_CACHEB2_M |
334 AM_REG_PWRCTRL_PWRONSTATUS_PD_CACHEB0_M;
335 ui32PwrStatDisMask = 0;
336 }
337 else if ( ui32MemEn == AM_HAL_PWRCTRL_MEMEN_CACHE_DIS )
338 {
339 ui32MemEnMask = 0;
340 ui32MemDisMask = AM_REG_PWRCTRL_MEMEN_CACHEB0_EN |
341 AM_REG_PWRCTRL_MEMEN_CACHEB2_EN;
342 ui32PwrStatEnMask = 0;
343 ui32PwrStatDisMask = AM_REG_PWRCTRL_PWRONSTATUS_PD_CACHEB2_M |
344 AM_REG_PWRCTRL_PWRONSTATUS_PD_CACHEB0_M;
345 }
346 else if ( ui32MemEn == AM_HAL_PWRCTRL_MEMEN_ALL )
347 {
348 ui32MemEnMask = AM_HAL_PWRCTRL_MEMEN_ALL;
349 ui32MemDisMask = 0;
350 ui32PwrStatEnMask = AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_ALL;
351 ui32PwrStatDisMask = 0;
352 }
353 else
354 {
355 return false;
356 }
357
358 //
359 // Disable unneeded memory. If nothing to be disabled, skip to save time.
360 //
361 // Note that a deliberate disable step using a disable mask is taken here
362 // for 2 reasons: 1) To only affect the specified type of memory, and 2)
363 // To avoid inadvertently disabling any memory currently being depended on.
364 //
365 if ( ui32MemDisMask != 0 )
366 {
367 AM_REG(PWRCTRL, MEMEN) &= ~ui32MemDisMask;
368 }
369
370 //
371 // Enable the required memory.
372 //
373 if ( ui32MemEnMask != 0 )
374 {
375 AM_REG(PWRCTRL, MEMEN) |= ui32MemEnMask;
376 }
377
378 //
379 // Wait for the power to be turned on.
380 // Apollo2 note - these loops typically end up taking 1 iteration.
381 //
382 i32TOcnt = 200;
383 if ( ui32PwrStatDisMask )
384 {
385 while ( --i32TOcnt &&
386 ( AM_REG(PWRCTRL, PWRONSTATUS) & ui32PwrStatDisMask ) );
387 }
388
389 if ( i32TOcnt <= 0 )
390 {
391 return false;
392 }
393
394 i32TOcnt = 200;
395 if ( ui32PwrStatEnMask )
396 {
397 while ( --i32TOcnt &&
398 (( AM_REG(PWRCTRL, PWRONSTATUS) & ui32PwrStatEnMask )
399 != ui32PwrStatEnMask) );
400 }
401 if ( i32TOcnt <= 0 )
402 {
403 return false;
404 }
405
406 return true;
407 }
408
409 //*****************************************************************************
410 //
411 //! @brief Initialize the core and memory buck converters.
412 //!
413 //! This function is intended to be used for first time core and memory buck
414 //! converters initialization.
415 //!
416 //! @return None
417 //
418 //*****************************************************************************
419 void
am_hal_pwrctrl_bucks_init(void)420 am_hal_pwrctrl_bucks_init(void)
421 {
422 am_hal_pwrctrl_bucks_enable();
423
424 while ( ( AM_REG(PWRCTRL, POWERSTATUS) &
425 ( AM_REG_PWRCTRL_POWERSTATUS_COREBUCKON_M |
426 AM_REG_PWRCTRL_POWERSTATUS_MEMBUCKON_M ) ) !=
427 ( AM_REG_PWRCTRL_POWERSTATUS_COREBUCKON_M |
428 AM_REG_PWRCTRL_POWERSTATUS_MEMBUCKON_M ) );
429
430 //
431 // Additional delay to make sure BUCKs are initialized.
432 //
433 am_hal_flash_delay(200 / 3);
434 }
435
436 //*****************************************************************************
437 //
438 //! @brief Enable the core and memory buck converters.
439 //!
440 //! This function enables the core and memory buck converters.
441 //!
442 //! @return None
443 //
444 //*****************************************************************************
445 #define LDO_TRIM_REG_ADDR (0x50023004)
446 #define BUCK_TRIM_REG_ADDR (0x50023000)
447
448 void
am_hal_pwrctrl_bucks_enable(void)449 am_hal_pwrctrl_bucks_enable(void)
450 {
451 //
452 // Check to see if the bucks are already on. If so, we can just return.
453 //
454 if ( AM_BFR(PWRCTRL, POWERSTATUS, COREBUCKON) &&
455 AM_BFR(PWRCTRL, POWERSTATUS, MEMBUCKON) )
456 {
457 return;
458 }
459
460 //
461 // Enable BUCK power up
462 //
463 AM_BFW(PWRCTRL, SUPPLYSRC, COREBUCKEN, 1);
464 AM_BFW(PWRCTRL, SUPPLYSRC, MEMBUCKEN, 1);
465
466 //
467 // Make sure bucks are ready.
468 //
469 while ( ( AM_REG(PWRCTRL, POWERSTATUS) &
470 ( AM_REG_PWRCTRL_POWERSTATUS_COREBUCKON_M |
471 AM_REG_PWRCTRL_POWERSTATUS_MEMBUCKON_M ) ) !=
472 ( AM_REG_PWRCTRL_POWERSTATUS_COREBUCKON_M |
473 AM_REG_PWRCTRL_POWERSTATUS_MEMBUCKON_M ) );
474 }
475
476 //*****************************************************************************
477 //
478 //! @brief Disable the core and memory buck converters.
479 //!
480 //! This function disables the core and memory buck converters.
481 //!
482 //! @return None
483 //
484 //*****************************************************************************
485 void
am_hal_pwrctrl_bucks_disable(void)486 am_hal_pwrctrl_bucks_disable(void)
487 {
488 //
489 // Check to see if the bucks are already off. If so, we can just return.
490 //
491 if ( AM_BFR(PWRCTRL, POWERSTATUS, COREBUCKON) == 0 &&
492 AM_BFR(PWRCTRL, POWERSTATUS, MEMBUCKON) == 0)
493 {
494 return;
495 }
496
497 //
498 // Handle the special case if only the ADC is powered.
499 //
500 if ( isRev_ADC() &&
501 (AM_REG(PWRCTRL, DEVICEEN) == AM_REG_PWRCTRL_DEVICEEN_ADC_EN) )
502 {
503 //
504 // Set SUPPLYSRC to handle this case
505 //
506 AM_REG(PWRCTRL, SUPPLYSRC) &=
507 (AM_REG_PWRCTRL_SUPPLYSRC_SWITCH_LDO_IN_SLEEP_EN |
508 AM_REG_PWRCTRL_SUPPLYSRC_MEMBUCKEN_EN);
509 }
510 else
511 {
512 //
513 // Power them down
514 //
515 AM_BFW(PWRCTRL, SUPPLYSRC, COREBUCKEN, 0);
516 AM_BFW(PWRCTRL, SUPPLYSRC, MEMBUCKEN, 0);
517 }
518
519 //
520 // Wait until BUCKs are disabled.
521 //
522 am_hal_flash_delay(AM_HAL_PWRCTRL_BUCKDIS_DELAYCYCLES / 3);
523 }
524
525 //*****************************************************************************
526 //
527 //! @brief Misc low power initializations.
528 //!
529 //! This function performs low power initializations that aren't specifically
530 //! handled elsewhere.
531 //!
532 //! @return None
533 //
534 //*****************************************************************************
535 void
am_hal_pwrctrl_low_power_init(void)536 am_hal_pwrctrl_low_power_init(void)
537 {
538 //
539 // For lowest power, we enable clock gating for all SRAM configuration.
540 //
541 AM_REG(PWRCTRL, SRAMCTRL) |=
542 AM_REG_PWRCTRL_SRAMCTRL_SRAM_MASTER_CLKGATE_EN |
543 AM_REG_PWRCTRL_SRAMCTRL_SRAM_CLKGATE_EN |
544 AM_REG_PWRCTRL_SRAMCTRL_SRAM_LIGHT_SLEEP_DIS;
545
546 //
547 // For lowest deep sleep power, make sure we stay in BUCK mode.
548 //
549 AM_REG(PWRCTRL, SUPPLYSRC) &=
550 ~AM_REG_PWRCTRL_SUPPLYSRC_SWITCH_LDO_IN_SLEEP_M;
551 }
552
553 //*****************************************************************************
554 //
555 // End Doxygen group.
556 //! @}
557 //
558 //*****************************************************************************
559