1 /* 2 * Copyright (C) 2019 ETH Zurich, University of Bologna 3 * and GreenWaves Technologies 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 */ 17 18 #ifndef HAL_INCLUDE_HAL_PWM_PERIPH_H_ 19 #define HAL_INCLUDE_HAL_PWM_PERIPH_H_ 20 21 /* ---------------------------------------------------------------------------- 22 -- PWM Peripheral Access Layer -- 23 ---------------------------------------------------------------------------- */ 24 25 /** PWM_Type Register Layout Typedef */ 26 typedef struct 27 { 28 volatile uint32_t cmd; /**< ADV_TIMER0 command register. */ 29 volatile uint32_t config; /**< ADV_TIMER0 configuration register. */ 30 volatile uint32_t threshold; /**< ADV_TIMER0 threshold configuration register. */ 31 volatile uint32_t ch_threshold[4]; /**< ADV_TIMER0 channel threshold configuration register. */ 32 volatile uint32_t ch_lut[4]; /**< ADV_TIMER0 channel LUT configuration register. */ 33 volatile uint32_t counter; /**< ADV_TIMER0 counter register. */ 34 } pwm_t; 35 36 /* ---------------------------------------------------------------------------- 37 -- PWM Register Bitfield Access -- 38 ---------------------------------------------------------------------------- */ 39 40 /*! @name CMD */ 41 /* ADV_TIMER0 start command bitfield. */ 42 #define PWM_CMD_START_MASK (0x1) 43 #define PWM_CMD_START_SHIFT (0) 44 #define PWM_CMD_START(val) (((uint32_t)(((uint32_t)(val)) << PWM_CMD_START_SHIFT)) & PWM_CMD_START_MASK) 45 46 /* ADV_TIMER0 stop command bitfield. */ 47 #define PWM_CMD_STOP_MASK (0x2) 48 #define PWM_CMD_STOP_SHIFT (1) 49 #define PWM_CMD_STOP(val) (((uint32_t)(((uint32_t)(val)) << PWM_CMD_STOP_SHIFT)) & PWM_CMD_STOP_MASK) 50 51 /* ADV_TIMER0 update command bitfield. */ 52 #define PWM_CMD_UPDATE_MASK (0x4) 53 #define PWM_CMD_UPDATE_SHIFT (2) 54 #define PWM_CMD_UPDATE(val) (((uint32_t)(((uint32_t)(val)) << PWM_CMD_UPDATE_SHIFT)) & PWM_CMD_UPDATE_MASK) 55 56 /* ADV_TIMER0 reset command bitfield. */ 57 #define PWM_CMD_RESET_MASK (0x8) 58 #define PWM_CMD_RESET_SHIFT (3) 59 #define PWM_CMD_RESET(val) (((uint32_t)(((uint32_t)(val)) << PWM_CMD_RESET_SHIFT)) & PWM_CMD_RESET_MASK) 60 61 /* ADV_TIMER0 arm command bitfield. */ 62 #define PWM_CMD_ARM_MASK (0x10) 63 #define PWM_CMD_ARM_SHIFT (4) 64 #define PWM_CMD_ARM(val) (((uint32_t)(((uint32_t)(val)) << PWM_CMD_ARM_SHIFT)) & PWM_CMD_ARM_MASK) 65 66 67 /*! @name CONFIG */ 68 /* ADV_TIMER0 input source configuration bitfield: 69 - 0-31: GPIO[0] to GPIO[31] 70 - 32-35: Channel 0 to 3 of ADV_TIMER0 71 - 36-39: Channel 0 to 3 of ADV_TIMER1 72 - 40-43: Channel 0 to 3 of ADV_TIMER2 73 - 44-47: Channel 0 to 3 of ADV_TIMER3 */ 74 #define PWM_CONFIG_INSEL_MASK (0xff) 75 #define PWM_CONFIG_INSEL_SHIFT (0) 76 #define PWM_CONFIG_INSEL(val) (((uint32_t)(((uint32_t)(val)) << PWM_CONFIG_INSEL_SHIFT)) & PWM_CONFIG_INSEL_MASK) 77 78 /* ADV_TIMER0 trigger mode configuration bitfield: 79 - 3'h0: trigger event at each clock cycle. 80 - 3'h1: trigger event if input source is 0 81 - 3'h2: trigger event if input source is 1 82 - 3'h3: trigger event on input source rising edge 83 - 3'h4: trigger event on input source falling edge 84 - 3'h5: trigger event on input source falling or rising edge 85 - 3'h6: trigger event on input source rising edge when armed 86 - 3'h7: trigger event on input source falling edge when armed */ 87 #define PWM_CONFIG_MODE_MASK (0x700) 88 #define PWM_CONFIG_MODE_SHIFT (8) 89 #define PWM_CONFIG_MODE(val) (((uint32_t)(((uint32_t)(val)) << PWM_CONFIG_MODE_SHIFT)) & PWM_CONFIG_MODE_MASK) 90 91 /* ADV_TIMER0 clock source configuration bitfield: 92 - 1'b0: FLL 93 - 1'b1: reference clock at 32kHz */ 94 #define PWM_CONFIG_CLKSEL_MASK (0x800) 95 #define PWM_CONFIG_CLKSEL_SHIFT (11) 96 #define PWM_CONFIG_CLKSEL(val) (((uint32_t)(((uint32_t)(val)) << PWM_CONFIG_CLKSEL_SHIFT)) & PWM_CONFIG_CLKSEL_MASK) 97 98 /* ADV_TIMER0 center-aligned mode configuration bitfield: 99 - 1'b0: The counter counts up and down alternatively. 100 - 1'b1: The counter counts up and resets to 0 when reach threshold. */ 101 #define PWM_CONFIG_UPDOWNSEL_MASK (0x1000) 102 #define PWM_CONFIG_UPDOWNSEL_SHIFT (12) 103 #define PWM_CONFIG_UPDOWNSEL(val) (((uint32_t)(((uint32_t)(val)) << PWM_CONFIG_UPDOWNSEL_SHIFT)) & PWM_CONFIG_UPDOWNSEL_MASK) 104 105 /* ADV_TIMER0 prescaler value configuration bitfield. */ 106 #define PWM_CONFIG_PRESC_MASK (0xff0000) 107 #define PWM_CONFIG_PRESC_SHIFT (16) 108 #define PWM_CONFIG_PRESC(val) (((uint32_t)(((uint32_t)(val)) << PWM_CONFIG_PRESC_SHIFT)) & PWM_CONFIG_PRESC_MASK) 109 110 111 /*! @name THRESHOLD */ 112 /* ADV_TIMER0 threshold low part configuration bitfield. It defines start counter value. */ 113 #define PWM_THRESHOLD_TH_LO_MASK (0xffff) 114 #define PWM_THRESHOLD_TH_LO_SHIFT (0) 115 #define PWM_THRESHOLD_TH_LO(val) (((uint32_t)(((uint32_t)(val)) << PWM_THRESHOLD_TH_LO_SHIFT)) & PWM_THRESHOLD_TH_LO_MASK) 116 117 /* ADV_TIMER0 threshold high part configuration bitfield. It defines end counter value. */ 118 #define PWM_THRESHOLD_TH_HI_MASK (0xffff0000) 119 #define PWM_THRESHOLD_TH_HI_SHIFT (16) 120 #define PWM_THRESHOLD_TH_HI(val) (((uint32_t)(((uint32_t)(val)) << PWM_THRESHOLD_TH_HI_SHIFT)) & PWM_THRESHOLD_TH_HI_MASK) 121 122 123 /*! @name CH_THRESHOLD */ 124 /* ADV_TIMER0 channel 0 threshold configuration bitfield. */ 125 #define PWM_CH_THRESHOLD_TH_MASK (0xffff) 126 #define PWM_CH_THRESHOLD_TH_SHIFT (0) 127 #define PWM_CH_THRESHOLD_TH(val) (((uint32_t)(((uint32_t)(val)) << PWM_CH_THRESHOLD_TH_SHIFT)) & PWM_CH_THRESHOLD_TH_MASK) 128 129 /* ADV_TIMER0 channel 0 threshold match action on channel output signal configuration bitfield: 130 - 3'h0: set. 131 - 3'h1: toggle then next threshold match action is clear. 132 - 3'h2: set then next threshold match action is clear. 133 - 3'h3: toggle. 134 - 3'h4: clear. 135 - 3'h5: toggle then next threshold match action is set. 136 - 3'h6: clear then next threshold match action is set. */ 137 #define PWM_CH_THRESHOLD_MODE_MASK (0x70000) 138 #define PWM_CH_THRESHOLD_MODE_SHIFT (16) 139 #define PWM_CH_THRESHOLD_MODE(val) (((uint32_t)(((uint32_t)(val)) << PWM_CH_THRESHOLD_MODE_SHIFT)) & PWM_CH_THRESHOLD_MODE_MASK) 140 141 142 /*! @name CH_LUT */ 143 144 /*! @name COUNTER */ 145 146 /*! @name CMD */ 147 typedef union 148 { 149 struct 150 { 151 /* ADV_TIMER0 start command bitfield. */ 152 uint32_t start:1; 153 /* ADV_TIMER0 stop command bitfield. */ 154 uint32_t stop:1; 155 /* ADV_TIMER0 update command bitfield. */ 156 uint32_t update:1; 157 /* ADV_TIMER0 reset command bitfield. */ 158 uint32_t reset:1; 159 /* ADV_TIMER0 arm command bitfield. */ 160 uint32_t arm:1; 161 } field; 162 uint32_t word; 163 } pwm_cmd_t; 164 165 /*! @name CONFIG */ 166 typedef union 167 { 168 struct 169 { 170 /* ADV_TIMER0 input source configuration bitfield: 171 - 0-31: GPIO[0] to GPIO[31] 172 - 32-35: Channel 0 to 3 of ADV_TIMER0 173 - 36-39: Channel 0 to 3 of ADV_TIMER1 174 - 40-43: Channel 0 to 3 of ADV_TIMER2 175 - 44-47: Channel 0 to 3 of ADV_TIMER3 */ 176 uint32_t insel:8; 177 /* ADV_TIMER0 trigger mode configuration bitfield: 178 - 3'h0: trigger event at each clock cycle. 179 - 3'h1: trigger event if input source is 0 180 - 3'h2: trigger event if input source is 1 181 - 3'h3: trigger event on input source rising edge 182 - 3'h4: trigger event on input source falling edge 183 - 3'h5: trigger event on input source falling or rising edge 184 - 3'h6: trigger event on input source rising edge when armed 185 - 3'h7: trigger event on input source falling edge when armed */ 186 uint32_t mode:3; 187 /* ADV_TIMER0 clock source configuration bitfield: 188 - 1'b0: FLL 189 - 1'b1: reference clock at 32kHz */ 190 uint32_t clksel:1; 191 /* ADV_TIMER0 center-aligned mode configuration bitfield: 192 - 1'b0: The counter counts up and down alternatively. 193 - 1'b1: The counter counts up and resets to 0 when reach threshold. */ 194 uint32_t updownsel:1; 195 uint32_t reserved_0:3; 196 /* ADV_TIMER0 prescaler value configuration bitfield. */ 197 uint32_t presc:8; 198 } field; 199 uint32_t word; 200 } pwm_config_t; 201 202 /*! @name THRESHOLD */ 203 typedef union 204 { 205 struct 206 { 207 /* ADV_TIMER0 threshold low part configuration bitfield. It defines start counter value. */ 208 uint32_t th_lo:16; 209 /* ADV_TIMER0 threshold high part configuration bitfield. It defines end counter value. */ 210 uint32_t th_hi:16; 211 } field; 212 uint32_t word; 213 } pwm_threshold_t; 214 215 /*! @name CH_THRESHOLD */ 216 typedef union 217 { 218 struct 219 { 220 /* ADV_TIMER0 channel 0 threshold configuration bitfield. */ 221 uint32_t th:16; 222 /* ADV_TIMER0 channel 0 threshold match action on channel output signal configuration bitfield: 223 - 3'h0: set. 224 - 3'h1: toggle then next threshold match action is clear. 225 - 3'h2: set then next threshold match action is clear. 226 - 3'h3: toggle. 227 - 3'h4: clear. 228 - 3'h5: toggle then next threshold match action is set. 229 - 3'h6: clear then next threshold match action is set. */ 230 uint32_t mode:3; 231 } field; 232 uint32_t word; 233 } pwm_ch_threshold_t; 234 235 /*! @name CH_LUT */ 236 typedef union 237 { 238 struct 239 { 240 } field; 241 uint32_t word; 242 } pwm_ch_lut_t; 243 244 /*! @name COUNTER */ 245 typedef union 246 { 247 struct 248 { 249 } field; 250 uint32_t word; 251 } pwm_counter_t; 252 253 254 #endif /* HAL_INCLUDE_HAL_PWM_PERIPH_H_ */ 255