1
2 #if defined(BL616)
3 #include "bl616_memorymap.h"
4 #include "bl616_glb.h"
5 #include "bl616_ef_cfg.h"
6 #elif defined(BL606P)
7 #include "bl606p_memorymap.h"
8 #include "bl606p_glb.h"
9 #elif defined(BL808)
10 #include "bl808_memorymap.h"
11 #include "bl808_glb.h"
12 #elif defined(BL702L)
13 #include "bl702l_glb.h"
14 #include "bl702l_ef_ctrl.h"
15 #elif defined(BL602)
16 #include "bl602_glb.h"
17 #include "bl602_sflash_ext.h"
18 #include "bl602_xip_sflash_ext.h"
19 #include "bl602_sf_cfg_ext.h"
20 #elif defined(BL702)
21 #include "bl702_glb.h"
22 #include "bl702_xip_sflash_ext.h"
23 #include "bl702_sf_cfg_ext.h"
24 #endif
25 #include "bflb_xip_sflash.h"
26 #include "bflb_sf_cfg.h"
27 #include "bflb_flash.h"
28 #include "include/hardware/sf_ctrl_reg.h"
29
30 #if defined(BL616)
31 static uint32_t flash1_size = 4 * 1024 * 1024;
32 static uint32_t flash2_size = 2 * 1024 * 1024;
33 static uint32_t g_jedec_id2 = 0;
34 #endif
35 static uint32_t g_jedec_id = 0;
36 static spi_flash_cfg_type g_flash_cfg = {
37 .reset_c_read_cmd = 0xff,
38 .reset_c_read_cmd_size = 3,
39 .mid = 0xc8,
40
41 .de_burst_wrap_cmd = 0x77,
42 .de_burst_wrap_cmd_dmy_clk = 0x3,
43 .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
44 .de_burst_wrap_data = 0xF0,
45
46 /*reg*/
47 .write_enable_cmd = 0x06,
48 .wr_enable_index = 0x00,
49 .wr_enable_bit = 0x01,
50 .wr_enable_read_reg_len = 0x01,
51
52 .qe_index = 1,
53 .qe_bit = 0x01,
54 .qe_write_reg_len = 0x01,
55 .qe_read_reg_len = 0x1,
56
57 .busy_index = 0,
58 .busy_bit = 0x00,
59 .busy_read_reg_len = 0x1,
60 .release_powerdown = 0xab,
61
62 .read_reg_cmd[0] = 0x05,
63 .read_reg_cmd[1] = 0x35,
64 .write_reg_cmd[0] = 0x01,
65 .write_reg_cmd[1] = 0x31,
66
67 .fast_read_qio_cmd = 0xeb,
68 .fr_qio_dmy_clk = 16 / 8,
69 .c_read_support = 0,
70 .c_read_mode = 0x20,
71
72 .burst_wrap_cmd = 0x77,
73 .burst_wrap_cmd_dmy_clk = 0x3,
74 .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
75 .burst_wrap_data = 0x40,
76 /*erase*/
77 .chip_erase_cmd = 0xc7,
78 .sector_erase_cmd = 0x20,
79 .blk32_erase_cmd = 0x52,
80 .blk64_erase_cmd = 0xd8,
81 /*write*/
82 .page_program_cmd = 0x02,
83 .qpage_program_cmd = 0x32,
84 .qpp_addr_mode = SF_CTRL_ADDR_1_LINE,
85
86 .io_mode = 0x11,
87 .clk_delay = 0,
88 .clk_invert = 0x03,
89
90 .reset_en_cmd = 0x66,
91 .reset_cmd = 0x99,
92 .c_rexit = 0xff,
93 .wr_enable_write_reg_len = 0x00,
94
95 /*id*/
96 .jedec_id_cmd = 0x9f,
97 .jedec_id_cmd_dmy_clk = 0,
98 #if defined(BL702L) || defined(BL702) || defined(BL602)
99 .qpi_jedec_id_cmd = 0x9f,
100 .qpi_jedec_id_cmd_dmy_clk = 0x00,
101 #else
102 .enter_32bits_addr_cmd = 0xb7,
103 .exit_32bits_addr_cmd = 0xe9,
104 #endif
105 .sector_size = 4,
106 .page_size = 256,
107
108 /*read*/
109 .fast_read_cmd = 0x0b,
110 .fr_dmy_clk = 8 / 8,
111 .qpi_fast_read_cmd = 0x0b,
112 .qpi_fr_dmy_clk = 8 / 8,
113 .fast_read_do_cmd = 0x3b,
114 .fr_do_dmy_clk = 8 / 8,
115 .fast_read_dio_cmd = 0xbb,
116 .fr_dio_dmy_clk = 0,
117 .fast_read_qo_cmd = 0x6b,
118 .fr_qo_dmy_clk = 8 / 8,
119
120 .qpi_fast_read_qio_cmd = 0xeb,
121 .qpi_fr_qio_dmy_clk = 16 / 8,
122 .qpi_page_program_cmd = 0x02,
123 .write_vreg_enable_cmd = 0x50,
124
125 /* qpi mode */
126 .enter_qpi = 0x38,
127 .exit_qpi = 0xff,
128
129 /*AC*/
130 .time_e_sector = 300,
131 .time_e_32k = 1200,
132 .time_e_64k = 1200,
133 .time_page_pgm = 5,
134 .time_ce = 33 * 1000,
135 .pd_delay = 20,
136 .qe_data = 0,
137 };
138 #if defined(BL616)
139 static spi_flash_cfg_type g_flash2_cfg = {
140 .reset_c_read_cmd = 0xff,
141 .reset_c_read_cmd_size = 3,
142 .mid = 0xc8,
143
144 .de_burst_wrap_cmd = 0x77,
145 .de_burst_wrap_cmd_dmy_clk = 0x3,
146 .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
147 .de_burst_wrap_data = 0xF0,
148
149 /*reg*/
150 .write_enable_cmd = 0x06,
151 .wr_enable_index = 0x00,
152 .wr_enable_bit = 0x01,
153 .wr_enable_read_reg_len = 0x01,
154
155 .qe_index = 1,
156 .qe_bit = 0x01,
157 .qe_write_reg_len = 0x01,
158 .qe_read_reg_len = 0x1,
159
160 .busy_index = 0,
161 .busy_bit = 0x00,
162 .busy_read_reg_len = 0x1,
163 .release_powerdown = 0xab,
164
165 .read_reg_cmd[0] = 0x05,
166 .read_reg_cmd[1] = 0x35,
167 .write_reg_cmd[0] = 0x01,
168 .write_reg_cmd[1] = 0x31,
169
170 .fast_read_qio_cmd = 0xeb,
171 .fr_qio_dmy_clk = 16 / 8,
172 .c_read_support = 0,
173 .c_read_mode = 0x20,
174
175 .burst_wrap_cmd = 0x77,
176 .burst_wrap_cmd_dmy_clk = 0x3,
177 .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
178 .burst_wrap_data = 0x40,
179 /*erase*/
180 .chip_erase_cmd = 0xc7,
181 .sector_erase_cmd = 0x20,
182 .blk32_erase_cmd = 0x52,
183 .blk64_erase_cmd = 0xd8,
184 /*write*/
185 .page_program_cmd = 0x02,
186 .qpage_program_cmd = 0x32,
187 .qpp_addr_mode = SF_CTRL_ADDR_1_LINE,
188
189 .io_mode = 0x10,
190 .clk_delay = 0,
191 .clk_invert = 0x03,
192
193 .reset_en_cmd = 0x66,
194 .reset_cmd = 0x99,
195 .c_rexit = 0xff,
196 .wr_enable_write_reg_len = 0x00,
197
198 /*id*/
199 .jedec_id_cmd = 0x9f,
200 .jedec_id_cmd_dmy_clk = 0,
201 .enter_32bits_addr_cmd = 0xb7,
202 .exit_32bits_addr_cmd = 0xe9,
203 .sector_size = 4,
204 .page_size = 256,
205
206 /*read*/
207 .fast_read_cmd = 0x0b,
208 .fr_dmy_clk = 8 / 8,
209 .qpi_fast_read_cmd = 0x0b,
210 .qpi_fr_dmy_clk = 8 / 8,
211 .fast_read_do_cmd = 0x3b,
212 .fr_do_dmy_clk = 8 / 8,
213 .fast_read_dio_cmd = 0xbb,
214 .fr_dio_dmy_clk = 0,
215 .fast_read_qo_cmd = 0x6b,
216 .fr_qo_dmy_clk = 8 / 8,
217
218 .qpi_fast_read_qio_cmd = 0xeb,
219 .qpi_fr_qio_dmy_clk = 16 / 8,
220 .qpi_page_program_cmd = 0x02,
221 .write_vreg_enable_cmd = 0x50,
222
223 /* qpi mode */
224 .enter_qpi = 0x38,
225 .exit_qpi = 0xff,
226
227 /*AC*/
228 .time_e_sector = 300,
229 .time_e_32k = 1200,
230 .time_e_64k = 1200,
231 .time_page_pgm = 5,
232 .time_ce = 33 * 1000,
233 .pd_delay = 20,
234 .qe_data = 0,
235 };
236
237 static bflb_efuse_device_info_type deviceInfo;
238 #endif
239
240 #if defined(BL616)
bflb_flash2_get_jedec_id(void)241 uint32_t bflb_flash2_get_jedec_id(void)
242 {
243 uint32_t jid = 0;
244
245 jid = ((g_jedec_id2 & 0xff) << 16) + (g_jedec_id2 & 0xff00) + ((g_jedec_id2 & 0xff0000) >> 16);
246 return jid;
247 }
248 #endif
249
250 #if defined(BL616) || defined(BL606P) || defined(BL808) || defined(BL702L)
flash_get_clock_delay(spi_flash_cfg_type * cfg)251 static int flash_get_clock_delay(spi_flash_cfg_type *cfg)
252 {
253 uint32_t reg_base = 0;
254 uint32_t regval = 0;
255
256 reg_base = BFLB_SF_CTRL_BASE;
257
258 regval = getreg32(reg_base + SF_CTRL_0_OFFSET);
259 /* bit0-3 for clk delay */
260 if (regval & SF_CTRL_SF_IF_READ_DLY_EN) {
261 cfg->clk_delay = ((regval & SF_CTRL_SF_IF_READ_DLY_N_MASK) >> SF_CTRL_SF_IF_READ_DLY_N_SHIFT) + 1;
262 } else {
263 cfg->clk_delay = 0;
264 }
265 cfg->clk_invert = 0;
266 /* bit0 for clk invert */
267 cfg->clk_invert |= (((regval & SF_CTRL_SF_CLK_OUT_INV_SEL) ? 1 : 0) << 0);
268 /* bit1 for rx clk invert */
269 cfg->clk_invert |= (((regval & SF_CTRL_SF_CLK_SF_RX_INV_SEL) ? 1 : 0) << 1);
270
271 regval = getreg32(reg_base + SF_CTRL_SF_IF_IO_DLY_1_OFFSET);
272 /* bit4-6 for do delay */
273 cfg->clk_delay |= (((regval & SF_CTRL_SF_IO_0_DO_DLY_SEL_MASK) >> SF_CTRL_SF_IO_0_DO_DLY_SEL_SHIFT) << 4);
274 /* bit2-4 for di delay */
275 cfg->clk_invert |= (((regval & SF_CTRL_SF_IO_0_DI_DLY_SEL_MASK) >> SF_CTRL_SF_IO_0_DI_DLY_SEL_SHIFT) << 2);
276 /* bit5-7 for oe delay */
277 cfg->clk_invert |= (((regval & SF_CTRL_SF_IO_0_OE_DLY_SEL_MASK) >> SF_CTRL_SF_IO_0_OE_DLY_SEL_SHIFT) << 5);
278
279 return 0;
280 }
281 #endif
282
flash_set_qspi_enable(spi_flash_cfg_type * p_flash_cfg)283 static void ATTR_TCM_SECTION flash_set_qspi_enable(spi_flash_cfg_type *p_flash_cfg)
284 {
285 if ((p_flash_cfg->io_mode & 0x0f) == SF_CTRL_QO_MODE || (p_flash_cfg->io_mode & 0x0f) == SF_CTRL_QIO_MODE) {
286 bflb_sflash_qspi_enable(p_flash_cfg);
287 }
288 }
289
flash_set_l1c_wrap(spi_flash_cfg_type * p_flash_cfg)290 static void ATTR_TCM_SECTION flash_set_l1c_wrap(spi_flash_cfg_type *p_flash_cfg)
291 {
292 if ((p_flash_cfg->io_mode & 0x1f) == SF_CTRL_QIO_MODE) {
293 L1C_Set_Wrap(ENABLE);
294 bflb_sflash_set_burst_wrap(p_flash_cfg);
295 } else {
296 L1C_Set_Wrap(DISABLE);
297 bflb_sflash_disable_burst_wrap(p_flash_cfg);
298 }
299 }
300
301 /**
302 * @brief flash_config_init
303 *
304 * @return int
305 */
flash_config_init(spi_flash_cfg_type * p_flash_cfg,uint8_t * jedec_id)306 static int ATTR_TCM_SECTION flash_config_init(spi_flash_cfg_type *p_flash_cfg, uint8_t *jedec_id)
307 {
308 int ret = -1;
309 uint8_t is_aes_enable = 0;
310 uint32_t jid = 0;
311 uint32_t offset = 0;
312 uintptr_t flag;
313
314 flag = bflb_irq_save();
315 bflb_xip_sflash_opt_enter(&is_aes_enable);
316 bflb_xip_sflash_state_save(p_flash_cfg, &offset, 0, 0);
317 bflb_sflash_get_jedecid(p_flash_cfg, (uint8_t *)&jid);
318 arch_memcpy(jedec_id, (uint8_t *)&jid, 3);
319 jid &= 0xFFFFFF;
320 g_jedec_id = jid;
321 ret = bflb_sf_cfg_get_flash_cfg_need_lock_ext(jid, p_flash_cfg, 0, 0);
322 if (ret == 0) {
323 p_flash_cfg->mid = (jid & 0xff);
324 }
325
326 // p_flash_cfg->io_mode = 0x11;
327 // p_flash_cfg->c_read_support = 0x00;
328
329 /* Set flash controler from p_flash_cfg */
330 #if defined(BL616) || defined(BL606P) || defined(BL808)
331 bflb_flash_set_cmds(p_flash_cfg);
332 #endif
333 flash_set_qspi_enable(p_flash_cfg);
334 flash_set_l1c_wrap(p_flash_cfg);
335 #if defined(BL602)
336 bflb_xip_sflash_state_restore_ext(p_flash_cfg, offset, 0, 0);
337 #else
338 bflb_xip_sflash_state_restore(p_flash_cfg, offset, 0, 0);
339 #endif
340 bflb_xip_sflash_opt_exit(is_aes_enable);
341 bflb_irq_restore(flag);
342
343 return ret;
344 }
345
346 #if defined(BL616)
347 /**
348 * @brief flash2 init
349 *
350 * @return int
351 */
flash2_init(void)352 static int ATTR_TCM_SECTION flash2_init(void)
353 {
354 int stat = -1;
355 uint32_t ret = 0;
356 uint32_t jid = 0;
357
358 struct sf_ctrl_bank2_cfg sf_bank2_cfg;
359 struct sf_ctrl_cmds_cfg cmds_cfg;
360
361 sf_bank2_cfg.sbus2_select = 1;
362 sf_bank2_cfg.bank2_rx_clk_invert_src = 0;
363 sf_bank2_cfg.bank2_rx_clk_invert_sel = 0;
364 sf_bank2_cfg.bank2_delay_src = 0;
365 sf_bank2_cfg.bank2_clk_delay = 1;
366 sf_bank2_cfg.do_delay = 0;
367 sf_bank2_cfg.di_delay = 0;
368 sf_bank2_cfg.oe_delay = 0;
369 sf_bank2_cfg.remap = SF_CTRL_REMAP_4MB;
370 sf_bank2_cfg.remap_lock = 1;
371
372 cmds_cfg.ack_latency = 1;
373 cmds_cfg.cmds_core_en = 1;
374 cmds_cfg.cmds_en = 1;
375 cmds_cfg.cmds_wrap_mode = 1;
376 cmds_cfg.cmds_wrap_len = SF_CTRL_WRAP_LEN_4096;
377
378 if (deviceInfo.memoryInfo == 0) {
379 /* memoryInfo==0, external flash */
380 flash1_size = 64 * 1024 * 1024;
381 flash2_size = 0;
382 } else if (deviceInfo.memoryInfo == 1) {
383 flash1_size = 2 * 1024 * 1024;
384 flash2_size = 0;
385 } else if (deviceInfo.memoryInfo == 2) {
386 flash1_size = 4 * 1024 * 1024;
387 flash2_size = 0;
388 } else if (deviceInfo.memoryInfo == 3) {
389 /* memoryInfo==3, embedded 4MB+2MB flash */
390 flash1_size = 4 * 1024 * 1024;
391 flash2_size = 2 * 1024 * 1024;
392 } else {
393 flash1_size = 8 * 1024 * 1024;
394 flash2_size = 0;
395 }
396
397 if (flash2_size > 0) {
398 bflb_sf_cfg_sbus2_flash_init(SF_IO_EMB_SWAP_IO3IO0_AND_SF2, &sf_bank2_cfg);
399 bflb_sf_ctrl_sbus2_replace(SF_CTRL_PAD2);
400 ret = bflb_sf_cfg_flash_identify_ext(0, SF_IO_EMB_SWAP_IO3IO0_AND_SF2, 0, &g_flash2_cfg, 0, SF_CTRL_FLASH_BANK1);
401 if ((ret & BFLB_FLASH_ID_VALID_FLAG) == 0) {
402 return -1;
403 }
404 g_flash2_cfg.io_mode = 0x11;
405 g_flash2_cfg.c_read_support = 0;
406 g_flash2_cfg.c_read_mode = 0xff;
407 bflb_sflash_get_jedecid(&g_flash2_cfg, (uint8_t *)&jid);
408 jid &= 0xFFFFFF;
409 g_jedec_id2 = jid;
410
411 bflb_sf_ctrl_cmds_set(&cmds_cfg, SF_CTRL_FLASH_BANK1);
412 stat = bflb_sflash_xip_read_enable(&g_flash2_cfg, (g_flash2_cfg.io_mode & 0xf), 0, SF_CTRL_FLASH_BANK1);
413 if (0 != stat) {
414 return -1;
415 }
416 bflb_sf_ctrl_sbus2_revoke_replace();
417 }
418
419 return 0;
420 }
421 #endif
422
423 /**
424 * @brief multi flash adapter
425 *
426 * @return int
427 */
bflb_flash_init(void)428 int ATTR_TCM_SECTION bflb_flash_init(void)
429 {
430 int ret = -1;
431 uint32_t jedec_id = 0;
432 #if defined(BL602) || defined(BL702)
433 uint8_t clk_delay = 1;
434 uint8_t clk_invert = 1;
435 uintptr_t flag;
436 #endif
437
438 #if defined(BL616)
439 bflb_ef_ctrl_get_device_info(&deviceInfo);
440 #endif
441
442 #if defined(BL602) || defined(BL702)
443 flag = bflb_irq_save();
444 #if defined(BL602)
445 bflb_sflash_cache_flush();
446 #else
447 L1C_Cache_Flush();
448 #endif
449 bflb_sf_cfg_get_flash_cfg_need_lock_ext(jedec_id, &g_flash_cfg, 0, 0);
450 #if defined(BL602)
451 bflb_sflash_cache_flush();
452 #else
453 L1C_Cache_Flush();
454 #endif
455 bflb_irq_restore(flag);
456 if (g_flash_cfg.mid != 0xff && g_flash_cfg.mid != 0x00) {
457 return 0;
458 }
459 clk_delay = g_flash_cfg.clk_delay;
460 clk_invert = g_flash_cfg.clk_invert;
461 g_flash_cfg.io_mode &= 0x0f;
462
463 ret = flash_config_init(&g_flash_cfg, (uint8_t *)&jedec_id);
464
465 g_flash_cfg.clk_delay = clk_delay;
466 g_flash_cfg.clk_invert = clk_invert;
467 #else
468 jedec_id = GLB_Get_Flash_Id_Value();
469 if (jedec_id != 0) {
470 ret = bflb_sf_cfg_get_flash_cfg_need_lock_ext(jedec_id, &g_flash_cfg, 0, 0);
471 if (ret == 0) {
472 g_jedec_id = jedec_id;
473 g_flash_cfg.io_mode &= 0x0f;
474 flash_get_clock_delay(&g_flash_cfg);
475 #if defined(BL616)
476 flash2_init();
477 #endif
478 return 0;
479 }
480 }
481
482 g_flash_cfg.io_mode &= 0x0f;
483 ret = flash_config_init(&g_flash_cfg, (uint8_t *)&jedec_id);
484
485 g_flash_cfg.io_mode &= 0x0f;
486 flash_get_clock_delay(&g_flash_cfg);
487 GLB_Set_Flash_Id_Value(g_jedec_id);
488 #endif
489
490 #if defined(BL616)
491 flash2_init();
492 #endif
493
494 return ret;
495 }
496
497 #if defined(BL616) || defined(BL606P) || defined(BL808)
bflb_flash_set_cmds(spi_flash_cfg_type * p_flash_cfg)498 void ATTR_TCM_SECTION bflb_flash_set_cmds(spi_flash_cfg_type *p_flash_cfg)
499 {
500 struct sf_ctrl_cmds_cfg cmds_cfg;
501
502 cmds_cfg.ack_latency = 1;
503 cmds_cfg.cmds_core_en = 1;
504 cmds_cfg.cmds_en = 1;
505 cmds_cfg.cmds_wrap_mode = 1;
506 cmds_cfg.cmds_wrap_len = 9;
507
508 if ((p_flash_cfg->io_mode & 0x1f) == SF_CTRL_QIO_MODE) {
509 cmds_cfg.cmds_wrap_mode = 2;
510 cmds_cfg.cmds_wrap_len = 2;
511 }
512 bflb_sf_ctrl_cmds_set(&cmds_cfg, 0);
513 }
514 #endif
515
bflb_flash_get_jedec_id(void)516 uint32_t bflb_flash_get_jedec_id(void)
517 {
518 uint32_t jid = 0;
519
520 jid = ((g_jedec_id & 0xff) << 16) + (g_jedec_id & 0xff00) + ((g_jedec_id & 0xff0000) >> 16);
521 return jid;
522 }
523
bflb_flash_get_cfg(uint8_t ** cfg_addr,uint32_t * len)524 void bflb_flash_get_cfg(uint8_t **cfg_addr, uint32_t *len)
525 {
526 *cfg_addr = (uint8_t *)&g_flash_cfg;
527 *len = sizeof(spi_flash_cfg_type);
528 }
529
bflb_flash_set_iomode(uint8_t iomode)530 void ATTR_TCM_SECTION bflb_flash_set_iomode(uint8_t iomode)
531 {
532 uintptr_t flag = 0;
533 uint8_t is_aes_enable = 0;
534 uint32_t offset = 0;
535
536 flag = bflb_irq_save();
537 bflb_xip_sflash_opt_enter(&is_aes_enable);
538 bflb_xip_sflash_state_save(&g_flash_cfg, &offset, 0, 0);
539
540 g_flash_cfg.io_mode &= ~0x1f;
541 if (iomode&4) {
542 g_flash_cfg.io_mode |= iomode;
543 } else {
544 g_flash_cfg.io_mode |= 0x10;
545 g_flash_cfg.io_mode |= iomode;
546 }
547
548 #if defined(BL616) || defined(BL606P) || defined(BL808)
549 bflb_flash_set_cmds(&g_flash_cfg);
550 #endif
551 flash_set_qspi_enable(&g_flash_cfg);
552 flash_set_l1c_wrap(&g_flash_cfg);
553 #if defined(BL602)
554 bflb_xip_sflash_state_restore_ext(&g_flash_cfg, offset, 0, 0);
555 #else
556 bflb_xip_sflash_state_restore(&g_flash_cfg, offset, 0, 0);
557 #endif
558 bflb_xip_sflash_opt_exit(is_aes_enable);
559 bflb_irq_restore(flag);
560 }
561
bflb_flash_get_image_offset(void)562 ATTR_TCM_SECTION uint32_t bflb_flash_get_image_offset(void)
563 {
564 return bflb_sf_ctrl_get_flash_image_offset(0, 0);
565 }
566
567 /**
568 * @brief erase flash via sbus
569 *
570 * @param flash absolute startaddr
571 * @param flash absolute endaddr
572 * @return int
573 */
bflb_flash_erase(uint32_t startaddr,uint32_t len)574 int ATTR_TCM_SECTION bflb_flash_erase(uint32_t startaddr, uint32_t len)
575 {
576 int stat = -1;
577 uintptr_t flag;
578
579 #if defined(BL616)
580 if ((startaddr + len) > (flash1_size + flash2_size)) {
581 return -ENOMEM;
582 } else if ((startaddr + len) <= flash1_size) {
583 flag = bflb_irq_save();
584 stat = bflb_xip_sflash_erase_need_lock(&g_flash_cfg, startaddr, len, 0, 0);
585 bflb_irq_restore(flag);
586 } else if (startaddr >= flash1_size) {
587 bflb_sf_ctrl_sbus2_replace(SF_CTRL_PAD2);
588 stat = bflb_sflash_erase(&g_flash2_cfg, startaddr, startaddr + len - 1);
589 bflb_sf_ctrl_sbus2_revoke_replace();
590 } else {
591 flag = bflb_irq_save();
592 stat = bflb_xip_sflash_erase_need_lock(&g_flash_cfg, startaddr, flash1_size - startaddr, 0, 0);
593 bflb_irq_restore(flag);
594 if (stat != 0) {
595 return stat;
596 }
597 bflb_sf_ctrl_sbus2_replace(SF_CTRL_PAD2);
598 stat = bflb_sflash_erase(&g_flash2_cfg, flash1_size, startaddr + len - flash1_size - 1);
599 bflb_sf_ctrl_sbus2_revoke_replace();
600 }
601 #else
602 if (startaddr >= BFLB_FLASH_XIP_END - BFLB_FLASH_XIP_BASE) {
603 return -ENOMEM;
604 }
605
606 flag = bflb_irq_save();
607 #if defined(BL602)
608 stat = bflb_xip_sflash_erase_need_lock_ext(&g_flash_cfg, startaddr, startaddr+len-1, 0, 0);
609 #elif defined(BL702)
610 uint8_t aes_enabled = 0;
611 bflb_xip_sflash_opt_enter(&aes_enabled);
612 stat = bflb_xip_sflash_erase_need_lock(&g_flash_cfg, startaddr, len, 0, 0);
613 bflb_xip_sflash_opt_exit(aes_enabled);
614 #else
615 stat = bflb_xip_sflash_erase_need_lock(&g_flash_cfg, startaddr, len, 0, 0);
616 #endif
617 bflb_irq_restore(flag);
618 #endif
619
620 return stat;
621 }
622
623 /**
624 * @brief write flash data via sbus
625 *
626 * @param flash absolute addr
627 * @param data
628 * @param len
629 * @return int
630 */
bflb_flash_write(uint32_t addr,uint8_t * data,uint32_t len)631 int ATTR_TCM_SECTION bflb_flash_write(uint32_t addr, uint8_t *data, uint32_t len)
632 {
633 int stat = -1;
634 uintptr_t flag;
635
636 #if defined(BL616)
637 if ((addr + len) > (flash1_size + flash2_size)) {
638 return -ENOMEM;
639 } else if ((addr + len) <= flash1_size) {
640 flag = bflb_irq_save();
641 stat = bflb_xip_sflash_write_need_lock(&g_flash_cfg, addr, data, len, 0, 0);
642 bflb_irq_restore(flag);
643 } else if (addr >= flash1_size) {
644 bflb_sf_ctrl_sbus2_replace(SF_CTRL_PAD2);
645 stat = bflb_sflash_program(&g_flash2_cfg, SF_CTRL_DO_MODE, addr, data, len);
646 bflb_sf_ctrl_sbus2_revoke_replace();
647 } else {
648 flag = bflb_irq_save();
649 stat = bflb_xip_sflash_write_need_lock(&g_flash_cfg, addr, data, flash1_size - addr, 0, 0);
650 bflb_irq_restore(flag);
651 if (stat != 0) {
652 return stat;
653 }
654 bflb_sf_ctrl_sbus2_replace(SF_CTRL_PAD2);
655 stat = bflb_sflash_program(&g_flash2_cfg, SF_CTRL_DO_MODE, flash1_size, data + (flash1_size - addr), addr + len - flash1_size);
656 bflb_sf_ctrl_sbus2_revoke_replace();
657 }
658 #else
659 if (addr >= BFLB_FLASH_XIP_END - BFLB_FLASH_XIP_BASE) {
660 return -ENOMEM;
661 }
662
663 flag = bflb_irq_save();
664 #if defined(BL602)
665 stat = bflb_xip_sflash_write_need_lock_ext(&g_flash_cfg, addr, data, len, 0, 0);
666 #elif defined(BL702)
667 uint8_t aes_enabled = 0;
668 bflb_xip_sflash_opt_enter(&aes_enabled);
669 stat = bflb_xip_sflash_write_need_lock(&g_flash_cfg, addr, data, len, 0, 0);
670 bflb_xip_sflash_opt_exit(aes_enabled);
671 #else
672 stat = bflb_xip_sflash_write_need_lock(&g_flash_cfg, addr, data, len, 0, 0);
673 #endif
674 bflb_irq_restore(flag);
675 #endif
676
677 return stat;
678 }
679
680 /**
681 * @brief read flash data via sbus
682 *
683 * @param flash absolute addr
684 * @param data
685 * @param len
686 * @return int
687 */
bflb_flash_read(uint32_t addr,uint8_t * data,uint32_t len)688 int ATTR_TCM_SECTION bflb_flash_read(uint32_t addr, uint8_t *data, uint32_t len)
689 {
690 int stat = -1;
691 uintptr_t flag;
692
693 #if defined(BL616)
694 if ((addr + len) > (flash1_size + flash2_size)) {
695 return -ENOMEM;
696 } else if ((addr + len) <= flash1_size) {
697 flag = bflb_irq_save();
698 stat = bflb_xip_sflash_read_need_lock(&g_flash_cfg, addr, data, len, 0, 0);
699 bflb_irq_restore(flag);
700 } else if (addr >= flash1_size) {
701 bflb_sf_ctrl_sbus2_replace(SF_CTRL_PAD2);
702 stat = bflb_sflash_read(&g_flash2_cfg, SF_CTRL_DO_MODE, 0, addr, data, len);
703 bflb_sf_ctrl_sbus2_revoke_replace();
704 } else {
705 flag = bflb_irq_save();
706 stat = bflb_xip_sflash_read_need_lock(&g_flash_cfg, addr, data, flash1_size - addr, 0, 0);
707 bflb_irq_restore(flag);
708 if (stat != 0) {
709 return stat;
710 }
711 bflb_sf_ctrl_sbus2_replace(SF_CTRL_PAD2);
712 stat = bflb_sflash_read(&g_flash2_cfg, SF_CTRL_DO_MODE, 0, flash1_size, data + (flash1_size - addr), addr + len - flash1_size);
713 bflb_sf_ctrl_sbus2_revoke_replace();
714 }
715 #else
716 if (addr >= BFLB_FLASH_XIP_END - BFLB_FLASH_XIP_BASE) {
717 return -ENOMEM;
718 }
719
720 flag = bflb_irq_save();
721 #if defined(BL602)
722 stat = bflb_xip_sflash_read_need_lock_ext(&g_flash_cfg, addr, data, len, 0, 0);
723 #elif defined(BL702)
724 uint8_t aes_enabled = 0;
725 bflb_xip_sflash_opt_enter(&aes_enabled);
726 stat = bflb_xip_sflash_read_need_lock(&g_flash_cfg, addr, data, len, 0, 0);
727 bflb_xip_sflash_opt_exit(aes_enabled);
728 #else
729 stat = bflb_xip_sflash_read_need_lock(&g_flash_cfg, addr, data, len, 0, 0);
730 #endif
731 bflb_irq_restore(flag);
732 #endif
733
734 return stat;
735 }
736
bflb_flash_set_cache(uint8_t cont_read,uint8_t cache_enable,uint8_t cache_way_disable,uint32_t flash_offset)737 int ATTR_TCM_SECTION bflb_flash_set_cache(uint8_t cont_read, uint8_t cache_enable, uint8_t cache_way_disable, uint32_t flash_offset)
738 {
739 uint8_t is_aes_enable = 0;
740 uint32_t tmp[1];
741 int stat;
742
743 bflb_sf_ctrl_set_owner(SF_CTRL_OWNER_SAHB);
744
745 bflb_xip_sflash_opt_enter(&is_aes_enable);
746 /* To make it simple, exit cont read anyway */
747 bflb_sflash_reset_continue_read(&g_flash_cfg);
748
749 if (g_flash_cfg.c_read_support == 0) {
750 cont_read = 0;
751 }
752
753 if (cont_read == 1) {
754 stat = bflb_sflash_read(&g_flash_cfg, g_flash_cfg.io_mode & 0xf, 1, 0x00000000, (uint8_t *)tmp, sizeof(tmp));
755
756 if (0 != stat) {
757 bflb_xip_sflash_opt_exit(is_aes_enable);
758 return -1;
759 }
760 }
761
762 #if defined(BL602) || defined(BL702)
763 #if defined(BL602)
764 bflb_sflash_cache_enable_set(0xf);
765 #else
766 L1C_Cache_Enable_Set(0xf);
767 #endif
768
769 if (cache_enable) {
770 bflb_sf_ctrl_set_flash_image_offset(flash_offset, 0, 0);
771 bflb_sflash_xip_read_enable(&g_flash_cfg, g_flash_cfg.io_mode & 0xf, cont_read, 0);
772 }
773 #if defined(BL602)
774 bflb_sflash_cache_enable_set(cache_way_disable);
775 #else
776 L1C_Cache_Enable_Set(cache_way_disable);
777 #endif
778 #else
779 bflb_sf_ctrl_set_flash_image_offset(flash_offset, 0, 0);
780 bflb_sflash_xip_read_enable(&g_flash_cfg, g_flash_cfg.io_mode & 0xf, cont_read, 0);
781 #endif
782
783 bflb_xip_sflash_opt_exit(is_aes_enable);
784
785 return 0;
786 }
787
bflb_flash_aes_init(struct bflb_flash_aes_config_s * config)788 void bflb_flash_aes_init(struct bflb_flash_aes_config_s *config)
789 {
790 uint8_t hw_key_enable = 0;
791
792 if (config->key == NULL) {
793 hw_key_enable = 1;
794 }
795
796 bflb_sf_ctrl_aes_set_key_be(config->region, (uint8_t *)config->key, config->keybits);
797 bflb_sf_ctrl_aes_set_iv_be(config->region, (uint8_t *)config->iv, config->start_addr);
798 bflb_sf_ctrl_aes_set_region(config->region, config->region_enable, hw_key_enable, config->start_addr, config->end_addr - 1, config->lock_enable);
799 }
800
bflb_flash_aes_enable(void)801 void bflb_flash_aes_enable(void)
802 {
803 bflb_sf_ctrl_aes_enable();
804 }
805
bflb_flash_aes_disable(void)806 void bflb_flash_aes_disable(void)
807 {
808 bflb_sf_ctrl_aes_disable();
809 }