1 /*
2 *********************************************************************************************************
3 * AR100 SYSTEM
4 * AR100 Software System Develop Kits
5 * clock control unit module
6 *
7 * (c) Copyright 2012-2016, Sunny China
8 * All Rights Reserved
9 *
10 * File : reset.c
11 * By : Sunny
12 * Version : v1.0
13 * Date : 2012-11-22
14 * Descript: reset control of a module.
15 * Update : date auther ver notes
16 * 2012-11-22 16:55:22 Sunny 1.0 Create this file.
17 *********************************************************************************************************
18 */
19 #include "ccu_i.h"
20 #include "hal_prcm.h"
21 #include "aw_io.h"
22 #include "aw_common.h"
23 #include "errno.h"
24
25 /*
26 *********************************************************************************************************
27 * SET RESET STATUS OF MODULE CLOCK
28 *
29 * Description: set the reset status of a specific module clock.
30 *
31 * Arguments : mclk : the module clock ID which we want to set reset status.
32 * reset : the reset status which we want to set, the detail please
33 * refer to the clock status of reset.
34 *
35 * Returns : OK if set module clock reset status succeeded, others if failed.
36 *********************************************************************************************************
37 */
ccu_set_mclk_reset(u32 mclk,s32 reset)38 s32 ccu_set_mclk_reset(u32 mclk, s32 reset)
39 {
40 switch (mclk) {
41 case CCU_MOD_CLK_MSGBOX0:
42 writel(((readl(CCU_MSGBOX_BGR_REG) & (~(0x1 << 16))) |
43 (reset << 16)),
44 CCU_MSGBOX_BGR_REG);
45 break;
46 case CCU_MOD_CLK_MSGBOX1:
47 writel(((readl(CCU_MSGBOX_BGR_REG) & (~(0x1 << 17))) |
48 (reset << 17)),
49 CCU_MSGBOX_BGR_REG);
50 break;
51 case CCU_MOD_CLK_MSGBOXR:
52 writel(((readl(CCU_R_MSGBOX_BGR_REG) & (~(0x1 << 16))) |
53 (reset << 16)),
54 CCU_R_MSGBOX_BGR_REG);
55 break;
56 case CCU_MOD_CLK_R_DMA_MCLK:
57 /* this is nothing to do with it */
58 return OK;
59 case CCU_MOD_CLK_R_DMA:
60 {
61 writel(((readl(CCU_R_DMA_BGR_REG) & (~(0x1 << 16))) |
62 (reset << 16)),
63 CCU_R_DMA_BGR_REG);
64 return OK;
65 }
66 case CCU_MOD_CLK_R_TWI:
67 {
68 ccu_reg_addr->r_twi.reset = reset;
69 return OK;
70 }
71 case CCU_MOD_CLK_R_UART:
72 {
73 ccu_reg_addr->r_uart.reset = reset;
74 return OK;
75 }
76 case CCU_MOD_CLK_R_TIMER0_1:
77 {
78 ccu_reg_addr->r_timer.reset = reset;
79 return OK;
80 }
81 case CCU_MOD_CLK_R_TWD:
82 {
83 ccu_reg_addr->r_twd.reset = reset;
84 return OK;
85 }
86 case CCU_MOD_CLK_R_PWM:
87 {
88 ccu_reg_addr->r_pwm.reset = reset;
89 return OK;
90 }
91 case CCU_MOD_CLK_R_RTC:
92 {
93 ccu_reg_addr->r_owc.reset = reset;
94 return OK;
95 }
96 case CCU_MOD_CLK_R_RSB:
97 {
98 ccu_reg_addr->r_rsb.reset = reset;
99 return OK;
100 }
101 case CCU_MOD_CLK_R_CIR:
102 {
103 ccu_reg_addr->r_ir.reset = reset;
104 return OK;
105 }
106 case CCU_MOD_CLK_VDD_SYS:
107 {
108 ccu_reg_addr->sys_pwr_rst.module_reset = reset;
109 return OK;
110 }
111 case CCU_MOD_CLK_SPINLOCK:
112 {
113 writel(((readl(CCU_SPINLOCK_BGR_REG) & (~(0x1 << 16)))
114 | (reset << 16)), CCU_SPINLOCK_BGR_REG);
115 return OK;
116 }
117 case CCU_MOD_CLK_MSGBOX:
118 {
119 writel(((readl(CCU_MSGBOX_BGR_REG) & (~(0x1 << 16)))
120 | (reset << 16)), CCU_MSGBOX_BGR_REG);
121 return OK;
122 }
123 case CCU_MOD_CLK_R_AC_ADC:
124 case CCU_MOD_CLK_R_AC_DAC:
125 case CCU_MOD_CLK_R_AUDIO_CODEC:
126 {
127 if (reset) {
128 ccu_reg_addr->r_ac_gate.reset = reset;
129 ccu_reg_addr->r_ac_gate.gate = reset;
130 } else {
131 ccu_reg_addr->r_ac_gate.gate = reset;
132 ccu_reg_addr->r_ac_gate.reset = reset;
133 }
134 return OK;
135 }
136 case CCU_MOD_CLK_R_DMIC:
137 {
138 if (reset) {
139 ccu_reg_addr->r_dmic_gate.reset = reset;
140 ccu_reg_addr->r_dmic_gate.gate = reset;
141 } else {
142 ccu_reg_addr->r_dmic_gate.gate = reset;
143 ccu_reg_addr->r_dmic_gate.reset = reset;
144 }
145 return OK;
146 }
147 case CCU_MOD_CLK_R_I2S0:
148 {
149 if (reset) {
150 writel(((readl(CCU_R_I2S_BGR_REG) & (~(0x1 << 0))) |
151 (reset << 0)), CCU_R_I2S_BGR_REG);
152 writel(((readl(CCU_R_I2S_BGR_REG) & (~(0x1 << 16))) |
153 (reset << 16)), CCU_R_I2S_BGR_REG);
154 } else {
155 writel(((readl(CCU_R_I2S_BGR_REG) & (~(0x1 << 16))) |
156 (reset << 16)), CCU_R_I2S_BGR_REG);
157 writel(((readl(CCU_R_I2S_BGR_REG) & (~(0x1 << 0))) |
158 (reset << 0)), CCU_R_I2S_BGR_REG);
159 }
160 return OK;
161 }
162 case CCU_MOD_CLK_R_I2S1:
163 {
164 if (reset) {
165 writel(((readl(CCU_R_I2S_BGR_REG) & (~(0x1 << 1))) |
166 (reset << 1)), CCU_R_I2S_BGR_REG);
167 writel(((readl(CCU_R_I2S_BGR_REG) & (~(0x1 << 17))) |
168 (reset << 17)), CCU_R_I2S_BGR_REG);
169 } else {
170 writel(((readl(CCU_R_I2S_BGR_REG) & (~(0x1 << 17))) |
171 (reset << 17)), CCU_R_I2S_BGR_REG);
172 writel(((readl(CCU_R_I2S_BGR_REG) & (~(0x1 << 1))) |
173 (reset << 1)), CCU_R_I2S_BGR_REG);
174 }
175 return OK;
176 }
177 case CCU_MOD_CLK_R_MAD_CFG:
178 {
179 if (reset) {
180 writel(((readl(CCU_R_MAD_BGR_REG) & (~(0x1 << 1))) |
181 (reset << 1)), CCU_R_MAD_BGR_REG);
182 writel(((readl(CCU_R_MAD_BGR_REG) & (~(0x1 << 17))) |
183 (reset << 17)), CCU_R_MAD_BGR_REG);
184 } else {
185 writel(((readl(CCU_R_MAD_BGR_REG) & (~(0x1 << 17))) |
186 (reset << 17)), CCU_R_MAD_BGR_REG);
187 writel(((readl(CCU_R_MAD_BGR_REG) & (~(0x1 << 1))) |
188 (reset << 1)), CCU_R_MAD_BGR_REG);
189 }
190 return OK;
191 }
192 case CCU_MOD_CLK_R_MAD:
193 {
194 if (reset) {
195 writel(((readl(CCU_R_MAD_BGR_REG) & (~(0x1 << 0))) |
196 (reset << 0)), CCU_R_MAD_BGR_REG);
197 writel(((readl(CCU_R_MAD_BGR_REG) & (~(0x1 << 16))) |
198 (reset << 16)), CCU_R_MAD_BGR_REG);
199 } else {
200 writel(((readl(CCU_R_MAD_BGR_REG) & (~(0x1 << 16))) |
201 (reset << 16)), CCU_R_MAD_BGR_REG);
202 writel(((readl(CCU_R_MAD_BGR_REG) & (~(0x1 << 0))) |
203 (reset << 0)), CCU_R_MAD_BGR_REG);
204 }
205 return OK;
206 }
207 case CCU_MOD_CLK_R_MAD_SRAM:
208 {
209 if (reset) {
210 writel(((readl(CCU_R_MAD_BGR_REG) & (~(0x1 << 3))) |
211 (reset << 3)), CCU_R_MAD_BGR_REG);
212 writel(((readl(CCU_R_MAD_BGR_REG) & (~(0x1 << 19))) |
213 (reset << 19)), CCU_R_MAD_BGR_REG);
214 } else {
215 writel(((readl(CCU_R_MAD_BGR_REG) & (~(0x1 << 19))) |
216 (reset << 19)), CCU_R_MAD_BGR_REG);
217 writel(((readl(CCU_R_MAD_BGR_REG) & (~(0x1 << 3))) |
218 (reset << 3)), CCU_R_MAD_BGR_REG);
219 }
220 return OK;
221 }
222 case CCU_MOD_CLK_R_LPSD:
223 {
224 if (reset) {
225 writel(((readl(CCU_R_MAD_BGR_REG) & (~(0x1 << 18))) |
226 (reset << 18)), CCU_R_MAD_BGR_REG);
227 } else {
228 writel(((readl(CCU_R_MAD_BGR_REG) & (~(0x1 << 18))) |
229 (reset << 18)), CCU_R_MAD_BGR_REG);
230 }
231 return OK;
232 }
233 default:
234 {
235 pr_warning("invaid module clock id (%d) when set reset\n",
236 mclk);
237 return -EINVAL;
238 }
239 }
240 /* un-reached */
241 return OK;
242 }
243
ccu_reset_module(u32 mclk)244 s32 ccu_reset_module(u32 mclk)
245 {
246 /* module reset method: set as reset valid->set as reset invalid */
247 ccu_set_mclk_reset(mclk, CCU_CLK_RESET);
248 ccu_set_mclk_reset(mclk, CCU_CLK_NRESET);
249
250 return OK;
251 }
252