| /bsp/allwinner/libraries/sunxi-hal/hal/source/ccmu/sunxi-ng/ |
| A D | clk.c | 23 struct clk *clk = NULL; in clk_get() local
38 hal_clk_status_t clk_put(struct clk *clk) in clk_put()
51 hal_clk_status_t clk_is_enabled(struct clk *clk) in clk_is_enabled()
62 hal_clk_status_t clk_prepare_enable(struct clk *clk) in clk_prepare_enable()
72 hal_clk_status_t clk_disable_unprepare(struct clk *clk) in clk_disable_unprepare()
81 struct clk *clk_get_parent(struct clk *clk) in clk_get_parent()
112 hal_clk_status_t clk_set_parent(struct clk *clk, struct clk *p_clk) in clk_set_parent()
131 hal_clk_status_t clk_get_rate(struct clk *clk, u32 *rate) in clk_get_rate()
145 hal_clk_status_t clk_set_rate(struct clk *clk, u32 rate) in clk_set_rate()
159 hal_clk_status_t clk_recalc_rate(struct clk *clk, u32 *rate) in clk_recalc_rate()
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| /bsp/allwinner/libraries/sunxi-hal/hal/source/prcm/ |
| A D | clk_compat.c | 10 hal_clk_status_t hal_clk_set_parent(hal_clk_id_t clk, hal_clk_id_t parent) in hal_clk_set_parent()
17 hal_clk_id_t hal_clk_get_parent(hal_clk_id_t clk) in hal_clk_get_parent()
22 u32 hal_clk_recalc_rate(hal_clk_id_t clk) in hal_clk_recalc_rate()
27 u32 hal_clk_round_rate(hal_clk_id_t clk, u32 rate) in hal_clk_round_rate()
33 u32 hal_clk_get_rate(hal_clk_id_t clk) in hal_clk_get_rate()
38 hal_clk_status_t hal_clk_set_rate(hal_clk_id_t clk, u32 rate) in hal_clk_set_rate()
45 hal_clk_status_t hal_clock_is_enabled(hal_clk_id_t clk) in hal_clock_is_enabled()
51 hal_clk_status_t hal_clock_enable(hal_clk_id_t clk) in hal_clock_enable()
62 hal_clk_status_t hal_clock_disable(hal_clk_id_t clk) in hal_clock_disable()
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| /bsp/allwinner/libraries/sunxi-hal/hal/source/ccmu/ |
| A D | hal_clk.c | 46 hal_clk_status_t hal_clock_put(hal_clk_t clk) in hal_clock_put()
52 hal_clk_status_t hal_clk_set_parent(hal_clk_t clk, hal_clk_t parent) in hal_clk_set_parent()
58 hal_clk_t hal_clk_get_parent(hal_clk_t clk) in hal_clk_get_parent()
64 u32 hal_clk_recalc_rate(hal_clk_t clk) in hal_clk_recalc_rate()
74 u32 hal_clk_round_rate(hal_clk_t clk, u32 rate) in hal_clk_round_rate()
84 u32 hal_clk_get_rate(hal_clk_t clk) in hal_clk_get_rate()
94 hal_clk_status_t hal_clk_set_rate(hal_clk_t clk, u32 rate) in hal_clk_set_rate()
104 hal_clk_status_t hal_clock_is_enabled(hal_clk_t clk) in hal_clock_is_enabled()
110 hal_clk_status_t hal_clock_enable(hal_clk_t clk) in hal_clock_enable()
121 hal_clk_status_t hal_clock_disable(hal_clk_t clk) in hal_clock_disable()
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| A D | common_ccmu.h | 47 #define CCMU_TRACE_CLK(tpye, clk) printf("CCMU:trace %s:%d CLK "#tpye" id %d\n",__func__, __LINE_… argument
50 #define CCMU_TRACE_CLK(clk, rate) do{} while(0) argument
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| /bsp/allwinner/libraries/sunxi-hal/hal/source/ccmu/sunxi/ |
| A D | clk.c | 79 clk_core_pt clk_get_core(hal_clk_id_t clk) in clk_get_core()
261 hal_clk_status_t sunxi_clk_disable(hal_clk_id_t clk) in sunxi_clk_disable()
317 hal_clk_status_t sunxi_clk_enabled(hal_clk_id_t clk) in sunxi_clk_enabled()
368 hal_clk_status_t sunxi_clk_is_enabled(hal_clk_id_t clk) in sunxi_clk_is_enabled()
548 hal_clk_status_t sunxi_clk_set_rate(hal_clk_id_t clk, u32 rate) in sunxi_clk_set_rate()
757 hal_clk_id_t clk_get_parent(hal_clk_id_t clk) in clk_get_parent()
773 hal_clk_status_t clk_disable_unprepare(hal_clk_id_t clk) in clk_disable_unprepare()
778 hal_clk_status_t clk_prepare_enable(hal_clk_id_t clk) in clk_prepare_enable()
783 hal_clk_status_t clk_is_enabled(hal_clk_id_t clk) in clk_is_enabled()
798 hal_clk_status_t clk_set_rate(hal_clk_id_t clk, u32 rate) in clk_set_rate()
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| A D | clk_periph.c | 37 hal_clk_status_t sunxi_clk_periph_get_parent(clk_periph_pt clk, u8 *parent_index) in sunxi_clk_periph_get_parent()
63 hal_clk_status_t sunxi_clk_periph_set_parent(clk_periph_pt clk, u8 index) in sunxi_clk_periph_set_parent()
175 hal_clk_status_t sunxi_clk_periph_enable(clk_periph_pt clk) in sunxi_clk_periph_enable()
205 hal_clk_status_t sunxi_clk_periph_is_enabled(clk_periph_pt clk) in sunxi_clk_periph_is_enabled()
342 hal_clk_status_t sunxi_clk_periph_disable(clk_periph_pt clk) in sunxi_clk_periph_disable()
367 hal_clk_status_t sunxi_clk_periph_recalc_rate(clk_periph_pt clk, u32 *rate) in sunxi_clk_periph_recalc_rate()
407 u32 sunxi_clk_periph_round_rate(clk_periph_pt clk, u32 rate, u32 prate) in sunxi_clk_periph_round_rate()
480 hal_clk_status_t sunxi_clk_periph_set_rate(clk_periph_pt clk, u32 rate) in sunxi_clk_periph_set_rate()
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| A D | clk_factors.c | 124 hal_clk_status_t sunxi_clk_fators_enable(clk_factor_pt clk) in sunxi_clk_fators_enable()
195 hal_clk_status_t sunxi_clk_fators_disable(clk_factor_pt clk) in sunxi_clk_fators_disable()
249 hal_clk_status_t sunxi_clk_fators_is_enabled(clk_factor_pt clk) in sunxi_clk_fators_is_enabled()
275 hal_clk_status_t sunxi_clk_factors_recalc_rate(clk_factor_pt clk, u32 *rate) in sunxi_clk_factors_recalc_rate()
374 hal_clk_status_t sunxi_clk_factors_set_rate(clk_factor_pt clk, u32 rate) in sunxi_clk_factors_set_rate()
493 u32 sunxi_clk_factors_round_rate(clk_factor_pt clk, u32 rate) in sunxi_clk_factors_round_rate()
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| /bsp/k230/drivers/interdrv/sysctl/sysctl_clock/ |
| A D | sysctl_clk.c | 45 int sysctl_clk_attribute(sysctl_clk_node_e clk) in sysctl_clk_attribute()
264 bool sysctl_boot_get_root_clk_bypass(sysctl_clk_node_e clk) in sysctl_boot_get_root_clk_bypass()
298 void sysctl_boot_set_root_clk_bypass(sysctl_clk_node_e clk, bool enable) in sysctl_boot_set_root_clk_bypass()
366 bool sysctl_boot_get_root_clk_en(sysctl_clk_node_e clk) in sysctl_boot_get_root_clk_en()
400 void sysctl_boot_set_root_clk_en(sysctl_clk_node_e clk, bool enable) in sysctl_boot_set_root_clk_en()
454 bool sysctl_boot_set_root_clk_pwroff(sysctl_clk_node_e clk) in sysctl_boot_set_root_clk_pwroff()
492 bool sysctl_boot_get_root_clk_lock(sysctl_clk_node_e clk) in sysctl_boot_get_root_clk_lock()
529 uint32_t sysctl_boot_get_root_clk_freq(sysctl_clk_node_e clk) in sysctl_boot_get_root_clk_freq()
672 bool sysctl_boot_set_root_clk_freq(sysctl_clk_node_e clk, uint32_t fbdiv, uint32_t refdiv, uint32_t… in sysctl_boot_set_root_clk_freq()
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| /bsp/at91/at91sam9g45/platform/ |
| A D | system_clock.c | 16 struct clk { struct
19 struct clk *parent; argument
23 static struct clk clk32k = { argument
71 struct clk *clk; in clk_get() local
84 rt_uint32_t clk_get_rate(struct clk *clk) in clk_get_rate()
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| /bsp/dm365/platform/ |
| A D | dm365.c | 64 struct clk { struct
67 struct clk *parent; argument
71 static struct clk davinci_dm365_clks[] = { argument
161 struct clk *clk; in clk_get() local
174 rt_uint32_t clk_get_rate(struct clk *clk) in clk_get_rate()
188 void clk_register(struct clk *clk) in clk_register()
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| /bsp/at91/at91sam9260/platform/ |
| A D | system_clock.c | 16 struct clk { struct
19 struct clk *parent; argument
23 static struct clk clk32k = { argument
85 struct clk *clk; in clk_get() local
98 rt_uint32_t clk_get_rate(struct clk *clk) in clk_get_rate()
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| /bsp/allwinner_tina/drivers/ |
| A D | drv_clock.c | 208 rt_err_t cpu_set_pll_clk(int clk) in cpu_set_pll_clk()
240 rt_err_t audio_set_pll_clk(int clk) in audio_set_pll_clk()
284 rt_err_t video_set_pll_clk(int clk) in video_set_pll_clk()
329 rt_err_t ve_set_pll_clk(int clk) in ve_set_pll_clk()
373 rt_err_t periph_set_pll_clk(int clk) in periph_set_pll_clk()
413 rt_err_t cpu_set_clk(int clk) in cpu_set_clk()
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| A D | drv_sdio.c | 257 static rt_err_t mmc_config_clock(tina_mmc_t mmc, int clk) in mmc_config_clock()
293 static rt_err_t mmc_set_ios(tina_mmc_t mmc, int clk, int bus_width) in mmc_set_ios()
601 int clk = io_cfg->clock; local
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| /bsp/allwinner/libraries/sunxi-hal/hal/source/disp2/disp/ |
| A D | disp_sys_intf.c | 27 hal_clk_id_t clk = (hal_clk_id_t)p_clk; in disp_sys_clk_set_rate() local
41 hal_clk_id_t clk = (hal_clk_id_t)p_clk; in disp_sys_clk_get_rate() local
48 s32 disp_sys_clk_enable(hal_clk_id_t clk) in disp_sys_clk_enable()
81 bool disp_clock_is_enabled(hal_clk_id_t clk) in disp_clock_is_enabled()
93 s32 disp_sys_clk_disable(hal_clk_id_t clk) in disp_sys_clk_disable()
122 s32 disp_sys_clk_set_parent(hal_clk_id_t clk, hal_clk_id_t parent) in disp_sys_clk_set_parent()
146 hal_clk_id_t disp_sys_clk_get_parent(hal_clk_id_t clk) in disp_sys_clk_get_parent()
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| /bsp/rockchip/common/rk_hal/lib/hal/src/cru/ |
| A D | hal_cru.c | 631 HAL_Check HAL_CRU_ClkIsEnabled(uint32_t clk) in HAL_CRU_ClkIsEnabled()
659 HAL_Status HAL_CRU_ClkEnable(uint32_t clk) in HAL_CRU_ClkEnable()
686 HAL_Status HAL_CRU_ClkDisable(uint32_t clk) in HAL_CRU_ClkDisable()
713 HAL_Check HAL_CRU_ClkIsReset(uint32_t clk) in HAL_CRU_ClkIsReset()
737 HAL_Status HAL_CRU_ClkResetAssert(uint32_t clk) in HAL_CRU_ClkResetAssert()
761 HAL_Status HAL_CRU_ClkResetDeassert(uint32_t clk) in HAL_CRU_ClkResetDeassert()
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| /bsp/allwinner/libraries/sunxi-hal/hal/source/disp2/soc/ |
| A D | platform_resource.c | 69 s32 plat_get_clk_parent(hal_clk_id_t clk, hal_clk_id_t *parent) in plat_get_clk_parent()
83 s32 plat_get_clk_from_id(hal_clk_id_t clk_id, hal_clk_t *clk, struct reset_control **rst) in plat_get_clk_from_id()
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| /bsp/allwinner/libraries/sunxi-hal/hal/test/ccmu/ |
| A D | test_ng_ccmu.c | 34 int is_strict_clk(hal_clk_t clk) in is_strict_clk()
63 hal_clk_t clk, p_clk; in cmd_test_ng_ccmu() local
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| /bsp/airm2m/air32f103/libraries/rt_drivers/ |
| A D | drv_hwtimer.c | 25 rt_uint32_t clk = 0; in air32_hwtimer_init() local
155 rt_uint32_t clk = 0; in air32_hwtimer_control() local
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| /bsp/allwinner/libraries/sunxi-hal/include/hal/ |
| A D | hal_clk.h | 74 #define CCMU_TRACE_CLK(tpye, clk) printf("CCMU:trace %s:%d CLK "#tpye" id %d\n",__func__, __LINE_… argument
77 #define CCMU_TRACE_CLK(clk, rate) do{} while(0) argument
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| /bsp/wch/arm/Libraries/ch32_drivers/ |
| A D | drv_hwtimer_ch32f10x.c | 64 rt_uint32_t clk = 0; in ch32f1_hwtimer_init() local
194 rt_uint32_t clk = 0; in ch32f1_hwtimer_control() local
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| A D | drv_hwtimer_ch32f20x.c | 112 rt_uint32_t clk = 0; in ch32f2_hwtimer_init() local
242 rt_uint32_t clk = 0; in ch32f2_hwtimer_control() local
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| /bsp/nuvoton/libraries/m480/rtt_port/ |
| A D | drv_wdt.c | 186 uint32_t clk, new_hz; in wdt_pm_frequency_change() local
293 uint32_t clk, hz = 0; in wdt_get_working_hz() local
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| /bsp/nuvoton/libraries/m031/rtt_port/ |
| A D | drv_wdt.c | 189 uint32_t clk, new_hz; in wdt_pm_frequency_change() local
297 uint32_t clk, hz = 0; in wdt_get_working_hz() local
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| /bsp/nuvoton/libraries/m2354/rtt_port/ |
| A D | drv_wdt.c | 189 uint32_t clk, new_hz; in wdt_pm_frequency_change() local
296 uint32_t clk, hz = 0; in wdt_get_working_hz() local
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| /bsp/n32/libraries/n32_drivers/ |
| A D | drv_hwtimer.c | 169 uint32_t clk; in n32_hwtimer_control() local
245 uint32_t clk; in n32_hwtimer_init() local
|