1 /* 2 * Copyright (c) 2021 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 #ifndef HPM_ROMAPI_XPI_NOR_DEF_H 8 #define HPM_ROMAPI_XPI_NOR_DEF_H 9 10 /** 11 * @brief XPI NOR ROM APIs 12 * @defgroup xpi_nor_interface XPI NOR driver APIs 13 * @ingroup romapi_interfaces 14 * @{ 15 */ 16 17 18 #include "hpm_common.h" 19 #include "hpm_romapi_xpi_def.h" 20 21 #define XPI_NOR_CFG_TAG 0x524f4E58U /**< ASCII: "XNOR" */ 22 23 /** 24 * @brief XPI NOR properties 25 */ 26 enum { 27 xpi_nor_property_total_size, /**< Total size in bytes */ 28 xpi_nor_property_page_size, /**< Page size in bytes */ 29 xpi_nor_property_sector_size, /**<sector size in bytes */ 30 xpi_nor_property_block_size, /**< block size in bytes */ 31 xpi_nor_property_max = xpi_nor_property_block_size, 32 }; 33 34 35 /** 36 * @brief XPI NOR safe frequency option 37 */ 38 enum { 39 xpi_nor_clk_safe_clk_freq = 1, 40 }; 41 42 /** 43 * @brief XPI NOR miscellaneous options 44 */ 45 enum { 46 xpi_nor_option_misc_spi_only = 1, /**< SPI only */ 47 xpi_nor_option_misc_internal_loopback = 2, /**< Internal loopback mode */ 48 xpi_nor_option_misc_ext_dqs = 3, /**< External DQS pin */ 49 }; 50 51 /** 52 * @brief XPI NOR connection option 53 */ 54 enum { 55 xpi_nor_connection_sel_chna_cs0, /**< Channel A, CS0 */ 56 xpi_nor_connection_sel_chnb_cs0, /**< Channel B, CS0 */ 57 xpi_nor_connection_sel_chna_cs0_chnb_cs0, /**< Channel A + Channel B, CS0 */ 58 xpi_nor_connection_sel_chna_cs0_cs1, /**< Channel A, CS0 + CS1 */ 59 xpi_nor_connection_sel_chnb_cs0_cs1 /**< Channel B, CS0 + CS1 */ 60 }; 61 62 /** 63 * @brief QE bit enable sequence option 64 */ 65 typedef enum { 66 xpi_nor_quad_en_auto_or_ignore = 0U, /**< Auto enable or ignore */ 67 xpi_nor_quad_en_set_bit6_in_status_reg1 = 1U, /**< QE bit is at bit6 in Status register 1 */ 68 xpi_nor_quad_en_set_bit1_in_status_reg2 = 2U, /**< QE bit is at bit1 in Status register 2 register 2 */ 69 xpi_nor_quad_en_set_bit7_in_status_reg2 = 3U, /**< QE bit is at bit7 in Status register 2 */ 70 xpi_nor_quad_en_set_bi1_in_status_reg2_via_0x31_cmd = 4U, /**< QE bit is in status register 2 and configured by CMD 0x31 */ 71 } xpi_nor_quad_enable_seq_t; 72 73 /** 74 * @brief XPI working mode 75 */ 76 typedef enum { 77 xpi_working_mode_extend_spi, /**< XPI works in extended SPI mode, including 1-1-1, 1-2-2, 1-4-4, 1-8-8 */ 78 xpi_working_mode_xpi, /**< XPI works in XPI mode, including, 1-1-1, 2-2-2, 4-4-4, 8-8-8 */ 79 xpi_working_mode_hyperbus, /**< XPI works in HyperBus mode */ 80 } xpi_working_mode_t; 81 82 83 /** 84 * @brief XPI NOR configuration command type 85 */ 86 typedef enum { 87 xpi_nor_cfg_cmd_type_no_cfg = 0U, /**< No configuration */ 88 xpi_nor_cfg_cmd_type_generic = 1U, /**< Generic configuration */ 89 xpi_nor_cfg_cmd_type_spi2xpi = 2U, /**< SPI to XPI mode */ 90 xpi_nor_cfg_cmd_type_xpi2spi = 3U, /**< XPI to SPI mode */ 91 } xpi_nor_cfg_cmd_type_t; 92 93 /** 94 * @brief XPI NOR probe options 95 */ 96 typedef enum { 97 xpi_nor_probe_sfdp_sdr = 0U, /**< Probe FLASH using SFDP and set FLASH to SDR mode */ 98 xpi_nor_probe_sfdp_ddr = 1U, /**< Probe FLASH using SDP and set FLASH to DDR mode */ 99 xpi_nor_quad_read_0xeb = 2U, /**< Set FLASH to default Quad I/O read in SDR mode */ 100 xpi_nor_dual_read_0xbb = 3U, /**< Set FLASH to default Dual I/O read in SDR mode */ 101 xpi_nor_hyperbus_1v8 = 4U, /**< Probe FLASH using HyperBus in 1.8V voltage */ 102 xpi_nor_hyperbus_3v0 = 5U, /**< Probe FLASH using HyperBus in 3.0V voltage */ 103 xpi_nor_octabus_ddr = 6U, /**< Probe FLASH using Macronix OctaBus and configure FLASH to OPI DDR mode */ 104 xpi_nor_octabus_sdr = 7U, /**< Probe FLASH using Macronix OctaBus and configure FLASH to OPI SDR mode */ 105 xpi_nor_xccela_ddr = 8U, /**< Probe FLASH using Xccela Protocol and configure FLASH to OPI DDR mode */ 106 xpi_nor_xccela_sdr = 9U, /**< Probe FLASH using Xccela Protocol and configure FLASH to SDR mode */ 107 xpi_nor_ecoxip_ddr = 10U, /**< Probe FLASH using EcoXiP Protocol and configure FLASH to OPI DDR mode */ 108 xpi_nor_ecoxip_sdr = 11U, /**< Probe FLASH using EcoXiP Protocol and configure FLASH to SDR mode */ 109 } xpi_nor_probe_t; 110 111 /** 112 * @brief Standard XPI NOR seuqnce index definitions 113 */ 114 typedef enum { 115 xpi_std_nor_seq_idx_read = 0U, /**< 0 - Read */ 116 xpi_std_nor_seq_idx_page_program = 1U, /**< 1 - Page Program */ 117 xpi_std_nor_seq_idx_read_status = 2U, /**< 2 - Read Status */ 118 xpi_std_nor_seq_idx_read_status_xpi = 3U, /**< 3 - Read Status in xSPI mode */ 119 xpi_std_nor_seq_idx_write_enable = 4U, /**< 4 - Write Enable */ 120 xpi_std_nor_seq_idx_write_enable_xpi = 5U, /**< 5 - Write Enable in xSPI mode */ 121 xpi_std_nor_seq_idx_erase_sector = 6U, /**< 6 - Erase sector */ 122 xpi_std_nor_seq_idx_erase_block = 7U, /**< 7 - Erase block */ 123 xpi_std_nor_seq_idx_erase_chip = 8U, /**< 8 - Erase full chip */ 124 xpi_std_nor_seq_idx_max = 9, /**< 9 */ 125 } xpi_std_nor_instr_idx_t; 126 127 /** 128 * @brief XPI NOR option tag 129 */ 130 #define XPI_NOR_CFG_OPTION_TAG (0xfcf90U) 131 132 /** 133 * @brief XPI NOR configuration option 134 * The ROM SW can detect the FLASH configuration based on the following structure specified by the end-user 135 */ 136 typedef struct { 137 union { 138 struct { 139 uint32_t words: 4; /**< Option words, exclude the header itself */ 140 uint32_t reserved: 8; /**< Reserved for future use */ 141 uint32_t tag: 20; /**< Must be 0xfcf90 */ 142 }; 143 uint32_t U; 144 } header; 145 union { 146 struct { 147 uint32_t freq_opt: 4; /**< 1 - 30MHz, others, SoC specific setting */ 148 uint32_t misc: 4; /**< Not used for now */ 149 uint32_t dummy_cycles: 8; /**< 0 - Auto detected/ use predefined value, others - specified by end-user */ 150 uint32_t quad_enable_seq: 4; /**< See the xpi_nor_quad_enable_seq_t definitions for more details */ 151 uint32_t cmd_pads_after_init: 4; /**< See the xpi_data_pad_t definitions for more details */ 152 uint32_t cmd_pads_after_por: 4; /**< See the xpi_data_pad_t definitions for more details */ 153 uint32_t probe_type: 4; /**< See the xpi_nor_probe_t definitions for more details */ 154 }; 155 uint32_t U; 156 } option0; 157 union { 158 struct { 159 uint32_t drive_strength: 8; /**< IO drive strength, 0 - pre-defined, Others - specified by end-user */ 160 uint32_t connection_sel: 4; /**< Device connection selection: 0 - PORTA, 1 - PORTB, 2 - Parallel mode */ 161 uint32_t pin_group_sel: 4; /**< Pin group selection, 0 - 1st group, 1 - 2nd group, by default, the pin group is 1st group */ 162 uint32_t io_voltage: 4; /**< SoC pad voltage, 0 - 3.0V, 1-1.8V */ 163 uint32_t reserved: 12; /**< Reserved for future use */ 164 }; 165 uint32_t U; 166 } option1; 167 union { 168 struct { 169 uint32_t flash_size_option:8; /**< FLASH size option */ 170 uint32_t flash_sector_size_option:4; /**< FLASH sector size option */ 171 uint32_t flash_sector_erase_cmd_option:4; /**< Sector Erase command option */ 172 uint32_t reserved:20; 173 }; 174 uint32_t U; 175 } option2; 176 } xpi_nor_config_option_t; 177 178 /** 179 * @brief Sector size options 180 */ 181 enum { 182 serial_nor_sector_size_4kb, /**< Sector size: 4KB */ 183 serial_nor_sector_size_32kb, /**< Sector size: 32KB */ 184 serial_nor_sector_size_64kb, /**< Sector size: 64KB */ 185 serial_nor_sector_size_256kb, /**< Sector size: 256KB */ 186 }; 187 188 /** 189 * @brief Sector erase command options 190 */ 191 enum { 192 serial_nor_erase_type_4kb, /**< Sector erase command: 4KB Erase */ 193 serial_nor_erase_type_32kb, /**< Sector erase command: 32KB Erase */ 194 serial_nor_erase_type_64kb, /**< Sector erase command: 64KB Erase */ 195 serial_nor_erase_type_256kb, /**< Sector erase command: 256KB Erase */ 196 }; 197 198 /** 199 * @brief FLASH size options 200 */ 201 enum { 202 flash_size_4mb, /**< FLASH size: 4MB */ 203 flash_size_8mb, /**< FLASH size: 8MB */ 204 flash_size_16mb, /**< FLASH size: 16MB */ 205 }; 206 207 /** 208 * @brief Device Mode configuration structure 209 */ 210 typedef struct { 211 uint8_t cfg_cmd_type; /**< Configuration command type */ 212 uint8_t param_size; /**< Size for parameter */ 213 } device_mode_cfg_t; 214 215 /** 216 * @brief Device mode parameter structure 217 */ 218 typedef struct { 219 uint32_t instr_seq[4]; /**< Command Instruction sequence*/ 220 uint32_t param; /**< Parameter */ 221 } device_mode_param_t; 222 223 /** 224 * @brief XPI NOR device information structure 225 */ 226 typedef struct { 227 uint32_t size_in_kbytes; /**< Device Size in Kilobytes, offset 0x00 */ 228 uint16_t page_size; /**< Page size, offset 0x04 */ 229 uint16_t sector_size_kbytes; /**< Sector size in kilobytes, offset 0x06 */ 230 uint16_t block_size_kbytes; /**< Block size in kilobytes, offset 0x08 */ 231 uint8_t busy_offset; /**< Busy offset, offset 0x0a */ 232 uint8_t busy_polarity; /**< Busy polarity, offset 0x0b */ 233 uint8_t data_pads; /**< Device Size in Kilobytes, offset 0x0c */ 234 uint8_t en_ddr_mode; /**< Enable DDR mode, offset 0x0d */ 235 uint8_t clk_freq_for_device_cfg; /**< Clk frequency for device configuration offset 0x0e */ 236 uint8_t working_mode_por; /**< Working mode after POR reset offset 0x0f */ 237 uint8_t working_mode; /**< The device working mode, offset 0x10 */ 238 uint8_t en_diff_clk; /**< Enable Differential clock, offset 0x11 */ 239 uint8_t data_valid_time; /**< Data valid time, in 0.1ns, offset 0x12 */ 240 uint8_t en_half_clk_for_non_read_cmd; /**< Enable half clock for non-read command, offset 0x13 */ 241 uint8_t clk_freq_for_non_read_cmd; /**< Enable safe clock for non-read command, offset 0x14 */ 242 uint8_t dll_dly_target; /**< XPI DLL Delay Target, offset 0x15 */ 243 uint8_t io_voltage; /**< IO voltage, offset 0x16 */ 244 uint8_t reserved0; /**< Reserved for future use, offset 0x17 */ 245 uint8_t cs_hold_time; /**< CS hold time, 0 - default value, others - user specified value, offset 0x18 */ 246 uint8_t cs_setup_time; /**< CS setup time, 0 - default value, others - user specified value, offset 0x19 */ 247 uint8_t cs_interval; /**< CS interval, intervals between to CS active, offset 0x1a */ 248 uint8_t en_dev_mode_cfg; /**< Enable device mode configuration, offset 0x1b */ 249 uint32_t flash_state_ctx; /**< Flash state context, offset 0x1c */ 250 device_mode_cfg_t mode_cfg_list[2]; /**< Mode configuration sequences, offset 0x20 */ 251 uint32_t mode_cfg_param[2]; /**< Mode configuration parameters, offset 0x24 */ 252 uint32_t reserved1; /**< Reserved for future use, offset 0x2C */ 253 struct { 254 uint32_t entry[4]; 255 } cfg_instr_seq[2]; /**< Mode Configuration Instruction sequence, offset 0x30 */ 256 } xpi_device_info_t; 257 258 /** 259 * @brief XPI NOR configuration structure 260 */ 261 typedef struct { 262 uint32_t tag; /**< Must be "XNOR", offset 0x000 */ 263 uint32_t reserved0; /**< Reserved for future use, offset 0x004 */ 264 uint8_t rxclk_src; /**< RXCLKSRC value, offset 0x008 */ 265 uint8_t clk_freq; /**< Clock frequency, offset 0x009 */ 266 uint8_t drive_strength; /**< Drive strength, offset 0x0a */ 267 uint8_t column_addr_size; /**< Column address size, offset 0x0b */ 268 uint8_t rxclk_src_for_init; /**< RXCLKSRC during FLASH initialization, offset 0x0c */ 269 uint8_t config_in_progress; /**< Indicate whether device configuration is in progress, offset: 0x0d */ 270 uint8_t reserved[2]; /**< Reserved for future use, offset 0x00f */ 271 struct { 272 uint8_t enable; /**< Port enable flag, 0 - not enabled, 1 - enabled */ 273 uint8_t group; /**< 0 - 1st IO group, 1 - 2nd IO group */ 274 uint8_t reserved[2]; 275 } chn_info[4]; /**< Device connection information */ 276 xpi_device_info_t device_info; /**< Device info, offset 0x20 */ 277 xpi_instr_seq_t instr_set[xpi_std_nor_seq_idx_max];/**< Standard instruction sequence table, offset 0x70 */ 278 } xpi_nor_config_t; 279 280 /** 281 * @brief FLASH runtime context structure 282 */ 283 typedef union { 284 struct { 285 uint32_t wait_time: 7; /**< Wait time */ 286 uint32_t wait_time_unit: 1; /**< 0 - 10us, 1 - 1ms */ 287 uint32_t reset_gpio: 8; /**<Reset GPIO */ 288 uint32_t restore_sequence: 4; /**<Restore sequence */ 289 uint32_t exit_no_cmd_sequence: 4; /**< Exit no-cmd sequence */ 290 uint32_t current_mode: 4; /**< Current FLASH mode */ 291 uint32_t por_mode: 4; /**< FLASH mode upon Power-on Reset */ 292 }; 293 uint32_t U; 294 } flash_run_context_t; 295 296 /** 297 * @brief XPI NOR API error codes 298 */ 299 enum { 300 status_xpi_nor_sfdp_not_found = MAKE_STATUS(status_group_xpi_nor, 0), /**< SFDP table was not found */ 301 status_xpi_nor_ddr_read_dummy_cycle_probe_failed = MAKE_STATUS(status_group_xpi_nor, 1), /**< Probing Dummy cyles for DDR read failed */ 302 status_xpi_nor_flash_not_found = MAKE_STATUS(status_group_xpi_nor, 2), /**< FLASH was not detected */ 303 }; 304 305 /** 306 * @} 307 */ 308 309 #endif /* HPM_ROMAPI_XPI_NOR_DEF_H */ 310