1 /** 2 ****************************************************************************** 3 * @file bflb_sf_ctrl.h 4 * @version V1.0 5 * @date 6 * @brief This file is the standard driver header file 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2> 11 * 12 * Redistribution and use in source and binary forms, with or without modification, 13 * are permitted provided that the following conditions are met: 14 * 1. Redistributions of source code must retain the above copyright notice, 15 * this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright notice, 17 * this list of conditions and the following disclaimer in the documentation 18 * and/or other materials provided with the distribution. 19 * 3. Neither the name of Bouffalo Lab nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 30 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 ****************************************************************************** 35 */ 36 #ifndef __BL628_SF_CTRL_H__ 37 #define __BL628_SF_CTRL_H__ 38 39 #include "bflb_core.h" 40 41 /** @addtogroup BL628_Peripheral_Driver 42 * @{ 43 */ 44 45 /** @addtogroup SF_CTRL 46 * @{ 47 */ 48 49 /** @defgroup SF_CTRL_Public_Types 50 * @{ 51 */ 52 53 #if defined(BL602) || defined(BL702) || defined(BL702L) 54 #define BFLB_SF_CTRL_BASE ((uint32_t)0x4000B000) 55 #elif defined(BL606P) || defined(BL808) || defined(BL616) 56 #define BFLB_SF_CTRL_BASE ((uint32_t)0x2000b000) 57 #elif defined(BL628) 58 #define BFLB_SF_CTRL_BASE ((uint32_t)0x20082000) 59 #endif 60 61 #if defined(BL602) || defined(BL702) || defined(BL702L) 62 #define BFLB_FLASH_XIP_BASE (0x23000000) 63 #define BFLB_FLASH_XIP_END (0x23000000 + 16 * 1024 * 1024) 64 #elif defined(BL606P) || defined(BL808) 65 #define BFLB_FLASH_XIP_BASE (0x58000000) 66 #define BFLB_FLASH_XIP_END (0x58000000 + 64 * 1024 * 1024) 67 #elif defined(BL616) 68 #define BFLB_FLASH_XIP_BASE (0xA0000000) 69 #define BFLB_FLASH_XIP_END (0xA0000000 + 64 * 1024 * 1024) 70 #elif defined(BL628) 71 #define BFLB_FLASH_XIP_BASE (0x80000000) 72 #define BFLB_FLASH_XIP_END (0x80000000 + 64 * 1024 * 1024) 73 #endif 74 75 #if defined(BL628) || defined(BL616) || defined(BL808) || defined(BL606P) 76 #ifndef CONFIG_DISABLE_SBUS2_ENABLE_SUPPORT 77 #define BFLB_SF_CTRL_SBUS2_ENABLE 78 #endif 79 #define BFLB_SF_CTRL_32BITS_ADDR_ENABLE 80 #define BFLB_SF_CTRL_AES_XTS_ENABLE 81 #endif 82 #if defined(BL702) || defined(BL702L) 83 #define BFLB_SF_CTRL_PSRAM_ENABLE 84 #endif 85 86 /** 87 * @brief Serial flash pad type definition 88 */ 89 #define SF_CTRL_PAD1 0 /*!< SF Ctrl pad 1 */ 90 #define SF_CTRL_PAD2 1 /*!< SF Ctrl pad 2 */ 91 #define SF_CTRL_PAD3 2 /*!< SF Ctrl pad 3 */ 92 93 /** 94 * @brief Serial flash config pin select type definition 95 */ 96 #if defined(BL628) || defined(BL616) 97 #define SF_IO_EMB_SWAP_IO3IO0 0x0 /*!< SF select embedded flash swap io3 with io0 */ 98 #define SF_IO_EMB_SWAP_IO3IO0_IO2CS 0x1 /*!< SF select embedded flash swap io3 with io0 and io2 with cs */ 99 #define SF_IO_EMB_SWAP_NONE 0x2 /*!< SF select embedded flash no swap */ 100 #define SF_IO_EMB_SWAP_IO2CS 0x3 /*!< SF select embedded flash swap io2 with cs */ 101 #define SF_IO_EXT_SF2_SWAP_IO3IO0 0x4 /*!< SF select external flash SF2 use gpio4-9 and SF2 swap io3 with io0 */ 102 #define SF_IO_EXT_SF3 0x8 /*!< SF select external flash SF3 use gpio10-15 */ 103 #define SF_IO_EMB_SWAP_IO3IO0_AND_SF2_SWAP_IO3IO0 0x14 /*!< SF select embedded flash swap io3 with io0 and SF2 swap io3 with io0*/ 104 #define SF_IO_EMB_SWAP_IO3IO0_IO2CS_AND_SF2_SWAP_IO3IO0 0x15 /*!< SF select embedded flash swap io3 with io0、io2 with cs and SF2 swap io3 with io0 */ 105 #define SF_IO_EMB_SWAP_NONE_AND_SF2_SWAP_IO3IO0 0x16 /*!< SF select embedded flash no swap and SF2 swap io3 with io0 */ 106 #define SF_IO_EMB_SWAP_IO2CS_AND_SF2_SWAP_IO3IO0 0x17 /*!< SF select embedded flash swap io2 with cs, and SF2 swap io3 with io0 */ 107 #define SF_IO_EXT_SF2 0x24 /*!< SF select external flash SF2 use gpio4-9 */ 108 #define SF_IO_EMB_SWAP_IO3IO0_AND_SF2 0x34 /*!< SF select embedded flash swap io3 with io0 and SF2 use gpio4-9 */ 109 #define SF_IO_EMB_SWAP_IO3IO0_IO2CS_AND_SF2 0x35 /*!< SF select embedded flash swap io3 with io0、io2 with cs and SF2 use gpio4-9 */ 110 #define SF_IO_EMB_SWAP_NONE_AND_SF2 0x36 /*!< SF select embedded flash no swap and SF2 use gpio4-9 */ 111 #define SF_IO_EMB_SWAP_IO2CS_AND_SF2 0x37 /*!< SF select embedded flash swap io2 with cs and SF2 use gpio4-9 */ 112 #elif defined(BL808) || defined(BL606P) 113 #define SF_IO_EMB_SWAP_IO0_IO3 0x0 /*!< SF select embedded flash swap io0 with io3 */ 114 #define SF_IO_EMB_SWAP_DUAL_IO0_IO3 0x1 /*!< SF select embedded flash swap dual io0 with io3 */ 115 #define SF_IO_EMB_SWAP_NONE 0x2 /*!< SF select embedded flash no swap */ 116 #define SF_IO_EMB_SWAP_NONE_DUAL_IO0 0x3 /*!< SF select embedded flash no swap and use dual io0 */ 117 #define SF_IO_EXT_SF2 0x4 /*!< SF select external flash SF2 use gpio34-39 */ 118 #define SF_IO_EMB_SWAP_IO0_IO3_AND_EXT_SF2 0x14 /*!< SF select embedded flash swap io0 with io3 and external SF2 use gpio34-39 */ 119 #define SF_IO_EMB_SWAP_DUAL_IO0_IO3_AND_EXT_SF2 0x15 /*!< SF select embedded flash swap dual io0 with io3 and external SF2 use gpio34-39 */ 120 #define SF_IO_EMB_SWAP_NONE_AND_EXT_SF2 0x16 /*!< SF select embedded flash no swap and external SF2 use gpio34-39 */ 121 #define SF_IO_EMB_SWAP_NONE_DUAL_IO0_AND_EXT_SF2 0x17 /*!< SF select embedded flash no swap, use dual io0 and external SF2 use gpio34-39 */ 122 #elif defined(BL702L) 123 #define SF_CTRL_SEL_EXTERNAL_FLASH 0x0 /*!< SF select sf2, flash use GPIO 23-28, external flash */ 124 #define SF_CTRL_SEL_INTERNAL_FLASH_SWAP_NONE 0x1 /*!< SF select sf1, embedded flash do not swap */ 125 #define SF_CTRL_SEL_INTERNAL_FLASH_SWAP_CSIO2 0x2 /*!< SF select sf1, embedded flash swap cs/io2 */ 126 #define SF_CTRL_SEL_INTERNAL_FLASH_SWAP_IO0IO3 0x3 /*!< SF select sf1, embedded flash swap io0/io3 */ 127 #define SF_CTRL_SEL_INTERNAL_FLASH_SWAP_BOTH 0x4 /*!< SF select sf1, embedded flash swap cs/io2 and io0/io3 */ 128 #define SF_CTRL_SEL_INTERNAL_FLASH_REVERSE_SWAP_NONE 0x5 /*!< SF select sf1, embedded flash interface reverse and do not swap */ 129 #define SF_CTRL_SEL_INTERNAL_FLASH_REVERSE_SWAP_CSIO2 0x6 /*!< SF select sf1, embedded flash interface reverse and swap cs/io2 */ 130 #define SF_CTRL_SEL_INTERNAL_FLASH_REVERSE_SWAP_IO0IO3 0x7 /*!< SF select sf1, embedded flash interface reverse and swap io0/io3 */ 131 #define SF_CTRL_SEL_INTERNAL_FLASH_REVERSE_SWAP_BOTH 0x8 /*!< SF select sf1, embedded flash interface reverse and swap cs/io2 and io0/io3 */ 132 #elif defined(BL702) 133 #define SF_CTRL_SEL_SF1 0x0 /*!< SF Ctrl select sf1, flash use GPIO 17-22, no psram */ 134 #define SF_CTRL_SEL_SF2 0x1 /*!< SF Ctrl select sf2, flash use GPIO 23-28, no psram, embedded flash */ 135 #define SF_CTRL_SEL_SF3 0x2 /*!< SF Ctrl select sf3, flash use GPIO 32-37, no psram */ 136 #define SF_CTRL_SEL_DUAL_BANK_SF1_SF2 0x3 /*!< SF Ctrl select sf1 and sf2, flash use GPIO 17-22, psram use GPIO 23-28 */ 137 #define SF_CTRL_SEL_DUAL_BANK_SF2_SF3 0x4 /*!< SF Ctrl select sf2 and sf3, flash use GPIO 23-28, psram use GPIO 32-37 */ 138 #define SF_CTRL_SEL_DUAL_BANK_SF3_SF1 0x5 /*!< SF Ctrl select sf3 and sf1, flash use GPIO 32-37, psram use GPIO 17-22 */ 139 #define SF_CTRL_SEL_DUAL_CS_SF2 0x6 /*!< SF Ctrl select sf2, flash/psram use GPIO 23-28, psram use GPIO 17 as CS2 */ 140 #define SF_CTRL_SEL_DUAL_CS_SF3 0x7 /*!< SF Ctrl select sf3, flash/psram use GPIO 32-37, psram use GPIO 23 as CS2 */ 141 #elif defined(BL602) 142 #define SF_CTRL_EMBEDDED_SEL 0x0 /*!< Embedded flash select */ 143 #define SF_CTRL_EXTERNAL_17TO22_SEL 0x1 /*!< External flash select gpio 17-22 */ 144 #define SF_CTRL_EXTERNAL_0TO2_20TO22_SEL 0x2 /*!< External flash select gpio 0-2 and 20-22 */ 145 #endif 146 147 148 /** 149 * @brief Serial flash select bank control type definition 150 */ 151 #if defined(BL702) || defined(BL702L) 152 #define SF_CTRL_SEL_FLASH 0 /*!< SF Ctrl system bus control flash */ 153 #define SF_CTRL_SEL_PSRAM 1 /*!< SF Ctrl system bus control psram */ 154 #else 155 #define SF_CTRL_FLASH_BANK0 0 /*!< SF Ctrl select flash bank0 */ 156 #define SF_CTRL_FLASH_BANK1 1 /*!< SF Ctrl select flash bank1 */ 157 #endif 158 159 /** 160 * @brief Serial flash controller wrap mode type definition 161 */ 162 #define SF_CTRL_WRAP_MODE_0 0 /*!< Cmds bypass wrap commands to macro, original mode */ 163 #define SF_CTRL_WRAP_MODE_1 1 /*!< Cmds handle wrap commands, original mode */ 164 #define SF_CTRL_WRAP_MODE_2 2 /*!< Cmds bypass wrap commands to macro, cmds force wrap16*4 splitted into two wrap8*4 */ 165 #define SF_CTRL_WRAP_MODE_3 3 /*!< Cmds handle wrap commands, cmds force wrap16*4 splitted into two wrap8*4 */ 166 167 /** 168 * @brief Serail flash controller wrap mode len type definition 169 */ 170 #define SF_CTRL_WRAP_LEN_8 0 /*!< SF Ctrl wrap length: 8 */ 171 #define SF_CTRL_WRAP_LEN_16 1 /*!< SF Ctrl wrap length: 16 */ 172 #define SF_CTRL_WRAP_LEN_32 2 /*!< SF Ctrl wrap length: 32 */ 173 #define SF_CTRL_WRAP_LEN_64 3 /*!< SF Ctrl wrap length: 64 */ 174 #define SF_CTRL_WRAP_LEN_128 4 /*!< SF Ctrl wrap length: 128 */ 175 #define SF_CTRL_WRAP_LEN_256 5 /*!< SF Ctrl wrap length: 256 */ 176 #define SF_CTRL_WRAP_LEN_512 6 /*!< SF Ctrl wrap length: 512 */ 177 #define SF_CTRL_WRAP_LEN_1024 7 /*!< SF Ctrl wrap length: 1024 */ 178 #define SF_CTRL_WRAP_LEN_2048 8 /*!< SF Ctrl wrap length: 2048 */ 179 #define SF_CTRL_WRAP_LEN_4096 9 /*!< SF Ctrl wrap length: 4096 */ 180 181 /** 182 * @brief Serail flash controller memory remap type define 183 */ 184 #define SF_CTRL_ORIGINAL_MEMORY_MAP 0 /*!< Remap none, use two addr map when use dual flash */ 185 #define SF_CTRL_REMAP_16MB 1 /*!< Remap HADDR>16MB region to psram port HADDR[24] -> HADDR[28] */ 186 #define SF_CTRL_REMAP_8MB 2 /*!< Remap HADDR>8MB region to psram port HADDR[23] -> HADDR[28] */ 187 #define SF_CTRL_REMAP_4MB 3 /*!< Remap HADDR>4MB region to psram port HADDR[22] -> HADDR[28] */ 188 189 /** 190 * @brief Serial flash controller select clock type definition 191 */ 192 #define SF_CTRL_OWNER_SAHB 0 /*!< System AHB bus control serial flash controller */ 193 #define SF_CTRL_OWNER_IAHB 1 /*!< I-Code AHB bus control serial flash controller */ 194 195 /** 196 * @brief Serial flash controller select clock type definition 197 */ 198 #define SF_CTRL_SAHB_CLOCK 0 /*!< Serial flash controller select default sahb clock */ 199 #define SF_CTRL_FLASH_CLOCK 1 /*!< Serial flash controller select flash clock */ 200 201 /** 202 * @brief Read and write type definition 203 */ 204 #define SF_CTRL_READ 0 /*!< Serail flash read command flag */ 205 #define SF_CTRL_WRITE 1 /*!< Serail flash write command flag */ 206 207 /** 208 * @brief Serail flash interface IO type definition 209 */ 210 #define SF_CTRL_NIO_MODE 0 /*!< Normal IO mode define */ 211 #define SF_CTRL_DO_MODE 1 /*!< Dual Output mode define */ 212 #define SF_CTRL_QO_MODE 2 /*!< Quad Output mode define */ 213 #define SF_CTRL_DIO_MODE 3 /*!< Dual IO mode define */ 214 #define SF_CTRL_QIO_MODE 4 /*!< Quad IO mode define */ 215 216 /** 217 * @brief Serail flash controller interface mode type definition 218 */ 219 #define SF_CTRL_SPI_MODE 0 /*!< SPI mode define */ 220 #define SF_CTRL_QPI_MODE 1 /*!< QPI mode define */ 221 222 /** 223 * @brief Serail flash controller command mode type definition 224 */ 225 #define SF_CTRL_CMD_1_LINE 0 /*!< Command in one line mode */ 226 #define SF_CTRL_CMD_4_LINES 1 /*!< Command in four lines mode */ 227 228 /** 229 * @brief Serail flash controller address mode type definition 230 */ 231 #define SF_CTRL_ADDR_1_LINE 0 /*!< Address in one line mode */ 232 #define SF_CTRL_ADDR_2_LINES 1 /*!< Address in two lines mode */ 233 #define SF_CTRL_ADDR_4_LINES 2 /*!< Address in four lines mode */ 234 235 /** 236 * @brief Serail flash controller dummy mode type definition 237 */ 238 #define SF_CTRL_DUMMY_1_LINE 0 /*!< Dummy in one line mode */ 239 #define SF_CTRL_DUMMY_2_LINES 1 /*!< Dummy in two lines mode */ 240 #define SF_CTRL_DUMMY_4_LINES 2 /*!< Dummy in four lines mode */ 241 242 /** 243 * @brief Serail flash controller data mode type definition 244 */ 245 #define SF_CTRL_DATA_1_LINE 0 /*!< Data in one line mode */ 246 #define SF_CTRL_DATA_2_LINES 1 /*!< Data in two lines mode */ 247 #define SF_CTRL_DATA_4_LINES 2 /*!< Data in four lines mode */ 248 249 /** 250 * @brief Serail flash controller AES mode type definition 251 */ 252 #define SF_CTRL_AES_CTR_MODE 0 /*!< Serail flash AES CTR mode */ 253 #define SF_CTRL_AES_XTS_MODE 1 /*!< Serail flash AES XTS mode */ 254 255 /** 256 * @brief Serail flash controller AES key len type definition 257 */ 258 #define SF_CTRL_AES_128BITS 0 /*!< Serail flash AES key 128 bits length */ 259 #define SF_CTRL_AES_256BITS 1 /*!< Serail flash AES key 256 bits length */ 260 #define SF_CTRL_AES_192BITS 2 /*!< Serail flash AES key 192 bits length */ 261 #define SF_CTRL_AES_128BITS_DOUBLE_KEY 3 /*!< Serail flash AES key 128 bits length double key */ 262 263 /** 264 * @brief Serail flash controller configuration structure type definition 265 */ 266 struct sf_ctrl_cfg_type { 267 uint8_t owner; /*!< Sflash interface bus owner */ 268 #ifdef BFLB_SF_CTRL_32BITS_ADDR_ENABLE 269 uint8_t en32b_addr; /*!< Sflash enable 32-bits address */ 270 #endif 271 uint8_t clk_delay; /*!< Clock count for read due to pad delay */ 272 uint8_t clk_invert; /*!< Clock invert */ 273 uint8_t rx_clk_invert; /*!< RX clock invert */ 274 uint8_t do_delay; /*!< Data out delay */ 275 uint8_t di_delay; /*!< Data in delay */ 276 uint8_t oe_delay; /*!< Output enable delay */ 277 }; 278 279 #ifdef BFLB_SF_CTRL_SBUS2_ENABLE 280 /** 281 * @brief SF Ctrl bank2 controller configuration structure type definition 282 */ 283 struct sf_ctrl_bank2_cfg { 284 uint8_t sbus2_select; /*!< Select sbus2 as 2nd flash controller */ 285 uint8_t bank2_rx_clk_invert_src; /*!< Select bank2 rx clock invert source */ 286 uint8_t bank2_rx_clk_invert_sel; /*!< Select inveted bank2 rx clock */ 287 uint8_t bank2_delay_src; /*!< Select bank2 read delay source */ 288 uint8_t bank2_clk_delay; /*!< Bank2 read delay cycle = n + 1 */ 289 uint8_t do_delay; /*!< Data out delay */ 290 uint8_t di_delay; /*!< Data in delay */ 291 uint8_t oe_delay; /*!< Output enable delay */ 292 uint8_t remap; /*!< Select dual flash memory remap set */ 293 uint8_t remap_lock; /*!< Select memory remap lock */ 294 }; 295 #endif 296 297 #ifdef BFLB_SF_CTRL_PSRAM_ENABLE 298 /** 299 * @brief SF Ctrl psram controller configuration structure type definition 300 */ 301 struct sf_ctrl_psram_cfg { 302 uint8_t owner; /*!< Psram interface bus owner */ 303 uint8_t pad_sel; /*!< SF Ctrl pad select */ 304 uint8_t bank_sel; /*!< SF Ctrl bank select */ 305 uint8_t psram_rx_clk_invert_src; /*!< Select psram rx clock invert source */ 306 uint8_t psram_rx_clk_invert_sel; /*!< Select inveted psram rx clock */ 307 uint8_t psram_delay_src; /*!< Select psram read delay source */ 308 uint8_t psram_clk_delay; /*!< Psram read delay cycle = n + 1 */ 309 } ; 310 #endif 311 312 /** 313 * @brief SF Ctrl cmds configuration structure type definition 314 */ 315 struct sf_ctrl_cmds_cfg { 316 uint8_t ack_latency; /*!< SF Ctrl ack latency cycles */ 317 uint8_t cmds_core_en; /*!< SF Ctrl cmds core enable */ 318 #if defined(BL702) 319 uint8_t burst_toggle_en; /*!< SF Ctrl burst toggle mode enable */ 320 #endif 321 uint8_t cmds_en; /*!< SF Ctrl cmds enable */ 322 uint8_t cmds_wrap_mode; /*!< SF Ctrl cmds wrap mode */ 323 uint8_t cmds_wrap_len; /*!< SF Ctrl cmds wrap length */ 324 }; 325 326 /** 327 * @brief Serail flash command configuration structure type definition 328 */ 329 struct sf_ctrl_cmd_cfg_type { 330 uint8_t rw_flag; /*!< Read write flag */ 331 uint8_t cmd_mode; /*!< Command mode */ 332 uint8_t addr_mode; /*!< Address mode */ 333 uint8_t addr_size; /*!< Address size */ 334 uint8_t dummy_clks; /*!< Dummy clocks */ 335 uint8_t dummy_mode; /*!< Dummy mode */ 336 uint8_t data_mode; /*!< Data mode */ 337 uint8_t rsv[1]; /*!< Reserved */ 338 uint32_t nb_data; /*!< Transfer number of bytes */ 339 uint32_t cmd_buf[2]; /*!< Command buffer */ 340 }; 341 342 /*@} end of group SF_CTRL_Public_Types */ 343 344 /** @defgroup SF_CTRL_Public_Macros 345 * @{ 346 */ 347 #if defined(BL602) || defined(BL702) || defined(BL702L) 348 #define SF_CTRL_BUSY_STATE_TIMEOUT (5 * 160 * 1000) 349 #else 350 #define SF_CTRL_BUSY_STATE_TIMEOUT (5 * 320 * 1000) 351 #endif 352 #define SF_CTRL_NO_ADDRESS 0xFFFFFFFF 353 #define NOR_FLASH_CTRL_BUF_SIZE 256 354 #define NAND_FLASH_CTRL_BUF_SIZE 512 355 356 #if defined(BL628) || defined(BL616) 357 #define IS_SF_CTRL_PIN_SELECT(type) (((type) == SF_IO_EMB_SWAP_IO3IO0) || \ 358 ((type) == SF_IO_EMB_SWAP_IO3IO0_IO2CS) || \ 359 ((type) == SF_IO_EMB_SWAP_NONE) || \ 360 ((type) == SF_IO_EMB_SWAP_IO2CS) || \ 361 ((type) == SF_IO_EXT_SF2_SWAP_IO3IO0) || \ 362 ((type) == SF_IO_EXT_SF3) || \ 363 ((type) == SF_IO_EMB_SWAP_IO3IO0_AND_SF2_SWAP_IO3IO0) || \ 364 ((type) == SF_IO_EMB_SWAP_IO3IO0_IO2CS_AND_SF2_SWAP_IO3IO0) || \ 365 ((type) == SF_IO_EMB_SWAP_NONE_AND_SF2_SWAP_IO3IO0) || \ 366 ((type) == SF_IO_EMB_SWAP_IO2CS_AND_SF2_SWAP_IO3IO0) || \ 367 ((type) == SF_IO_EXT_SF2) || \ 368 ((type) == SF_IO_EMB_SWAP_IO3IO0_AND_SF2) || \ 369 ((type) == SF_IO_EMB_SWAP_IO3IO0_IO2CS_AND_SF2) || \ 370 ((type) == SF_IO_EMB_SWAP_NONE_AND_SF2) || \ 371 ((type) == SF_IO_EMB_SWAP_IO2CS_AND_SF2)) 372 #elif defined(BL808) || defined(BL606P) 373 #define IS_SF_CTRL_PIN_SELECT(type) (((type) == SF_IO_EMB_SWAP_IO0_IO3) || \ 374 ((type) == SF_IO_EMB_SWAP_DUAL_IO0_IO3) || \ 375 ((type) == SF_IO_EMB_SWAP_NONE) || \ 376 ((type) == SF_IO_EMB_SWAP_NONE_DUAL_IO0) || \ 377 ((type) == SF_IO_EXT_SF2) || \ 378 ((type) == SF_IO_EMB_SWAP_IO0_IO3_AND_EXT_SF2) || \ 379 ((type) == SF_IO_EMB_SWAP_DUAL_IO0_IO3_AND_EXT_SF2) || \ 380 ((type) == SF_IO_EMB_SWAP_NONE_AND_EXT_SF2) || \ 381 ((type) == SF_IO_EMB_SWAP_NONE_DUAL_IO0_AND_EXT_SF2)) 382 #elif defined(BL702L) 383 #define IS_SF_CTRL_PIN_SELECT(type) (((type) == SF_CTRL_SEL_EXTERNAL_FLASH) || \ 384 ((type) == SF_CTRL_SEL_INTERNAL_FLASH_SWAP_NONE) || \ 385 ((type) == SF_CTRL_SEL_INTERNAL_FLASH_SWAP_CSIO2) || \ 386 ((type) == SF_CTRL_SEL_INTERNAL_FLASH_SWAP_IO0IO3) || \ 387 ((type) == SF_CTRL_SEL_INTERNAL_FLASH_SWAP_BOTH) || \ 388 ((type) == SF_CTRL_SEL_INTERNAL_FLASH_REVERSE_SWAP_NONE) || \ 389 ((type) == SF_CTRL_SEL_INTERNAL_FLASH_REVERSE_SWAP_CSIO2) || \ 390 ((type) == SF_CTRL_SEL_INTERNAL_FLASH_REVERSE_SWAP_IO0IO3) || \ 391 ((type) == SF_CTRL_SEL_INTERNAL_FLASH_REVERSE_SWAP_BOTH)) 392 #elif defined(BL702) 393 #define IS_SF_CTRL_PIN_SELECT(type) (((type) == SF_CTRL_SEL_SF1) || \ 394 ((type) == SF_CTRL_SEL_SF2) || \ 395 ((type) == SF_CTRL_SEL_SF3) || \ 396 ((type) == SF_CTRL_SEL_DUAL_BANK_SF1_SF2) || \ 397 ((type) == SF_CTRL_SEL_DUAL_BANK_SF2_SF3) || \ 398 ((type) == SF_CTRL_SEL_DUAL_BANK_SF3_SF1) || \ 399 ((type) == SF_CTRL_SEL_DUAL_CS_SF2) || \ 400 ((type) == SF_CTRL_SEL_DUAL_CS_SF3)) 401 #elif defined(BL602) 402 #define IS_SF_CTRL_PIN_SELECT(type) (((type) == SF_CTRL_EMBEDDED_SEL) || \ 403 ((type) == SF_CTRL_EXTERNAL_17TO22_SEL) || \ 404 ((type) == SF_CTRL_EXTERNAL_0TO2_20TO22_SEL)) 405 #endif 406 407 /*@} end of group SF_CTRL_Public_Macros */ 408 409 /** @defgroup SF_CTRL_Public_Functions 410 * @{ 411 */ 412 void bflb_sf_ctrl_enable(const struct sf_ctrl_cfg_type *cfg); 413 void bflb_sf_ctrl_set_io_delay(uint8_t pad, uint8_t dodelay, uint8_t didelay, uint8_t oedelay); 414 #ifdef BFLB_SF_CTRL_SBUS2_ENABLE 415 void bflb_sf_ctrl_bank2_enable(const struct sf_ctrl_bank2_cfg *bank2cfg); 416 void bflb_sf_ctrl_sbus2_hold_sram(void); 417 void bflb_sf_ctrl_sbus2_release_sram(void); 418 uint8_t sf_ctrl_is_sbus2_enable(void); 419 void bflb_sf_ctrl_sbus2_replace(uint8_t pad); 420 void bflb_sf_ctrl_sbus2_revoke_replace(void); 421 void bflb_sf_ctrl_sbus2_set_delay(uint8_t clk_delay, uint8_t rx_clk_invert); 422 void bflb_sf_ctrl_remap_set(uint8_t remap, uint8_t lock); 423 #endif 424 #ifdef BFLB_SF_CTRL_32BITS_ADDR_ENABLE 425 void bflb_sf_ctrl_32bits_addr_en(uint8_t en_32bit_saddr); 426 #endif 427 #ifdef BFLB_SF_CTRL_PSRAM_ENABLE 428 void bflb_sf_ctrl_psram_init(struct sf_ctrl_psram_cfg *psram_cfg); 429 #endif 430 uint8_t bflb_sf_ctrl_get_clock_delay(void); 431 void bflb_sf_ctrl_set_clock_delay(uint8_t delay); 432 uint8_t bflb_sf_ctrl_get_wrap_queue_value(void); 433 void bflb_sf_ctrl_cmds_set(struct sf_ctrl_cmds_cfg *cmds_cfg, uint8_t sel); 434 #if defined(BL702L) 435 void bflb_sf_ctrl_burst_toggle_set(uint8_t burst_toggle_en, uint8_t mode); 436 #endif 437 void bflb_sf_ctrl_select_pad(uint8_t sel); 438 void bflb_sf_ctrl_sbus_select_bank(uint8_t bank); 439 void bflb_sf_ctrl_set_owner(uint8_t owner); 440 void bflb_sf_ctrl_disable(void); 441 void bflb_sf_ctrl_aes_enable_be(void); 442 void bflb_sf_ctrl_aes_enable_le(void); 443 void bflb_sf_ctrl_aes_set_region(uint8_t region, uint8_t enable, uint8_t hwkey, 444 uint32_t start_addr, uint32_t end_addr, uint8_t locked); 445 void bflb_sf_ctrl_aes_set_key(uint8_t region, uint8_t *key, uint8_t key_type); 446 void bflb_sf_ctrl_aes_set_key_be(uint8_t region, uint8_t *key, uint8_t key_type); 447 void bflb_sf_ctrl_aes_set_iv(uint8_t region, uint8_t *iv, uint32_t addr_offset); 448 void bflb_sf_ctrl_aes_set_iv_be(uint8_t region, uint8_t *iv, uint32_t addr_offset); 449 #ifdef BFLB_SF_CTRL_AES_XTS_ENABLE 450 void bflb_sf_ctrl_aes_xts_set_key(uint8_t region, uint8_t *key, uint8_t key_type); 451 void bflb_sf_ctrl_aes_xts_set_key_be(uint8_t region, uint8_t *key, uint8_t key_type); 452 void bflb_sf_ctrl_aes_xts_set_iv(uint8_t region, uint8_t *iv, uint32_t addr_offset); 453 void bflb_sf_ctrl_aes_xts_set_iv_be(uint8_t region, uint8_t *iv, uint32_t addr_offset); 454 #endif 455 void bflb_sf_ctrl_aes_set_mode(uint8_t mode); 456 void bflb_sf_ctrl_aes_enable(void); 457 void bflb_sf_ctrl_aes_disable(void); 458 uint8_t bflb_sf_ctrl_is_aes_enable(void); 459 void bflb_sf_ctrl_set_flash_image_offset(uint32_t addr_offset, uint8_t group, uint8_t bank); 460 uint32_t bflb_sf_ctrl_get_flash_image_offset(uint8_t group, uint8_t bank); 461 void bflb_sf_ctrl_lock_flash_image_offset(uint8_t lock); 462 void bflb_sf_ctrl_select_clock(uint8_t sahb_sram_sel); 463 void bflb_sf_ctrl_sendcmd(struct sf_ctrl_cmd_cfg_type *cfg); 464 void bflb_sf_ctrl_disable_wrap_access(uint8_t disable); 465 void bflb_sf_ctrl_xip_set(struct sf_ctrl_cmd_cfg_type *cfg, uint8_t cmd_valid); 466 #ifdef BFLB_SF_CTRL_SBUS2_ENABLE 467 void bflb_sf_ctrl_xip2_set(struct sf_ctrl_cmd_cfg_type *cfg, uint8_t cmd_valid); 468 #endif 469 #ifdef BFLB_SF_CTRL_PSRAM_ENABLE 470 void bflb_sf_ctrl_psram_write_set(struct sf_ctrl_cmd_cfg_type *cfg, uint8_t cmd_valid); 471 void bflb_sf_ctrl_psram_read_set(struct sf_ctrl_cmd_cfg_type *cfg, uint8_t cmd_valid); 472 #endif 473 uint8_t bflb_sf_ctrl_get_busy_state(void); 474 #ifndef BFLB_USE_HAL_DRIVER 475 void bflb_sf_ctrl_irqhandler(void); 476 #endif 477 478 /*@} end of group SF_CTRL_Public_Functions */ 479 480 /*@} end of group SF_CTRL */ 481 482 /*@} end of group BL628_Peripheral_Driver */ 483 484 #endif /* __BL628_SF_CTRL_H__ */ 485