1/*
2 * Copyright (c) 2020-2020, BLUETRUM Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include "ab32vg1.h"
8
9.global _start
10.section .reset, "ax"
11_start:
12    la      tp, _tp
13    la      gp, _gp
14
15    //load comm
16    la      a0, __comm_vma
17    la      a1, __comm_lma
18    la      a2, __comm_size
19    call    _memcpy
20
21    //load ram1
22    la      a0, __ram1_vma
23    la      a1, __ram1_lma
24    la      a2, __ram1_size
25    call    _memcpy
26
27    la      a0, __irq_stack_start           //Stack清成0x23
28    li      a1, 0x23
29    la      a2, __irq_stack_size
30    call    rt_memset
31    la      ra, __irq_stack
32    lui	    a5, 0x1
33    sw	    zero, -1920(a5)
34    sw	    zero, -1916(a5)
35
36    //clear bss
37    la      a0, __bss_start
38    li      a1, 0
39    la      a2, __bss_size
40    call    rt_memset
41
42    call    cache_init
43
44    la      a0, __comm_vma
45    sw      a0, PICADR(zero)
46
47    call    entry
48    la      ra, __exception
49    jr      ra
50
51.section .vector, "ax"
52    .org    0x10
53__exception:
54    li      sp, 0x10600                     //出错后，不破坏错误点的堆栈数据
55    jal     exception_isr
56    1: j       1b
57    mret
58
59    .org    0x40
60    jal x0, low_prio_irq
61
62    .org    0x80
63#define METHOD 1
64#if METHOD == 1
65    addi    sp, sp, -6*4
66    # lw      a0, PICEN(zero)
67    lw      a1, EPC(zero)
68    lw      a2, EPICCON(zero)
69    # sw      a0, 3*4(sp)
70    sw      a1, 4*4(sp)
71    sw      a2, 5*4(sp)
72    # andi    a0, a0, 1
73    # sw      a0, PICEN(zero)
74    li      a2, 0
75    sw      a2, EPICCON(zero)
76    la      a0, 0f
77    sw      a0, EPC(zero)
78    j       isr_cache
790:
80    sw      a0, 0(sp)
81    sw      a1, 4(sp)
82    sw      a2, 8(sp)
83
84    # lw      a0, 3*4(sp)
85    lw      a1, 4*4(sp)
86    lw      a2, 5*4(sp)
87    # sw      a0, PICEN(zero)
88    sw      a1, EPC(zero)
89    sw      a2, EPICCON(zero)
90
91    lw      a0, 0(sp)
92    lw      a1, 4(sp)
93    lw      a2, 8(sp)
94    addi    sp, sp, 6*4
95    mret
96#endif
97
98    .org    0x1e0
99    1: j       1b
100    nop
101    mret
102
103    .global cpu_irq_comm
104cpu_irq_comm:
105    la      a5, __irq_stack
106    mv      sp, a5
107    j       cpu_irq_comm_do
108
109    ret
110
111    .global _tp
112    .set    _tp,        0x84800
113
114    .set    _memcpy,    0x84044