1 /*!
2 \file gd32vf103_adc.c
3 \brief ADC driver
4
5 \version 2020-06-05, V1.0.0, firmware for GD32VF103
6 \version 2020-08-04, V1.1.0, firmware for GD32VF103
7 */
8
9 /*
10 Copyright (c) 2020, GigaDevice Semiconductor Inc.
11
12 Redistribution and use in source and binary forms, with or without modification,
13 are permitted provided that the following conditions are met:
14
15 1. Redistributions of source code must retain the above copyright notice, this
16 list of conditions and the following disclaimer.
17 2. Redistributions in binary form must reproduce the above copyright notice,
18 this list of conditions and the following disclaimer in the documentation
19 and/or other materials provided with the distribution.
20 3. Neither the name of the copyright holder nor the names of its contributors
21 may be used to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
26 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
27 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
28 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
29 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
30 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
31 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
33 OF SUCH DAMAGE.
34 */
35
36 #include "gd32vf103_adc.h"
37
38 /* discontinuous mode macro*/
39 #define ADC_CHANNEL_LENGTH_SUBTRACT_ONE ((uint8_t)1U)
40
41 /* ADC regular channel macro */
42 #define ADC_REGULAR_CHANNEL_RANK_SIX ((uint8_t)6U)
43 #define ADC_REGULAR_CHANNEL_RANK_TWELVE ((uint8_t)12U)
44 #define ADC_REGULAR_CHANNEL_RANK_SIXTEEN ((uint8_t)16U)
45 #define ADC_REGULAR_CHANNEL_RANK_LENGTH ((uint8_t)5U)
46
47 /* ADC sampling time macro */
48 #define ADC_CHANNEL_SAMPLE_TEN ((uint8_t)10U)
49 #define ADC_CHANNEL_SAMPLE_EIGHTEEN ((uint8_t)18U)
50 #define ADC_CHANNEL_SAMPLE_LENGTH ((uint8_t)3U)
51
52 /* ADC inserted channel macro */
53 #define ADC_INSERTED_CHANNEL_RANK_LENGTH ((uint8_t)5U)
54 #define ADC_INSERTED_CHANNEL_SHIFT_LENGTH ((uint8_t)15U)
55
56 /* ADC inserted channel offset macro */
57 #define ADC_OFFSET_LENGTH ((uint8_t)3U)
58 #define ADC_OFFSET_SHIFT_LENGTH ((uint8_t)4U)
59
60 /*!
61 \brief reset ADC
62 \param[in] adc_periph: ADCx, x=0,1
63 \param[out] none
64 \retval none
65 */
adc_deinit(uint32_t adc_periph)66 void adc_deinit(uint32_t adc_periph)
67 {
68 switch(adc_periph){
69 case ADC0:
70 /* reset ADC0 */
71 rcu_periph_reset_enable(RCU_ADC0RST);
72 rcu_periph_reset_disable(RCU_ADC0RST);
73 break;
74 case ADC1:
75 /* reset ADC1 */
76 rcu_periph_reset_enable(RCU_ADC1RST);
77 rcu_periph_reset_disable(RCU_ADC1RST);
78 break;
79 default:
80 break;
81 }
82 }
83
84 /*!
85 \brief configure the ADC sync mode
86 \param[in] mode: ADC mode
87 only one parameter can be selected which is shown as below:
88 \arg ADC_MODE_FREE: all the ADCs work independently
89 \arg ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL: ADC0 and ADC1 work in combined regular parallel + inserted parallel mode
90 \arg ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION: ADC0 and ADC1 work in combined regular parallel + trigger rotation mode
91 \arg ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_FAST: ADC0 and ADC1 work in combined inserted parallel + follow-up fast mode
92 \arg ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_SLOW: ADC0 and ADC1 work in combined inserted parallel + follow-up slow mode
93 \arg ADC_DAUL_INSERTED_PARALLEL: ADC0 and ADC1 work in inserted parallel mode only
94 \arg ADC_DAUL_REGULAL_PARALLEL: ADC0 and ADC1 work in regular parallel mode only
95 \arg ADC_DAUL_REGULAL_FOLLOWUP_FAST: ADC0 and ADC1 work in follow-up fast mode only
96 \arg ADC_DAUL_REGULAL_FOLLOWUP_SLOW: ADC0 and ADC1 work in follow-up slow mode only
97 \arg ADC_DAUL_INSERTED_TRIGGER_ROTATION: ADC0 and ADC1 work in trigger rotation mode only
98 \param[out] none
99 \retval none
100 */
adc_mode_config(uint32_t mode)101 void adc_mode_config(uint32_t mode)
102 {
103 ADC_CTL0(ADC0) &= ~(ADC_CTL0_SYNCM);
104 ADC_CTL0(ADC0) |= mode;
105 }
106
107 /*!
108 \brief enable or disable ADC special function
109 \param[in] adc_periph: ADCx, x=0,1
110 \param[in] function: the function to config
111 only one parameter can be selected which is shown as below:
112 \arg ADC_SCAN_MODE: scan mode select
113 \arg ADC_INSERTED_CHANNEL_AUTO: inserted channel group convert automatically
114 \arg ADC_CONTINUOUS_MODE: continuous mode select
115 \param[in] newvalue: ENABLE or DISABLE
116 \param[out] none
117 \retval none
118 */
adc_special_function_config(uint32_t adc_periph,uint32_t function,ControlStatus newvalue)119 void adc_special_function_config(uint32_t adc_periph, uint32_t function, ControlStatus newvalue)
120 {
121 if(newvalue){
122 if(0U != (function & ADC_SCAN_MODE)){
123 /* enable scan mode */
124 ADC_CTL0(adc_periph) |= ADC_SCAN_MODE;
125 }
126 if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)){
127 /* enable inserted channel group convert automatically */
128 ADC_CTL0(adc_periph) |= ADC_INSERTED_CHANNEL_AUTO;
129 }
130 if(0U != (function & ADC_CONTINUOUS_MODE)){
131 /* enable continuous mode */
132 ADC_CTL1(adc_periph) |= ADC_CONTINUOUS_MODE;
133 }
134 }else{
135 if(0U != (function & ADC_SCAN_MODE)){
136 /* disable scan mode */
137 ADC_CTL0(adc_periph) &= ~ADC_SCAN_MODE;
138 }
139 if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)){
140 /* disable inserted channel group convert automatically */
141 ADC_CTL0(adc_periph) &= ~ADC_INSERTED_CHANNEL_AUTO;
142 }
143 if(0U != (function & ADC_CONTINUOUS_MODE)){
144 /* disable continuous mode */
145 ADC_CTL1(adc_periph) &= ~ADC_CONTINUOUS_MODE;
146 }
147 }
148 }
149
150 /*!
151 \brief configure ADC data alignment
152 \param[in] adc_periph: ADCx, x=0,1
153 \param[in] data_alignment: data alignment select
154 only one parameter can be selected which is shown as below:
155 \arg ADC_DATAALIGN_RIGHT: LSB alignment
156 \arg ADC_DATAALIGN_LEFT: MSB alignment
157 \param[out] none
158 \retval none
159 */
adc_data_alignment_config(uint32_t adc_periph,uint32_t data_alignment)160 void adc_data_alignment_config(uint32_t adc_periph, uint32_t data_alignment)
161 {
162 if(ADC_DATAALIGN_RIGHT != data_alignment){
163 /* MSB alignment */
164 ADC_CTL1(adc_periph) |= ADC_CTL1_DAL;
165 }else{
166 /* LSB alignment */
167 ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DAL);
168 }
169 }
170
171 /*!
172 \brief enable ADC interface
173 \param[in] adc_periph: ADCx, x=0,1
174 \param[out] none
175 \retval none
176 */
adc_enable(uint32_t adc_periph)177 void adc_enable(uint32_t adc_periph)
178 {
179 if((uint32_t)RESET == (ADC_CTL1(adc_periph) & ADC_CTL1_ADCON)){
180 /* enable ADC */
181 ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_ADCON;
182 }
183 }
184
185 /*!
186 \brief disable ADC interface
187 \param[in] adc_periph: ADCx, x=0,1
188 \param[out] none
189 \retval none
190 */
adc_disable(uint32_t adc_periph)191 void adc_disable(uint32_t adc_periph)
192 {
193 /* disable ADC */
194 ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ADCON);
195 }
196
197 /*!
198 \brief ADC calibration and reset calibration
199 \param[in] adc_periph: ADCx, x=0,1
200 \param[out] none
201 \retval none
202 */
adc_calibration_enable(uint32_t adc_periph)203 void adc_calibration_enable(uint32_t adc_periph)
204 {
205 /* reset the selected ADC1 calibration registers */
206 ADC_CTL1(adc_periph) |= (uint32_t) ADC_CTL1_RSTCLB;
207 /* check the RSTCLB bit state */
208 while((uint32_t)RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_RSTCLB)){
209 }
210 /* enable ADC calibration process */
211 ADC_CTL1(adc_periph) |= ADC_CTL1_CLB;
212 /* check the CLB bit state */
213 while((uint32_t)RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_CLB)){
214 }
215 }
216
217 /*!
218 \brief enable the temperature sensor and Vrefint channel
219 \param[in] none
220 \param[out] none
221 \retval none
222 */
adc_tempsensor_vrefint_enable(void)223 void adc_tempsensor_vrefint_enable(void)
224 {
225 /* enable the temperature sensor and Vrefint channel */
226 ADC_CTL1(ADC0) |= ADC_CTL1_TSVREN;
227 }
228
229 /*!
230 \brief disable the temperature sensor and Vrefint channel
231 \param[in] none
232 \param[out] none
233 \retval none
234 */
adc_tempsensor_vrefint_disable(void)235 void adc_tempsensor_vrefint_disable(void)
236 {
237 /* disable the temperature sensor and Vrefint channel */
238 ADC_CTL1(ADC0) &= ~ADC_CTL1_TSVREN;
239 }
240
241 /*!
242 \brief enable DMA request
243 \param[in] adc_periph: ADCx, x=0,1
244 \param[out] none
245 \retval none
246 */
adc_dma_mode_enable(uint32_t adc_periph)247 void adc_dma_mode_enable(uint32_t adc_periph)
248 {
249 /* enable DMA request */
250 ADC_CTL1(adc_periph) |= (uint32_t)(ADC_CTL1_DMA);
251 }
252
253 /*!
254 \brief disable DMA request
255 \param[in] adc_periph: ADCx, x=0,1
256 \param[out] none
257 \retval none
258 */
adc_dma_mode_disable(uint32_t adc_periph)259 void adc_dma_mode_disable(uint32_t adc_periph)
260 {
261 /* disable DMA request */
262 ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DMA);
263 }
264
265 /*!
266 \brief configure ADC discontinuous mode
267 \param[in] adc_periph: ADCx, x=0,1
268 \param[in] adc_channel_group: select the channel group
269 only one parameter can be selected which is shown as below:
270 \arg ADC_REGULAR_CHANNEL: regular channel group
271 \arg ADC_INSERTED_CHANNEL: inserted channel group
272 \arg ADC_CHANNEL_DISCON_DISABLE: disable discontinuous mode of regular & inserted channel
273 \param[in] length: number of conversions in discontinuous mode,the number can be 1..8
274 for regular channel, the number has no effect for inserted channel
275 \param[out] none
276 \retval none
277 */
adc_discontinuous_mode_config(uint32_t adc_periph,uint8_t adc_channel_group,uint8_t length)278 void adc_discontinuous_mode_config(uint32_t adc_periph, uint8_t adc_channel_group, uint8_t length)
279 {
280 /* disable discontinuous mode of regular & inserted channel */
281 ADC_CTL0(adc_periph) &= ~((uint32_t)(ADC_CTL0_DISRC | ADC_CTL0_DISIC));
282 switch(adc_channel_group){
283 case ADC_REGULAR_CHANNEL:
284 /* config the number of conversions in discontinuous mode */
285 ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_DISNUM);
286 ADC_CTL0(adc_periph) |= CTL0_DISNUM(((uint32_t)length - ADC_CHANNEL_LENGTH_SUBTRACT_ONE));
287 /* enable regular channel group discontinuous mode */
288 ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISRC;
289 break;
290 case ADC_INSERTED_CHANNEL:
291 /* enable inserted channel group discontinuous mode */
292 ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISIC;
293 break;
294 case ADC_CHANNEL_DISCON_DISABLE:
295 /* disable discontinuous mode of regular & inserted channel */
296 default:
297 break;
298 }
299 }
300
301 /*!
302 \brief configure the length of regular channel group or inserted channel group
303 \param[in] adc_periph: ADCx, x=0,1
304 \param[in] adc_channel_group: select the channel group
305 only one parameter can be selected which is shown as below:
306 \arg ADC_REGULAR_CHANNEL: regular channel group
307 \arg ADC_INSERTED_CHANNEL: inserted channel group
308 \param[in] length: the length of the channel
309 regular channel 1-16
310 inserted channel 1-4
311 \param[out] none
312 \retval none
313 */
adc_channel_length_config(uint32_t adc_periph,uint8_t adc_channel_group,uint32_t length)314 void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t length)
315 {
316 switch(adc_channel_group){
317 case ADC_REGULAR_CHANNEL:
318 /* configure the length of regular channel group */
319 ADC_RSQ0(adc_periph) &= ~((uint32_t)ADC_RSQ0_RL);
320 ADC_RSQ0(adc_periph) |= RSQ0_RL((uint32_t)(length-ADC_CHANNEL_LENGTH_SUBTRACT_ONE));
321 break;
322 case ADC_INSERTED_CHANNEL:
323 /* configure the length of inserted channel group */
324 ADC_ISQ(adc_periph) &= ~((uint32_t)ADC_ISQ_IL);
325 ADC_ISQ(adc_periph) |= ISQ_IL((uint32_t)(length-ADC_CHANNEL_LENGTH_SUBTRACT_ONE));
326 break;
327 default:
328 break;
329 }
330 }
331
332 /*!
333 \brief configure ADC regular channel
334 \param[in] adc_periph: ADCx, x=0,1
335 \param[in] rank: the regular group sequence rank,this parameter must be between 0 to 15
336 \param[in] adc_channel: the selected ADC channel
337 only one parameter can be selected which is shown as below:
338 \arg ADC_CHANNEL_x(x=0..17)(x=16 and x=17 are only for ADC0): ADC Channelx
339 \param[in] sample_time: the sample time value
340 only one parameter can be selected which is shown as below:
341 \arg ADC_SAMPLETIME_1POINT5: 1.5 cycles
342 \arg ADC_SAMPLETIME_7POINT5: 7.5 cycles
343 \arg ADC_SAMPLETIME_13POINT5: 13.5 cycles
344 \arg ADC_SAMPLETIME_28POINT5: 28.5 cycles
345 \arg ADC_SAMPLETIME_41POINT5: 41.5 cycles
346 \arg ADC_SAMPLETIME_55POINT5: 55.5 cycles
347 \arg ADC_SAMPLETIME_71POINT5: 71.5 cycles
348 \arg ADC_SAMPLETIME_239POINT5: 239.5 cycles
349 \param[out] none
350 \retval none
351 */
adc_regular_channel_config(uint32_t adc_periph,uint8_t rank,uint8_t adc_channel,uint32_t sample_time)352 void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time)
353 {
354 uint32_t rsq,sampt;
355
356 /* ADC regular sequence config */
357 if(rank < ADC_REGULAR_CHANNEL_RANK_SIX){
358 /* the regular group sequence rank is smaller than six */
359 rsq = ADC_RSQ2(adc_periph);
360 rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH*rank)));
361 /* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */
362 rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH*rank));
363 ADC_RSQ2(adc_periph) = rsq;
364 }else if(rank < ADC_REGULAR_CHANNEL_RANK_TWELVE){
365 /* the regular group sequence rank is smaller than twelve */
366 rsq = ADC_RSQ1(adc_periph);
367 rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_SIX))));
368 /* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */
369 rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_SIX)));
370 ADC_RSQ1(adc_periph) = rsq;
371 }else if(rank < ADC_REGULAR_CHANNEL_RANK_SIXTEEN){
372 /* the regular group sequence rank is smaller than sixteen */
373 rsq = ADC_RSQ0(adc_periph);
374 rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_TWELVE))));
375 /* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */
376 rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_TWELVE)));
377 ADC_RSQ0(adc_periph) = rsq;
378 }else{
379 }
380
381 /* ADC sampling time config */
382 if(adc_channel < ADC_CHANNEL_SAMPLE_TEN){
383 /* the regular group sequence rank is smaller than ten */
384 sampt = ADC_SAMPT1(adc_periph);
385 sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel)));
386 /* channel sample time set*/
387 sampt |= (uint32_t)(sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel));
388 ADC_SAMPT1(adc_periph) = sampt;
389 }else if(adc_channel < ADC_CHANNEL_SAMPLE_EIGHTEEN){
390 /* the regular group sequence rank is smaller than eighteen */
391 sampt = ADC_SAMPT0(adc_periph);
392 sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel-ADC_CHANNEL_SAMPLE_TEN))));
393 /* channel sample time set*/
394 sampt |= (uint32_t)(sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel-ADC_CHANNEL_SAMPLE_TEN)));
395 ADC_SAMPT0(adc_periph) = sampt;
396 }else{
397 }
398 }
399
400 /*!
401 \brief configure ADC inserted channel
402 \param[in] adc_periph: ADCx, x=0,1
403 \param[in] rank: the inserted group sequencer rank,this parameter must be between 0 to 3
404 \param[in] adc_channel: the selected ADC channel
405 only one parameter can be selected which is shown as below:
406 \arg ADC_CHANNEL_x(x=0..17)(x=16 and x=17 are only for ADC0): ADC Channelx
407 \param[in] sample_time: The sample time value
408 only one parameter can be selected which is shown as below:
409 \arg ADC_SAMPLETIME_1POINT5: 1.5 cycles
410 \arg ADC_SAMPLETIME_7POINT5: 7.5 cycles
411 \arg ADC_SAMPLETIME_13POINT5: 13.5 cycles
412 \arg ADC_SAMPLETIME_28POINT5: 28.5 cycles
413 \arg ADC_SAMPLETIME_41POINT5: 41.5 cycles
414 \arg ADC_SAMPLETIME_55POINT5: 55.5 cycles
415 \arg ADC_SAMPLETIME_71POINT5: 71.5 cycles
416 \arg ADC_SAMPLETIME_239POINT5: 239.5 cycles
417 \param[out] none
418 \retval none
419 */
adc_inserted_channel_config(uint32_t adc_periph,uint8_t rank,uint8_t adc_channel,uint32_t sample_time)420 void adc_inserted_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time)
421 {
422 uint8_t inserted_length;
423 uint32_t isq,sampt;
424 /* get inserted channel group length */
425 inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph) , 20U , 21U);
426 /* the channel number is written to these bits to select a channel as the nth conversion in the inserted channel group */
427 isq = ADC_ISQ(adc_periph);
428 isq &= ~((uint32_t)(ADC_ISQ_ISQN << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH-(inserted_length-rank)*ADC_INSERTED_CHANNEL_RANK_LENGTH)));
429 isq |= ((uint32_t)adc_channel << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH-(inserted_length-rank)*ADC_INSERTED_CHANNEL_RANK_LENGTH));
430 ADC_ISQ(adc_periph) = isq;
431
432 /* ADC sampling time config */
433 if(adc_channel < ADC_CHANNEL_SAMPLE_TEN){
434 /* the inserted group sequence rank is smaller than ten */
435 sampt = ADC_SAMPT1(adc_periph);
436 sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel)));
437 /* channel sample time set*/
438 sampt |= (uint32_t) sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel);
439 ADC_SAMPT1(adc_periph) = sampt;
440 }else if(adc_channel < ADC_CHANNEL_SAMPLE_EIGHTEEN){
441 /* the inserted group sequence rank is smaller than eighteen */
442 sampt = ADC_SAMPT0(adc_periph);
443 sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel-ADC_CHANNEL_SAMPLE_TEN))));
444 /* channel sample time set*/
445 sampt |= ((uint32_t)sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel-ADC_CHANNEL_SAMPLE_TEN)));
446 ADC_SAMPT0(adc_periph) = sampt;
447 }else{
448 }
449 }
450
451 /*!
452 \brief configure ADC inserted channel offset
453 \param[in] adc_periph: ADCx, x=0,1
454 \param[in] inserted_channel: insert channel select
455 only one parameter can be selected
456 \arg ADC_INSERTED_CHANNEL_0: inserted channel0
457 \arg ADC_INSERTED_CHANNEL_1: inserted channel1
458 \arg ADC_INSERTED_CHANNEL_2: inserted channel2
459 \arg ADC_INSERTED_CHANNEL_3: inserted channel3
460 \param[in] offset: the offset data
461 \param[out] none
462 \retval none
463 */
adc_inserted_channel_offset_config(uint32_t adc_periph,uint8_t inserted_channel,uint16_t offset)464 void adc_inserted_channel_offset_config(uint32_t adc_periph, uint8_t inserted_channel, uint16_t offset)
465 {
466 uint8_t inserted_length;
467 uint32_t num = 0U;
468
469 inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph) , 20U , 21U);
470 num = ((uint32_t)ADC_OFFSET_LENGTH - ((uint32_t)inserted_length - (uint32_t)inserted_channel));
471
472 if(num <= ADC_OFFSET_LENGTH){
473 /* calculate the offset of the register */
474 num = num * ADC_OFFSET_SHIFT_LENGTH;
475 /* config the offset of the selected channels */
476 REG32((adc_periph) + 0x14U + num) = IOFFX_IOFF((uint32_t)offset);
477 }
478 }
479
480 /*!
481 \brief configure ADC external trigger source
482 \param[in] adc_periph: ADCx, x=0,1
483 \param[in] adc_channel_group: select the channel group
484 only one parameter can be selected which is shown as below:
485 \arg ADC_REGULAR_CHANNEL: regular channel group
486 \arg ADC_INSERTED_CHANNEL: inserted channel group
487 \param[in] external_trigger_source: regular or inserted group trigger source
488 only one parameter can be selected
489 for regular channel:
490 \arg ADC0_1_EXTTRIG_REGULAR_T0_CH0: TIMER0 CH0 event select
491 \arg ADC0_1_EXTTRIG_REGULAR_T0_CH1: TIMER0 CH1 event select
492 \arg ADC0_1_EXTTRIG_REGULAR_T0_CH2: TIMER0 CH2 event select
493 \arg ADC0_1_EXTTRIG_REGULAR_T1_CH1: TIMER1 CH1 event select
494 \arg ADC0_1_EXTTRIG_REGULAR_T2_TRGO: TIMER2 TRGO event select
495 \arg ADC0_1_EXTTRIG_REGULAR_T3_CH3: TIMER3 CH3 event select
496 \arg ADC0_1_EXTTRIG_REGULAR_EXTI_11: external interrupt line 11
497 \arg ADC0_1_EXTTRIG_REGULAR_NONE: software trigger
498 for inserted channel:
499 \arg ADC0_1_EXTTRIG_INSERTED_T0_TRGO: TIMER0 TRGO event select
500 \arg ADC0_1_EXTTRIG_INSERTED_T0_CH3: TIMER0 CH3 event select
501 \arg ADC0_1_EXTTRIG_INSERTED_T1_TRGO: TIMER1 TRGO event select
502 \arg ADC0_1_EXTTRIG_INSERTED_T1_CH0: TIMER1 CH0 event select
503 \arg ADC0_1_EXTTRIG_INSERTED_T2_CH3: TIMER2 CH3 event select
504 \arg ADC0_1_EXTTRIG_INSERTED_T3_TRGO: TIMER3 TRGO event select
505 \arg ADC0_1_EXTTRIG_INSERTED_EXTI_15: external interrupt line 15
506 \arg ADC0_1_EXTTRIG_INSERTED_NONE: software trigger
507 \param[out] none
508 \retval none
509 */
adc_external_trigger_source_config(uint32_t adc_periph,uint8_t adc_channel_group,uint32_t external_trigger_source)510 void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t external_trigger_source)
511 {
512 switch(adc_channel_group){
513 case ADC_REGULAR_CHANNEL:
514 /* configure ADC regular group external trigger source */
515 ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSRC);
516 ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source;
517 break;
518 case ADC_INSERTED_CHANNEL:
519 /* configure ADC inserted group external trigger source */
520 ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSIC);
521 ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source;
522 break;
523 default:
524 break;
525 }
526 }
527
528 /*!
529 \brief configure ADC external trigger
530 \param[in] adc_periph: ADCx, x=0,1
531 \param[in] adc_channel_group: select the channel group
532 one or more parameters can be selected which are shown as below:
533 \arg ADC_REGULAR_CHANNEL: regular channel group
534 \arg ADC_INSERTED_CHANNEL: inserted channel group
535 \param[in] newvalue: ENABLE or DISABLE
536 \param[out] none
537 \retval none
538 */
adc_external_trigger_config(uint32_t adc_periph,uint8_t adc_channel_group,ControlStatus newvalue)539 void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, ControlStatus newvalue)
540 {
541 if(newvalue){
542 if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){
543 /* enable ADC regular channel group external trigger */
544 ADC_CTL1(adc_periph) |= ADC_CTL1_ETERC;
545 }
546 if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){
547 /* enable ADC inserted channel group external trigger */
548 ADC_CTL1(adc_periph) |= ADC_CTL1_ETEIC;
549 }
550 }else{
551 if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){
552 /* disable ADC regular channel group external trigger */
553 ADC_CTL1(adc_periph) &= ~ADC_CTL1_ETERC;
554 }
555 if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){
556 /* disable ADC regular channel group external trigger */
557 ADC_CTL1(adc_periph) &= ~ADC_CTL1_ETEIC;
558 }
559 }
560 }
561
562 /*!
563 \brief enable ADC software trigger
564 \param[in] adc_periph: ADCx, x=0,1
565 \param[in] adc_channel_group: select the channel group
566 one or more parameters can be selected which are shown as below:
567 \arg ADC_REGULAR_CHANNEL: regular channel group
568 \arg ADC_INSERTED_CHANNEL: inserted channel group
569 \param[out] none
570 \retval none
571 */
adc_software_trigger_enable(uint32_t adc_periph,uint8_t adc_channel_group)572 void adc_software_trigger_enable(uint32_t adc_periph, uint8_t adc_channel_group)
573 {
574 if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){
575 /* enable ADC regular channel group software trigger */
576 ADC_CTL1(adc_periph) |= ADC_CTL1_SWRCST;
577 }
578 if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){
579 /* enable ADC inserted channel group software trigger */
580 ADC_CTL1(adc_periph) |= ADC_CTL1_SWICST;
581 }
582 }
583
584 /*!
585 \brief read ADC regular group data register
586 \param[in] adc_periph: ADCx, x=0,1
587 \param[in] none
588 \param[out] none
589 \retval the conversion value
590 */
adc_regular_data_read(uint32_t adc_periph)591 uint16_t adc_regular_data_read(uint32_t adc_periph)
592 {
593 return (uint16_t)(ADC_RDATA(adc_periph));
594 }
595
596 /*!
597 \brief read ADC inserted group data register
598 \param[in] adc_periph: ADCx, x=0,1
599 \param[in] inserted_channel: insert channel select
600 only one parameter can be selected
601 \arg ADC_INSERTED_CHANNEL_0: inserted Channel0
602 \arg ADC_INSERTED_CHANNEL_1: inserted channel1
603 \arg ADC_INSERTED_CHANNEL_2: inserted Channel2
604 \arg ADC_INSERTED_CHANNEL_3: inserted Channel3
605 \param[out] none
606 \retval the conversion value
607 */
adc_inserted_data_read(uint32_t adc_periph,uint8_t inserted_channel)608 uint16_t adc_inserted_data_read(uint32_t adc_periph, uint8_t inserted_channel)
609 {
610 uint32_t idata;
611 /* read the data of the selected channel */
612 switch(inserted_channel){
613 case ADC_INSERTED_CHANNEL_0:
614 /* read the data of channel 0 */
615 idata = ADC_IDATA0(adc_periph);
616 break;
617 case ADC_INSERTED_CHANNEL_1:
618 /* read the data of channel 1 */
619 idata = ADC_IDATA1(adc_periph);
620 break;
621 case ADC_INSERTED_CHANNEL_2:
622 /* read the data of channel 2 */
623 idata = ADC_IDATA2(adc_periph);
624 break;
625 case ADC_INSERTED_CHANNEL_3:
626 /* read the data of channel 3 */
627 idata = ADC_IDATA3(adc_periph);
628 break;
629 default:
630 idata = 0U;
631 break;
632 }
633 return (uint16_t)idata;
634 }
635
636 /*!
637 \brief read the last ADC0 and ADC1 conversion result data in sync mode
638 \param[in] none
639 \param[out] none
640 \retval the conversion value
641 */
adc_sync_mode_convert_value_read(void)642 uint32_t adc_sync_mode_convert_value_read(void)
643 {
644 /* return conversion value */
645 return ADC_RDATA(ADC0);
646 }
647
648
649 /*!
650 \brief configure ADC analog watchdog single channel
651 \param[in] adc_periph: ADCx, x=0,1
652 \param[in] adc_channel: the selected ADC channel
653 only one parameter can be selected which is shown as below:
654 \arg ADC_CHANNEL_x: ADC Channelx(x=0..17)(x=16 and x=17 are only for ADC0)
655 \param[out] none
656 \retval none
657 */
adc_watchdog_single_channel_enable(uint32_t adc_periph,uint8_t adc_channel)658 void adc_watchdog_single_channel_enable(uint32_t adc_periph, uint8_t adc_channel)
659 {
660 ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL);
661 /* analog watchdog channel select */
662 ADC_CTL0(adc_periph) |= (uint32_t)adc_channel;
663 ADC_CTL0(adc_periph) |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC);
664 }
665
666 /*!
667 \brief configure ADC analog watchdog group channel
668 \param[in] adc_periph: ADCx, x=0,1
669 \param[in] adc_channel_group: the channel group use analog watchdog
670 only one parameter can be selected which is shown as below:
671 \arg ADC_REGULAR_CHANNEL: regular channel group
672 \arg ADC_INSERTED_CHANNEL: inserted channel group
673 \arg ADC_REGULAR_INSERTED_CHANNEL: both regular and inserted group
674 \param[out] none
675 \retval none
676 */
adc_watchdog_group_channel_enable(uint32_t adc_periph,uint8_t adc_channel_group)677 void adc_watchdog_group_channel_enable(uint32_t adc_periph, uint8_t adc_channel_group)
678 {
679 ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC);
680 /* select the group */
681 switch(adc_channel_group){
682 case ADC_REGULAR_CHANNEL:
683 /* regular channel analog watchdog enable */
684 ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_RWDEN;
685 break;
686 case ADC_INSERTED_CHANNEL:
687 /* inserted channel analog watchdog enable */
688 ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_IWDEN;
689 break;
690 case ADC_REGULAR_INSERTED_CHANNEL:
691 /* regular and inserted channel analog watchdog enable */
692 ADC_CTL0(adc_periph) |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN);
693 break;
694 default:
695 break;
696 }
697 }
698
699 /*!
700 \brief disable ADC analog watchdog
701 \param[in] adc_periph: ADCx, x=0,1
702 \param[out] none
703 \retval none
704 */
adc_watchdog_disable(uint32_t adc_periph)705 void adc_watchdog_disable(uint32_t adc_periph)
706 {
707 ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL);
708 }
709
710 /*!
711 \brief configure ADC analog watchdog threshold
712 \param[in] adc_periph: ADCx, x=0,1
713 \param[in] low_threshold: analog watchdog low threshold, 0..4095
714 \param[in] high_threshold: analog watchdog high threshold, 0..4095
715 \param[out] none
716 \retval none
717 */
adc_watchdog_threshold_config(uint32_t adc_periph,uint16_t low_threshold,uint16_t high_threshold)718 void adc_watchdog_threshold_config(uint32_t adc_periph, uint16_t low_threshold, uint16_t high_threshold)
719 {
720 ADC_WDLT(adc_periph) = (uint32_t)WDLT_WDLT(low_threshold);
721 ADC_WDHT(adc_periph) = (uint32_t)WDHT_WDHT(high_threshold);
722 }
723
724 /*!
725 \brief get the ADC flag bits
726 \param[in] adc_periph: ADCx, x=0,1
727 \param[in] adc_flag: the adc flag bits
728 only one parameter can be selected which is shown as below:
729 \arg ADC_FLAG_WDE: analog watchdog event flag
730 \arg ADC_FLAG_EOC: end of group conversion flag
731 \arg ADC_FLAG_EOIC: end of inserted group conversion flag
732 \arg ADC_FLAG_STIC: start flag of inserted channel group
733 \arg ADC_FLAG_STRC: start flag of regular channel group
734 \param[out] none
735 \retval FlagStatus: SET or RESET
736 */
adc_flag_get(uint32_t adc_periph,uint32_t adc_flag)737 FlagStatus adc_flag_get(uint32_t adc_periph, uint32_t adc_flag)
738 {
739 FlagStatus reval = RESET;
740 if(ADC_STAT(adc_periph) & adc_flag){
741 reval = SET;
742 }
743 return reval;
744 }
745
746 /*!
747 \brief clear the ADC flag bits
748 \param[in] adc_periph: ADCx, x=0,1
749 \param[in] adc_flag: the adc flag bits
750 one or more parameters can be selected which are shown as below:
751 \arg ADC_FLAG_WDE: analog watchdog event flag
752 \arg ADC_FLAG_EOC: end of group conversion flag
753 \arg ADC_FLAG_EOIC: end of inserted group conversion flag
754 \arg ADC_FLAG_STIC: start flag of inserted channel group
755 \arg ADC_FLAG_STRC: start flag of regular channel group
756 \param[out] none
757 \retval none
758 */
adc_flag_clear(uint32_t adc_periph,uint32_t adc_flag)759 void adc_flag_clear(uint32_t adc_periph, uint32_t adc_flag)
760 {
761 ADC_STAT(adc_periph) &= ~((uint32_t)adc_flag);
762 }
763
764 /*!
765 \brief get the bit state of ADCx software start conversion
766 \param[in] adc_periph: ADCx, x=0,1
767 \param[in] none
768 \param[out] none
769 \retval FlagStatus: SET or RESET
770 */
adc_regular_software_startconv_flag_get(uint32_t adc_periph)771 FlagStatus adc_regular_software_startconv_flag_get(uint32_t adc_periph)
772 {
773 FlagStatus reval = RESET;
774 if((uint32_t)RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_SWRCST)){
775 reval = SET;
776 }
777 return reval;
778 }
779
780 /*!
781 \brief get the bit state of ADCx software inserted channel start conversion
782 \param[in] adc_periph: ADCx, x=0,1
783 \param[in] none
784 \param[out] none
785 \retval FlagStatus: SET or RESET
786 */
adc_inserted_software_startconv_flag_get(uint32_t adc_periph)787 FlagStatus adc_inserted_software_startconv_flag_get(uint32_t adc_periph)
788 {
789 FlagStatus reval = RESET;
790 if((uint32_t)RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_SWICST)){
791 reval = SET;
792 }
793 return reval;
794 }
795
796 /*!
797 \brief get the ADC interrupt bits
798 \param[in] adc_periph: ADCx, x=0,1
799 \param[in] adc_interrupt: the adc interrupt bits
800 only one parameter can be selected which is shown as below:
801 \arg ADC_INT_FLAG_WDE: analog watchdog interrupt
802 \arg ADC_INT_FLAG_EOC: end of group conversion interrupt
803 \arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt
804 \param[out] none
805 \retval FlagStatus: SET or RESET
806 */
adc_interrupt_flag_get(uint32_t adc_periph,uint32_t adc_interrupt)807 FlagStatus adc_interrupt_flag_get(uint32_t adc_periph, uint32_t adc_interrupt)
808 {
809 FlagStatus interrupt_flag = RESET;
810 uint32_t state;
811 /* check the interrupt bits */
812 switch(adc_interrupt){
813 case ADC_INT_FLAG_WDE:
814 /* get the ADC analog watchdog interrupt bits */
815 state = ADC_STAT(adc_periph) & ADC_STAT_WDE;
816 if((ADC_CTL0(adc_periph) & ADC_CTL0_WDEIE) && state){
817 interrupt_flag = SET;
818 }
819 break;
820 case ADC_INT_FLAG_EOC:
821 /* get the ADC end of group conversion interrupt bits */
822 state = ADC_STAT(adc_periph) & ADC_STAT_EOC;
823 if((ADC_CTL0(adc_periph) & ADC_CTL0_EOCIE) && state){
824 interrupt_flag = SET;
825 }
826 break;
827 case ADC_INT_FLAG_EOIC:
828 /* get the ADC end of inserted group conversion interrupt bits */
829 state = ADC_STAT(adc_periph) & ADC_STAT_EOIC;
830 if((ADC_CTL0(adc_periph) & ADC_CTL0_EOICIE) && state){
831 interrupt_flag = SET;
832 }
833 break;
834 default:
835 break;
836 }
837 return interrupt_flag;
838 }
839
840 /*!
841 \brief clear the ADC flag
842 \param[in] adc_periph: ADCx, x=0,1
843 \param[in] adc_interrupt: the adc status flag
844 one or more parameters can be selected which are shown as below:
845 \arg ADC_INT_FLAG_WDE: analog watchdog interrupt
846 \arg ADC_INT_FLAG_EOC: end of group conversion interrupt
847 \arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt
848 \param[out] none
849 \retval none
850 */
adc_interrupt_flag_clear(uint32_t adc_periph,uint32_t adc_interrupt)851 void adc_interrupt_flag_clear(uint32_t adc_periph, uint32_t adc_interrupt)
852 {
853 ADC_STAT(adc_periph) &= ~((uint32_t)adc_interrupt);
854 }
855
856 /*!
857 \brief enable ADC interrupt
858 \param[in] adc_periph: ADCx, x=0,1
859 \param[in] adc_interrupt: the adc interrupt
860 one or more parameters can be selected which are shown as below:
861 \arg ADC_INT_WDE: analog watchdog interrupt flag
862 \arg ADC_INT_EOC: end of group conversion interrupt flag
863 \arg ADC_INT_EOIC: end of inserted group conversion interrupt flag
864 \param[out] none
865 \retval none
866 */
adc_interrupt_enable(uint32_t adc_periph,uint32_t adc_interrupt)867 void adc_interrupt_enable(uint32_t adc_periph, uint32_t adc_interrupt)
868 {
869 /* enable ADC analog watchdog interrupt */
870 if(0U != (adc_interrupt & ADC_INT_WDE)){
871 ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_WDEIE;
872 }
873 /* enable ADC end of group conversion interrupt */
874 if(0U != (adc_interrupt & ADC_INT_EOC)){
875 ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOCIE;
876 }
877 /* enable ADC end of inserted group conversion interrupt */
878 if(0U != (adc_interrupt & ADC_INT_EOIC)){
879 ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOICIE;
880 }
881 }
882
883 /*!
884 \brief disable ADC interrupt
885 \param[in] adc_periph: ADCx, x=0,1
886 \param[in] adc_interrupt: the adc interrupt flag
887 one or more parameters can be selected which are shown as below:
888 \arg ADC_INT_WDE: analog watchdog interrupt flag
889 \arg ADC_INT_EOC: end of group conversion interrupt flag
890 \arg ADC_INT_EOIC: end of inserted group conversion interrupt flag
891 \param[out] none
892 \retval none
893 */
adc_interrupt_disable(uint32_t adc_periph,uint32_t adc_interrupt)894 void adc_interrupt_disable(uint32_t adc_periph, uint32_t adc_interrupt)
895 {
896 /* disable ADC analog watchdog interrupt */
897 if(0U != (adc_interrupt & ADC_INT_WDE)){
898 ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_WDEIE;
899 }
900 /* disable ADC end of group conversion interrupt */
901 if(0U != (adc_interrupt & ADC_INT_EOC)){
902 ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_EOCIE;
903 }
904 /* disable ADC end of inserted group conversion interrupt */
905 if(0U != (adc_interrupt & ADC_INT_EOIC)){
906 ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_EOICIE;
907 }
908 }
909
910 /*!
911 \brief adc resolution config
912 \param[in] adc_periph: ADCx, x=0,1
913 \param[in] resolution: ADC resolution
914 only one parameter can be selected which is shown as below:
915 \arg ADC_RESOLUTION_12B: 12-bit ADC resolution
916 \arg ADC_RESOLUTION_10B: 10-bit ADC resolution
917 \arg ADC_RESOLUTION_8B: 8-bit ADC resolution
918 \arg ADC_RESOLUTION_6B: 6-bit ADC resolution
919 \param[out] none
920 \retval none
921 */
adc_resolution_config(uint32_t adc_periph,uint32_t resolution)922 void adc_resolution_config(uint32_t adc_periph, uint32_t resolution)
923 {
924 ADC_OVSCR(adc_periph) &= ~((uint32_t)ADC_OVSCR_DRES);
925 ADC_OVSCR(adc_periph) |= (uint32_t)resolution;
926 }
927
928 /*!
929 \brief adc oversample mode config
930 \param[in] adc_periph: ADCx, x=0,1
931 \param[in] mode: ADC oversampling mode
932 only one parameter can be selected which is shown as below:
933 \arg ADC_OVERSAMPLING_ALL_CONVERT: all oversampled conversions for a channel
934 are done consecutively after a trigger
935 \arg ADC_OVERSAMPLING_ONE_CONVERT: each oversampled conversion for a channel
936 needs a trigger
937 \param[in] shift: ADC oversampling shift
938 only one parameter can be selected which is shown as below:
939 \arg ADC_OVERSAMPLING_SHIFT_NONE: no oversampling shift
940 \arg ADC_OVERSAMPLING_SHIFT_1B: 1-bit oversampling shift
941 \arg ADC_OVERSAMPLING_SHIFT_2B: 2-bit oversampling shift
942 \arg ADC_OVERSAMPLING_SHIFT_3B: 3-bit oversampling shift
943 \arg ADC_OVERSAMPLING_SHIFT_4B: 3-bit oversampling shift
944 \arg ADC_OVERSAMPLING_SHIFT_5B: 5-bit oversampling shift
945 \arg ADC_OVERSAMPLING_SHIFT_6B: 6-bit oversampling shift
946 \arg ADC_OVERSAMPLING_SHIFT_7B: 7-bit oversampling shift
947 \arg ADC_OVERSAMPLING_SHIFT_8B: 8-bit oversampling shift
948 \param[in] ratio: ADC oversampling ratio
949 only one parameter can be selected which is shown as below:
950 \arg ADC_OVERSAMPLING_RATIO_MUL2: oversampling ratio X2
951 \arg ADC_OVERSAMPLING_RATIO_MUL4: oversampling ratio X4
952 \arg ADC_OVERSAMPLING_RATIO_MUL8: oversampling ratio X8
953 \arg ADC_OVERSAMPLING_RATIO_MUL16: oversampling ratio X16
954 \arg ADC_OVERSAMPLING_RATIO_MUL32: oversampling ratio X32
955 \arg ADC_OVERSAMPLING_RATIO_MUL64: oversampling ratio X64
956 \arg ADC_OVERSAMPLING_RATIO_MUL128: oversampling ratio X128
957 \arg ADC_OVERSAMPLING_RATIO_MUL256: oversampling ratio X256
958 \param[out] none
959 \retval none
960 */
adc_oversample_mode_config(uint32_t adc_periph,uint8_t mode,uint16_t shift,uint8_t ratio)961 void adc_oversample_mode_config(uint32_t adc_periph, uint8_t mode, uint16_t shift,uint8_t ratio)
962 {
963 if(mode){
964 ADC_OVSCR(adc_periph) |= (uint32_t)ADC_OVSCR_TOVS;
965 }else{
966 ADC_OVSCR(adc_periph) &= ~((uint32_t)ADC_OVSCR_TOVS);
967 }
968 /* config the shift and ratio */
969 ADC_OVSCR(adc_periph) &= ~((uint32_t)(ADC_OVSCR_OVSR | ADC_OVSCR_OVSS));
970 ADC_OVSCR(adc_periph) |= ((uint32_t)shift | (uint32_t)ratio);
971 }
972
973 /*!
974 \brief enable ADC oversample mode
975 \param[in] adc_periph: ADCx, x=0,1
976 \param[out] none
977 \retval none
978 */
adc_oversample_mode_enable(uint32_t adc_periph)979 void adc_oversample_mode_enable(uint32_t adc_periph)
980 {
981 ADC_OVSCR(adc_periph) |= ADC_OVSCR_OVSEN;
982 }
983
984 /*!
985 \brief disable ADC oversample mode
986 \param[in] adc_periph: ADCx, x=0,1
987 \param[out] none
988 \retval none
989 */
adc_oversample_mode_disable(uint32_t adc_periph)990 void adc_oversample_mode_disable(uint32_t adc_periph)
991 {
992 ADC_OVSCR(adc_periph) &= ~((uint32_t)ADC_OVSCR_OVSEN);
993 }
994