1 /******************************************************************************* 2 * (c) Copyright 2012 Microsemi SoC Products Group. All rights reserved. 3 * 4 * 5 * 6 * SVN $Revision: 4410 $ 7 * SVN $Date: 2012-07-16 14:36:17 +0100 (Mon, 16 Jul 2012) $ 8 */ 9 10 #ifndef SYSTEM_INIT_CFG_TYPES_H_ 11 #define SYSTEM_INIT_CFG_TYPES_H_ 12 13 #ifdef __cplusplus 14 extern "C" { 15 #endif 16 17 /*============================================================================*/ 18 /* DDR Configuration */ 19 /*============================================================================*/ 20 typedef struct 21 { 22 /*-------------------------------------------------------------------------- 23 * DDR Controller registers. 24 */ 25 struct 26 { 27 uint16_t DYN_SOFT_RESET_CR; 28 uint16_t RESERVED0; 29 uint16_t DYN_REFRESH_1_CR; 30 uint16_t DYN_REFRESH_2_CR; 31 uint16_t DYN_POWERDOWN_CR; 32 uint16_t DYN_DEBUG_CR; 33 uint16_t MODE_CR; 34 uint16_t ADDR_MAP_BANK_CR; 35 uint16_t ECC_DATA_MASK_CR; 36 uint16_t ADDR_MAP_COL_1_CR; 37 uint16_t ADDR_MAP_COL_2_CR; 38 uint16_t ADDR_MAP_ROW_1_CR; 39 uint16_t ADDR_MAP_ROW_2_CR; 40 uint16_t INIT_1_CR; 41 uint16_t CKE_RSTN_CYCLES_1_CR; 42 uint16_t CKE_RSTN_CYCLES_2_CR; 43 uint16_t INIT_MR_CR; 44 uint16_t INIT_EMR_CR; 45 uint16_t INIT_EMR2_CR; 46 uint16_t INIT_EMR3_CR; 47 uint16_t DRAM_BANK_TIMING_PARAM_CR; 48 uint16_t DRAM_RD_WR_LATENCY_CR; 49 uint16_t DRAM_RD_WR_PRE_CR; 50 uint16_t DRAM_MR_TIMING_PARAM_CR; 51 uint16_t DRAM_RAS_TIMING_CR; 52 uint16_t DRAM_RD_WR_TRNARND_TIME_CR; 53 uint16_t DRAM_T_PD_CR; 54 uint16_t DRAM_BANK_ACT_TIMING_CR; 55 uint16_t ODT_PARAM_1_CR; 56 uint16_t ODT_PARAM_2_CR; 57 uint16_t ADDR_MAP_COL_3_CR; 58 uint16_t MODE_REG_RD_WR_CR; 59 uint16_t MODE_REG_DATA_CR; 60 uint16_t PWR_SAVE_1_CR; 61 uint16_t PWR_SAVE_2_CR; 62 uint16_t ZQ_LONG_TIME_CR; 63 uint16_t ZQ_SHORT_TIME_CR; 64 uint16_t ZQ_SHORT_INT_REFRESH_MARGIN_1_CR; 65 uint16_t ZQ_SHORT_INT_REFRESH_MARGIN_2_CR; 66 uint16_t PERF_PARAM_1_CR; 67 uint16_t HPR_QUEUE_PARAM_1_CR; 68 uint16_t HPR_QUEUE_PARAM_2_CR; 69 uint16_t LPR_QUEUE_PARAM_1_CR; 70 uint16_t LPR_QUEUE_PARAM_2_CR; 71 uint16_t WR_QUEUE_PARAM_CR; 72 uint16_t PERF_PARAM_2_CR; 73 uint16_t PERF_PARAM_3_CR; 74 uint16_t DFI_RDDATA_EN_CR; 75 uint16_t DFI_MIN_CTRLUPD_TIMING_CR; 76 uint16_t DFI_MAX_CTRLUPD_TIMING_CR; 77 uint16_t DFI_WR_LVL_CONTROL_1_CR; 78 uint16_t DFI_WR_LVL_CONTROL_2_CR; 79 uint16_t DFI_RD_LVL_CONTROL_1_CR; 80 uint16_t DFI_RD_LVL_CONTROL_2_CR; 81 uint16_t DFI_CTRLUPD_TIME_INTERVAL_CR; 82 uint16_t DYN_SOFT_RESET_CR2; 83 uint16_t AXI_FABRIC_PRI_ID_CR; 84 } ddrc; 85 86 /*-------------------------------------------------------------------------- 87 * DDR PHY configuration registers 88 */ 89 struct 90 { 91 uint16_t LOOPBACK_TEST_CR; 92 uint16_t BOARD_LOOPBACK_CR; 93 uint16_t CTRL_SLAVE_RATIO_CR; 94 uint16_t CTRL_SLAVE_FORCE_CR; 95 uint16_t CTRL_SLAVE_DELAY_CR; 96 uint16_t DATA_SLICE_IN_USE_CR; 97 uint16_t LVL_NUM_OF_DQ0_CR; 98 uint16_t DQ_OFFSET_1_CR; 99 uint16_t DQ_OFFSET_2_CR; 100 uint16_t DQ_OFFSET_3_CR; 101 uint16_t DIS_CALIB_RST_CR; 102 uint16_t DLL_LOCK_DIFF_CR; 103 uint16_t FIFO_WE_IN_DELAY_1_CR; 104 uint16_t FIFO_WE_IN_DELAY_2_CR; 105 uint16_t FIFO_WE_IN_DELAY_3_CR; 106 uint16_t FIFO_WE_IN_FORCE_CR; 107 uint16_t FIFO_WE_SLAVE_RATIO_1_CR; 108 uint16_t FIFO_WE_SLAVE_RATIO_2_CR; 109 uint16_t FIFO_WE_SLAVE_RATIO_3_CR; 110 uint16_t FIFO_WE_SLAVE_RATIO_4_CR; 111 uint16_t GATELVL_INIT_MODE_CR; 112 uint16_t GATELVL_INIT_RATIO_1_CR; 113 uint16_t GATELVL_INIT_RATIO_2_CR; 114 uint16_t GATELVL_INIT_RATIO_3_CR; 115 uint16_t GATELVL_INIT_RATIO_4_CR; 116 uint16_t LOCAL_ODT_CR; 117 uint16_t INVERT_CLKOUT_CR; 118 uint16_t RD_DQS_SLAVE_DELAY_1_CR; 119 uint16_t RD_DQS_SLAVE_DELAY_2_CR; 120 uint16_t RD_DQS_SLAVE_DELAY_3_CR; 121 uint16_t RD_DQS_SLAVE_FORCE_CR; 122 uint16_t RD_DQS_SLAVE_RATIO_1_CR; 123 uint16_t RD_DQS_SLAVE_RATIO_2_CR; 124 uint16_t RD_DQS_SLAVE_RATIO_3_CR; 125 uint16_t RD_DQS_SLAVE_RATIO_4_CR; 126 uint16_t WR_DQS_SLAVE_DELAY_1_CR; 127 uint16_t WR_DQS_SLAVE_DELAY_2_CR; 128 uint16_t WR_DQS_SLAVE_DELAY_3_CR; 129 uint16_t WR_DQS_SLAVE_FORCE_CR; 130 uint16_t WR_DQS_SLAVE_RATIO_1_CR; 131 uint16_t WR_DQS_SLAVE_RATIO_2_CR; 132 uint16_t WR_DQS_SLAVE_RATIO_3_CR; 133 uint16_t WR_DQS_SLAVE_RATIO_4_CR; 134 uint16_t WR_DATA_SLAVE_DELAY_1_CR; 135 uint16_t WR_DATA_SLAVE_DELAY_2_CR; 136 uint16_t WR_DATA_SLAVE_DELAY_3_CR; 137 uint16_t WR_DATA_SLAVE_FORCE_CR; 138 uint16_t WR_DATA_SLAVE_RATIO_1_CR; 139 uint16_t WR_DATA_SLAVE_RATIO_2_CR; 140 uint16_t WR_DATA_SLAVE_RATIO_3_CR; 141 uint16_t WR_DATA_SLAVE_RATIO_4_CR; 142 uint16_t WRLVL_INIT_MODE_CR; 143 uint16_t WRLVL_INIT_RATIO_1_CR; 144 uint16_t WRLVL_INIT_RATIO_2_CR; 145 uint16_t WRLVL_INIT_RATIO_3_CR; 146 uint16_t WRLVL_INIT_RATIO_4_CR; 147 uint16_t WR_RD_RL_CR; 148 uint16_t RDC_FIFO_RST_ERRCNTCLR_CR; 149 uint16_t RDC_WE_TO_RE_DELAY_CR; 150 uint16_t USE_FIXED_RE_CR; 151 uint16_t USE_RANK0_DELAYS_CR; 152 uint16_t USE_LVL_TRNG_LEVEL_CR; 153 uint16_t CONFIG_CR; 154 uint16_t RD_WR_GATE_LVL_CR; 155 uint16_t DYN_RESET_CR; 156 } phy; 157 158 /*-------------------------------------------------------------------------- 159 * FIC-64 registers 160 * These registers are 16-bit wide and 32-bit aligned. 161 */ 162 struct 163 { 164 uint16_t NB_ADDR_CR; 165 uint16_t NBRWB_SIZE_CR; 166 uint16_t WB_TIMEOUT_CR; 167 uint16_t HPD_SW_RW_EN_CR; 168 uint16_t HPD_SW_RW_INVAL_CR; 169 uint16_t SW_WR_ERCLR_CR; 170 uint16_t ERR_INT_ENABLE_CR; 171 uint16_t NUM_AHB_MASTERS_CR; 172 uint16_t LOCK_TIMEOUTVAL_1_CR; 173 uint16_t LOCK_TIMEOUTVAL_2_CR; 174 uint16_t LOCK_TIMEOUT_EN_CR; 175 } fic; 176 } ddr_subsys_cfg_t; 177 178 /*============================================================================*/ 179 /* FDDR Configuration */ 180 /*============================================================================*/ 181 182 typedef struct 183 { 184 uint16_t PLL_CONFIG_LOW_1; 185 uint16_t PLL_CONFIG_LOW_2; 186 uint16_t PLL_CONFIG_HIGH; 187 uint16_t FACC_CLK_EN; 188 uint16_t FACC_MUX_CONFIG; 189 uint16_t FACC_DIVISOR_RATIO; 190 uint16_t PLL_DELAY_LINE_SEL; 191 uint16_t SOFT_RESET; 192 uint16_t IO_CALIB; 193 uint16_t INTERRUPT_ENABLE; 194 uint16_t AXI_AHB_MODE_SEL; 195 uint16_t PHY_SELF_REF_EN; 196 } fddr_sysreg_t; 197 198 /*============================================================================*/ 199 /* PCI Express Bridge IP Core configuration. */ 200 /*============================================================================*/ 201 202 typedef struct 203 { 204 uint32_t * p_reg; 205 uint32_t value; 206 } cfg_addr_value_pair_t; 207 208 #ifdef __cplusplus 209 } 210 #endif 211 212 #endif /* SYSTEM_INIT_CFG_TYPES_H_ */ 213