1 //###########################################################################
2 //
3 // FILE: F2837xD_McBSP.c
4 //
5 // TITLE: F2837xD Device McBSP Initialization & Support Functions.
6 //
7 //###########################################################################
8 // $TI Release: F2837xD Support Library v3.05.00.00 $
9 // $Release Date: Tue Jun 26 03:15:23 CDT 2018 $
10 // $Copyright:
11 // Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/
12 //
13 // Redistribution and use in source and binary forms, with or without
14 // modification, are permitted provided that the following conditions
15 // are met:
16 //
17 // Redistributions of source code must retain the above copyright
18 // notice, this list of conditions and the following disclaimer.
19 //
20 // Redistributions in binary form must reproduce the above copyright
21 // notice, this list of conditions and the following disclaimer in the
22 // documentation and/or other materials provided with the
23 // distribution.
24 //
25 // Neither the name of Texas Instruments Incorporated nor the names of
26 // its contributors may be used to endorse or promote products derived
27 // from this software without specific prior written permission.
28 //
29 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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38 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 // $
41 //###########################################################################
42
43 //
44 // Included Files
45 //
46 #include "F2837xD_device.h"
47 #include "F2837xD_Examples.h"
48
49 //
50 // MCBSP_INIT_DELAY determines the amount of CPU cycles in the 2 sample rate
51 // generator (SRG) cycles required for the Mcbsp initialization routine.
52 // MCBSP_CLKG_DELAY determines the amount of CPU cycles in the 2 clock
53 // generator (CLKG) cycles required for the Mcbsp initialization routine.
54 //
55
56 //
57 // Defines
58 //
59 #define CPU_SPD 200E6
60 #define MCBSP_SRG_FREQ CPU_SPD/4 // SRG input is LSPCLK (SYSCLKOUT/4)
61 // for examples
62 #define CLKGDV_VAL 1
63
64 // # of CPU cycles in 2 SRG cycles-init delay
65 #define MCBSP_INIT_DELAY 2*(CPU_SPD/MCBSP_SRG_FREQ)
66
67 // # of CPU cycles in 2 CLKG cycles-init delay
68 #define MCBSP_CLKG_DELAY 2*(CPU_SPD/(MCBSP_SRG_FREQ/(1+CLKGDV_VAL)))
69
70 //
71 // Function Prototypes
72 //
73 void delay_loop(void); // Delay function used for SRG initialization
74 void clkg_delay_loop(void); // Delay function used for CLKG initialization
75
76 //
77 // InitMcbsp - This function initializes the McBSP to a known state.
78 //
InitMcbspa(void)79 void InitMcbspa(void)
80 {
81 //
82 // Reset the McBSP
83 // Disable all interrupts
84 // Frame sync generator reset
85 // Sample rate generator reset
86 // Transmitter reset
87 // Receiver reset
88 //
89 McbspaRegs.SPCR2.bit.FRST = 0;
90 McbspaRegs.SPCR2.bit.GRST = 0;
91 McbspaRegs.SPCR2.bit.XRST = 0;
92 McbspaRegs.SPCR1.bit.RRST = 0;
93
94 //
95 // Enable loop back mode
96 // This does not require external hardware
97 //
98 McbspaRegs.SPCR2.all = 0x0000;
99 McbspaRegs.SPCR1.all = 0x8000;
100
101 //
102 // RX data delay is 1 bit
103 // TX data delay is 1 bit
104 //
105 McbspaRegs.RCR2.bit.RDATDLY = 1;
106 McbspaRegs.XCR2.bit.XDATDLY = 1;
107
108 //
109 // No clock sync for CLKG
110 // Frame-synchronization period
111 //
112 McbspaRegs.SRGR2.bit.GSYNC = 0;
113 McbspaRegs.SRGR2.bit.FPER = 320;
114
115 //
116 // Frame-synchronization pulses from
117 // the sample rate generator
118 //
119 McbspaRegs.SRGR2.bit.FSGM = 1;
120
121 //
122 // Sample rate generator input clock is LSPCLK
123 //
124 McbspaRegs.SRGR2.bit.CLKSM = 1;
125 McbspaRegs.PCR.bit.SCLKME = 0;
126
127 //
128 // Divide-down value for CLKG
129 // Frame-synchronization pulse width
130 //
131 McbspaRegs.SRGR1.bit.CLKGDV = CLKGDV_VAL;
132 clkg_delay_loop();
133 McbspaRegs.SRGR1.bit.FWID = 1;
134
135 //
136 // CLKX is driven by the sample rate generator
137 // Transmit frame synchronization generated by internal
138 // sample rate generator
139 //
140 McbspaRegs.PCR.bit.CLKXM = 1;
141 McbspaRegs.PCR.bit.FSXM = 1;
142
143 //
144 // Enable Sample rate generator and
145 // wait at least 2 CLKG clock cycles
146 //
147 McbspaRegs.SPCR2.bit.GRST = 1;
148 clkg_delay_loop();
149
150 //
151 // Release from reset
152 // RX, TX and frame sync generator
153 //
154 McbspaRegs.SPCR2.bit.XRST = 1;
155 McbspaRegs.SPCR1.bit.RRST = 1;
156 McbspaRegs.SPCR2.bit.FRST = 1;
157 }
158
159 //
160 // InitMcbspaInt - Enable TX and RX interrupts
161 //
InitMcbspaInt(void)162 void InitMcbspaInt(void)
163 {
164 // Reset TX and RX
165 // Enable interrupts for TX and RX
166 // Release TX and RX
167 McbspaRegs.SPCR2.bit.XRST = 0;
168 McbspaRegs.SPCR1.bit.RRST = 0;
169 McbspaRegs.MFFINT.bit.XINT = 1;
170 McbspaRegs.MFFINT.bit.RINT = 1;
171 McbspaRegs.SPCR2.bit.XRST = 1;
172 McbspaRegs.SPCR1.bit.RRST = 1;
173 }
174
175 //
176 // InitMcbspa8bit - McBSP uses an 8-bit word for both TX and RX
177 //
InitMcbspa8bit(void)178 void InitMcbspa8bit(void)
179 {
180 McbspaRegs.RCR1.bit.RWDLEN1 = 0;
181 McbspaRegs.XCR1.bit.XWDLEN1 = 0;
182 }
183
184 //
185 // InitMcbspa12bit - McBSP uses an 12-bit word for both TX and RX
186 //
InitMcbspa12bit(void)187 void InitMcbspa12bit(void)
188 {
189 McbspaRegs.RCR1.bit.RWDLEN1 = 1;
190 McbspaRegs.XCR1.bit.XWDLEN1 = 1;
191 }
192
193 //
194 // InitMcbspa16bit - McBSP uses an 16-bit word for both TX and RX
195 //
InitMcbspa16bit(void)196 void InitMcbspa16bit(void)
197 {
198 McbspaRegs.RCR1.bit.RWDLEN1 = 2;
199 McbspaRegs.XCR1.bit.XWDLEN1 = 2;
200 }
201
202 //
203 // InitMcbspa20bit - McBSP uses an 20-bit word for both TX and RX
204 //
InitMcbspa20bit(void)205 void InitMcbspa20bit(void)
206 {
207 McbspaRegs.RCR1.bit.RWDLEN1 = 3;
208 McbspaRegs.XCR1.bit.XWDLEN1 = 3;
209 }
210
211 //
212 // InitMcbspa24bit - McBSP uses an 24-bit word for both TX and RX
213 //
InitMcbspa24bit(void)214 void InitMcbspa24bit(void)
215 {
216 McbspaRegs.RCR1.bit.RWDLEN1 = 4;
217 McbspaRegs.XCR1.bit.XWDLEN1 = 4;
218 }
219
220 //
221 // InitMcbspa32bit - McBSP uses an 32-bit word for both TX and RX
222 //
InitMcbspa32bit(void)223 void InitMcbspa32bit(void)
224 {
225 McbspaRegs.RCR1.bit.RWDLEN1 = 5;
226 McbspaRegs.XCR1.bit.XWDLEN1 = 5;
227 }
228
229 //
230 // InitMcbspaGpio - Assign GPIO pins to the McBSP peripheral
231 // (Note: This function must be called from CPU1.)
232 //
InitMcbspaGpio(void)233 void InitMcbspaGpio(void)
234 {
235 #ifdef CPU1
236 EALLOW;
237
238 //
239 // This specifies which of the possible GPIO pins will be
240 // McBSPA functional pins. Comment out unwanted connections.
241 // Set qualification for selected input pins to asynchronous only
242 // This will select asynchronous (no qualification) for the selected pins.
243 //
244
245 //
246 // MDXA
247 // GPIO20
248 // GPIO84
249 //
250 GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 2;
251 //GpioCtrlRegs.GPCGMUX2.bit.GPIO84 = 3;
252 //GpioCtrlRegs.GPCMUX2.bit.GPIO84 = 3;
253
254 //
255 // MDRA
256 // GPIO21 with asynchronous qualification
257 // GPIO85 with asynchronous qualification
258 //
259 GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 2;
260 GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 3;
261 //GpioCtrlRegs.GPCGMUX2.bit.GPIO85 = 3;
262 //GpioCtrlRegs.GPCMUX2.bit.GPIO85 = 3;
263 //GpioCtrlRegs.GPCQSEL2.bit.GPIO85 = 3;
264
265 //
266 // MCLKXA
267 // GPIO22 with asynchronous qualification
268 // GPIO86 with asynchronous qualification
269 //
270 GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 2;
271 //GpioCtrlRegs.GPAQSEL2.bit.GPIO22 = 3;
272 //GpioCtrlRegs.GPCGMUX2.bit.GPIO86 = 3;
273 //GpioCtrlRegs.GPCMUX2.bit.GPIO86 = 3;
274 //GpioCtrlRegs.GPCQSEL2.bit.GPIO86 = 3;
275
276 //
277 // MCLKRA
278 // Select one of the following
279 // GPIO7 with asynchronous qualification
280 // GPIO58 with asynchronous qualification
281 //
282 GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 2;
283 GpioCtrlRegs.GPAQSEL1.bit.GPIO7 = 3;
284 //GpioCtrlRegs.GPBMUX2.bit.GPIO58 = 1;
285 //GpioCtrlRegs.GPBQSEL2.bit.GPIO58 = 3;
286
287 //
288 // MFSXA
289 // GPIO23 with asynchronous qualification
290 // GPIO87 with asynchronous qualification
291 //
292 GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 2;
293 //GpioCtrlRegs.GPAQSEL2.bit.GPIO23 = 3;
294 //GpioCtrlRegs.GPCGMUX2.bit.GPIO87 = 3;
295 //GpioCtrlRegs.GPCMUX2.bit.GPIO87 = 3;
296 //GpioCtrlRegs.GPCQSEL2.bit.GPIO87 = 3;
297
298 //
299 // MFSRA
300 // Select one of the following
301 // GPIO5 with asynchronous qualification
302 // GPIO59 with asynchronous qualification
303 //
304 GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 2;
305 GpioCtrlRegs.GPAQSEL1.bit.GPIO5 = 3;
306 //GpioCtrlRegs.GPBMUX2.bit.GPIO59 = 1;
307 //GpioCtrlRegs.GPBQSEL2.bit.GPIO59 = 3;
308
309 EDIS;
310 #endif
311 }
312
313 //
314 // InitMcbspb - McBSPB initialization routine for examples
315 //
InitMcbspb(void)316 void InitMcbspb(void)
317 {
318 //
319 // Reset the McBSP
320 // Disable all interrupts
321 // Frame sync generator reset
322 // Sample rate generator reset
323 // Transmitter reset
324 // Receiver reset
325 //
326 McbspbRegs.SPCR2.bit.FRST = 0;
327 McbspbRegs.SPCR2.bit.GRST = 0;
328 McbspbRegs.SPCR2.bit.XRST = 0;
329 McbspbRegs.SPCR1.bit.RRST = 0;
330
331 //
332 // Enable loop back mode
333 // This does not require external hardware
334 //
335 McbspbRegs.SPCR2.all = 0x0000;
336 McbspbRegs.SPCR1.all = 0x8000;
337
338 //
339 // RX data delay is 1 bit
340 // TX data delay is 1 bit
341 //
342 McbspbRegs.RCR2.bit.RDATDLY = 1;
343 McbspbRegs.XCR2.bit.XDATDLY = 1;
344
345 //
346 // No clock sync for CLKG
347 // Frame-synchronization period
348 //
349 McbspbRegs.SRGR2.bit.GSYNC = 0;
350 McbspbRegs.SRGR2.bit.FPER = 320;
351
352 //
353 // Frame-synchronization pulses from
354 // the sample rate generator
355 //
356 McbspbRegs.SRGR2.bit.FSGM = 1;
357
358 //
359 // Sample rate generator input clock is LSPCLK
360 //
361 McbspbRegs.SRGR2.bit.CLKSM = 1;
362 McbspbRegs.PCR.bit.SCLKME = 0;
363
364 //
365 // Divide-down value for CLKG
366 // Frame-synchronization pulse width
367 //
368 McbspbRegs.SRGR1.bit.CLKGDV = CLKGDV_VAL;
369 clkg_delay_loop();
370 McbspbRegs.SRGR1.bit.FWID = 1;
371
372 //
373 // CLKX is driven by the sample rate generator
374 // Transmit frame synchronization generated by internal
375 // sample rate generator
376 //
377 McbspbRegs.PCR.bit.CLKXM = 1;
378 McbspbRegs.PCR.bit.FSXM = 1;
379
380 //
381 // Enable Sample rate generator and
382 // wait at least 2 CLKG clock cycles
383 //
384 McbspbRegs.SPCR2.bit.GRST = 1;
385 clkg_delay_loop();
386
387 //
388 // Release from reset
389 // RX, TX and frame sync generator
390 //
391 McbspbRegs.SPCR2.bit.XRST = 1;
392 McbspbRegs.SPCR1.bit.RRST = 1;
393 McbspbRegs.SPCR2.bit.FRST = 1;
394 }
395
396 //
397 // InitMcbspbInt - Enable TX and RX interrupts
398 //
InitMcbspbInt(void)399 void InitMcbspbInt(void)
400 {
401 //
402 // Reset TX and RX
403 // Enable interrupts for TX and RX
404 // Release TX and RX
405 //
406 McbspbRegs.SPCR2.bit.XRST = 0;
407 McbspbRegs.SPCR1.bit.RRST = 0;
408 McbspbRegs.MFFINT.bit.XINT = 1;
409 McbspbRegs.MFFINT.bit.RINT = 1;
410 McbspbRegs.SPCR2.bit.XRST = 1;
411 McbspbRegs.SPCR1.bit.RRST = 1;
412 }
413
414 //
415 // InitMcbspb8bit - McBSPB uses an 8-bit word for both TX and RX
416 //
InitMcbspb8bit(void)417 void InitMcbspb8bit(void)
418 {
419 McbspbRegs.RCR1.bit.RWDLEN1 = 0;
420 McbspbRegs.XCR1.bit.XWDLEN1 = 0;
421 }
422
423 //
424 // IniMcbspb12bit - McBSPB uses an 12-bit word for both TX and RX
425 //
IniMcbspb12bit(void)426 void IniMcbspb12bit(void)
427 {
428 McbspbRegs.RCR1.bit.RWDLEN1 = 1;
429 McbspbRegs.XCR1.bit.XWDLEN1 = 1;
430 }
431
432 //
433 // InitMcbspb16bit - McBSPB uses an 16-bit word for both TX and RX
434 //
InitMcbspb16bit(void)435 void InitMcbspb16bit(void)
436 {
437 McbspbRegs.RCR1.bit.RWDLEN1 = 2;
438 McbspbRegs.XCR1.bit.XWDLEN1 = 2;
439 }
440
441 //
442 // InitMcbspb20bit - McBSPB uses an 20-bit word for both TX and RX
443 //
InitMcbspb20bit(void)444 void InitMcbspb20bit(void)
445 {
446 McbspbRegs.RCR1.bit.RWDLEN1 = 3;
447 McbspbRegs.XCR1.bit.XWDLEN1 = 3;
448 }
449
450 //
451 // InitMcbspb24bit - McBSPB uses an 24-bit word for both TX and RX
452 //
InitMcbspb24bit(void)453 void InitMcbspb24bit(void)
454 {
455 McbspbRegs.RCR1.bit.RWDLEN1 = 4;
456 McbspbRegs.XCR1.bit.XWDLEN1 = 4;
457 }
458
459 //
460 // InitMcbspb32bit - McBSPB uses an 32-bit word for both TX and RX
461 //
InitMcbspb32bit(void)462 void InitMcbspb32bit(void)
463 {
464 McbspbRegs.RCR1.bit.RWDLEN1 = 5;
465 McbspbRegs.XCR1.bit.XWDLEN1 = 5;
466 }
467
468 //
469 // InitMcbspbGpio - Assign GPIO pins to the McBSP peripheral
470 // (Note: This function must be called from CPU1.)
471 //
InitMcbspbGpio(void)472 void InitMcbspbGpio(void)
473 {
474 #ifdef CPU1
475 EALLOW;
476
477 //
478 // This specifies which of the possible GPIO pins will be
479 // McBSPB functional pins. Comment out unwanted connections.
480 // Set qualification for selected input pins to asynchronous only
481 // This will select asynchronous (no qualification) for the selected pins.
482 //
483
484 //
485 // Select one of the following for MDXB
486 // GPIO24
487 // GPIO84
488 //
489 //GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 3;
490 GpioCtrlRegs.GPCGMUX2.bit.GPIO84 = 1;
491 GpioCtrlRegs.GPCMUX2.bit.GPIO84 = 2;
492
493 //
494 // MDRB
495 // GPIO13 with asynchronous qualification
496 // GPIO25 with asynchronous qualification
497 // GPIO85 with asynchronous qualification
498 //
499 //GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 3;
500 //GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 3;
501 //GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 3;
502 //GpioCtrlRegs.GPAQSEL2.bit.GPIO25 = 3;
503 GpioCtrlRegs.GPCGMUX2.bit.GPIO85 = 1;
504 GpioCtrlRegs.GPCMUX2.bit.GPIO85 = 2;
505 GpioCtrlRegs.GPCQSEL2.bit.GPIO85 = 3;
506
507 //
508 // MCLKXB
509 // GPIO14 with asynchronous qualification
510 // GPIO26 with asynchronous qualification
511 // GPIO86 with asynchronous qualification
512 //
513 //GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 3;
514 //GpioCtrlRegs.GPAQSEL1.bit.GPIO14 = 3;
515 //GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 3;
516 //GpioCtrlRegs.GPAQSEL2.bit.GPIO26 = 3;
517 GpioCtrlRegs.GPCGMUX2.bit.GPIO86 = 1;
518 GpioCtrlRegs.GPCMUX2.bit.GPIO86 = 2;
519 GpioCtrlRegs.GPCQSEL2.bit.GPIO86= 3;
520
521 //
522 // MCLKRB
523 // Select one of the following
524 // GPIO3 with asynchronous qualification
525 // GPIO60 with asynchronous qualification
526 //
527 //GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 3;
528 //GpioCtrlRegs.GPAQSEL1.bit.GPIO3 = 3;
529 GpioCtrlRegs.GPBMUX2.bit.GPIO60 = 1;
530 GpioCtrlRegs.GPBQSEL2.bit.GPIO60 = 3;
531
532 //
533 // MFSXB
534 // GPIO15 with asynchronous qualification
535 // GPIO27 with asynchronous qualification
536 // GPIO87 with asynchronous qualification
537 //
538 //GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 3;
539 //GpioCtrlRegs.GPAQSEL1.bit.GPIO15 = 3;
540 //GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 3;
541 //GpioCtrlRegs.GPAQSEL2.bit.GPIO27 = 3;
542 GpioCtrlRegs.GPCGMUX2.bit.GPIO87 = 1;
543 GpioCtrlRegs.GPCMUX2.bit.GPIO87 = 2;
544 GpioCtrlRegs.GPCQSEL2.bit.GPIO87= 3;
545
546 //
547 // MFSRB
548 // Select one of the following
549 // GPIO1 with asynchronous qualification
550 // GPIO61 with asynchronous qualification
551 //
552 //GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 3;
553 //GpioCtrlRegs.GPAQSEL1.bit.GPIO1 = 3;
554 GpioCtrlRegs.GPBMUX2.bit.GPIO61 = 1;
555 GpioCtrlRegs.GPBQSEL2.bit.GPIO61 = 3;
556
557 EDIS;
558
559 #endif
560 }
561
562 //
563 // delay_loop - Delay function (at least 2 SRG cycles)
564 // Required in McBSP initialization
565 //
delay_loop(void)566 void delay_loop(void)
567 {
568 long i;
569 for (i = 0; i < MCBSP_INIT_DELAY; i++) {}
570 }
571
572 //
573 // clkg_delay_loop - Delay function (at least 2 CLKG cycles)
574 // Required in McBSP init
575 //
clkg_delay_loop(void)576 void clkg_delay_loop(void)
577 {
578 long i;
579 for (i = 0; i < MCBSP_CLKG_DELAY; i++) {}
580 }
581
582 //
583 // End of file
584 //
585