1 /*
2 * Copyright (c) 2006-2023, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2022-08-22 Emuzit first version
9 */
10 #ifndef __CH56X_USBHS_H__
11 #define __CH56X_USBHS_H__
12
13 #include "soc.h"
14
15 #ifdef __cplusplus
16 extern "C" {
17 #endif
18
19 #ifdef SOC_SERIES_CH569
20 #define UEP_ADDRESS_MAX 7
21 #define UEP_RT_DMA_MASK 0x1fff0
22 #else
23 #define UEP_ADDRESS_MAX 4
24 #define UEP_RT_DMA_MASK 0x0fffc
25 #endif
26
27 union _usb_ctrl
28 {
29 uint8_t reg;
30 struct
31 {
32 uint8_t dma_en : 1; // RW, USB DMA and DMA interrupt enable bit
33 uint8_t clr_all : 1; // RW, Empty USB interrupt flag and FIFO
34 uint8_t reset_sie : 1; // RW, Forcibly reset the USB SIE
35 uint8_t int_busy : 1; // RW, Auto pause enable bit @ RB_USB_IF_TRANSFER
36 uint8_t pu_en : 1; // RW, device & pull-up-R enable, DEVICE mode
37 uint8_t sptp_mask : 2; // RW, USB bus signal transfer rate selection bit
38 uint8_t mode : 1; // RW, USB working mode selection bit
39 };
40 };
41 #define RB_USB_DMA_EN 0x01
42 #define RB_USB_CLR_ALL 0x02
43 #define RB_USB_RESET_SIE 0x04
44 #define RB_USB_INT_BUSY 0x08
45 #define RB_DEV_PU_EN 0x10
46 #define RB_USB_SPTP_MASK 0x60
47 #define RB_USB_MODE 0x80
48
49 #define USBHS_FULL_SPEED 0
50 #define USBHS_HIGH_SPEED 1
51 #define USBHS_LOW_SPEED 2
52
53 #define USBHS_DEVICE_MODE 0
54 #define USBHS_HOST_MODE 1
55
56 #define RB_SPTP_FULL_SPEED (USBHS_FULL_SPEED << 5)
57 #define RB_SPTP_HIGH_SPEED (USBHS_HIGH_SPEED << 5)
58 #define RB_SPTP_LOW_SPEED (USBHS_LOW_SPEED << 5)
59
60 #define RB_USB_DEVICE_MODE (USBHS_DEVICE_MODE << 7)
61 #define RB_USB_HOST_MODE (USBHS_HOST_MODE << 7)
62
63 union _usb_int_en
64 {
65 uint8_t reg;
66 struct
67 {
68 uint8_t busrst : 1; // RW, USB bus reset event IE, DEVICE mode
69 uint8_t trans : 1; // RW, USB transfer complete interrupt enable
70 uint8_t suspend : 1; // RW, USB bus suspend/wake-up event IE
71 uint8_t sof : 1; // RW, SOF packet/timing interrupt enable
72 uint8_t fifoov : 1; // RW, Internal FIFO overflow interrupt enable
73 #ifdef SOC_SERIES_CH569
74 uint8_t setupact : 1; // RW, SETUP transaction complete interrupt
75 uint8_t isoact : 1; // RW, ISOchronous token received IE
76 uint8_t dev_nak : 1; // RW, NAK interrupt enable, DEVICE mode
77 #else
78 uint8_t resv_5 : 1;
79 uint8_t dev_nak : 1; // RW, NAK interrupt enable, DEVICE mode
80 uint8_t dev_sof : 1; // RW, SOF packet received IE, DEVICE mode
81 #endif
82 };
83 struct
84 {
85 uint8_t detect : 1; // RW, USB device connect/disconnect IE, HOST mode
86 uint8_t stuff_1 : 7;
87 };
88 };
89 #define RB_USB_IE_BUSRST 0x01
90 #define RB_USB_IE_DETECT 0x01
91 #define RB_USB_IE_TRANS 0x02
92 #define RB_USB_IE_SUSPEND 0x04
93 #define RB_USB_IE_SOF 0x08
94 #define RB_USB_IE_FIFOOV 0x10
95
96 #ifdef SOC_SERIES_CH569
97 #define RB_USB_IE_SETUPACT 0x20
98 #define RB_USB_IE_ISOACT 0x40
99 #define RB_USB_IE_DEV_NAK 0x80
100 #else
101 #define RB_USB_IE_DEV_NAK 0x40
102 #define RB_USB_IE_DEV_SOF 0x80
103 #endif
104
105 union _usb_suspend
106 {
107 uint8_t reg;
108 struct
109 {
110 uint8_t resv_0 : 1;
111 uint8_t dev_wakeup : 1; // RW, Remote wake-up control bit
112 uint8_t resv_2 : 6;
113 };
114 };
115 #define RB_DEV_WAKEUP 0x02
116
117 union _usb_spd_type
118 {
119 uint8_t reg;
120 struct
121 {
122 uint8_t speed_mask : 2; // RO, Actual transfer speed
123 uint8_t resv_2 : 6;
124 };
125 };
126 #define RB_USBSPEED_MASK 0x03 // same USBHS_FULL_SPEED...
127
128 union _usb_mis_st
129 {
130 uint8_t reg;
131 struct
132 {
133 uint8_t split_en : 1; // RO, SPLIT packet transmission enabled, HOST mode
134 uint8_t attach : 1; // RO, USB device connection status bit, HOST mode
135 uint8_t bus_suspend : 1; // RO, USB suspend status bit
136 uint8_t bus_reset : 1; // RO, USB bus reset status bit
137 uint8_t fifo_rdy : 1; // RO, USB receive FIFO data ready status bit
138 uint8_t sie_free : 1; // RO, Free status bit of USB protocol processor
139 uint8_t sof_act : 1; // RO, SOF packet transfer status bit, HOST mode
140 uint8_t sof_pres : 1; // RO, SOF packet presage status bit, HOST mode
141 };
142 };
143 #define RB_HOST_SPLIT_EN 0x01
144 #define RB_USB_ATTACH 0x02
145 #define RB_USBBUS_SUSPEND 0x04
146 #define RB_USBBUS_RESET 0x08
147 #define RB_USB_FIFO_RDY 0x10
148 #define RB_USB_SIE_FREE 0x20
149 #define RB_USB_SOF_ACT 0x40
150 #define RB_USB_SOF_PRES 0x80
151
152 union _usb_int_fg
153 {
154 uint8_t reg;
155 struct
156 {
157 uint8_t busrst : 1; // RW1, USB bus reset event IF, DEVICE mode
158 uint8_t transfer : 1; // RW1, USB transmission complete interrupt flag
159 uint8_t suspend : 1; // RW1, USB bus suspend/wake-up event IF
160 uint8_t hst_sof : 1; // RW1, SOF timing interrupt flag bit, HOST mode
161 uint8_t fifoov : 1; // RW1, USB FIFO overflow interrupt flag
162 uint8_t setupact : 1; // RW1, SETUP transaction complete IF (CH569)
163 uint8_t isoact : 1; // RW1, ISOchronous token received IF (CH569)
164 uint8_t resv_7 : 1;
165 };
166 struct
167 {
168 uint8_t detect : 1; // RW1, USB device connect/disconnect IF, HOST mode
169 uint8_t stuff_1 : 7;
170 };
171 };
172 #define RB_USB_IF_BUSRST 0x01
173 #define RB_USB_IF_DETECT 0x01
174 #define RB_USB_IF_TRANSFER 0x02
175 #define RB_USB_IF_SUSPEND 0x04
176 #define RB_USB_IF_HST_SOF 0x08
177 #define RB_USB_IF_FIFOOV 0x10
178 #define RB_USB_IF_SETUPACT 0x20
179 #define RB_USB_IF_ISOACT 0x40
180
181 union _usb_int_st
182 {
183 uint8_t reg;
184 struct
185 {
186 uint8_t host_res_mask : 4; // RO, Current response PID, HOST mode
187 uint8_t dev_token_mask : 2; // RO, Current token PID, DEVICE mode
188 uint8_t st_togok : 1; // RO, Current transmit DATA0/1 sync state
189 uint8_t st_nak : 1; // RO, NAK response status bit, DEVICE mode
190 };
191 struct
192 {
193 uint8_t dev_endp_mask : 4; // RO, Current endpoint number, DEVICE mode
194 uint8_t stuff_4 : 4;
195 };
196 };
197 #define RB_HOST_RES_MASK 0x0f
198 #define RB_DEV_ENDP_MASK 0x0f
199 #define RB_DEV_TOKEN_MASK 0x30
200 #define RB_USB_ST_TOGOK 0x40
201 #define RB_USB_ST_NAK 0x80
202
203 #define DEV_TOKEN_OUT 0
204 #define DEV_TOKEN_SOF 1
205 #define DEV_TOKEN_IN 2
206 #define DEV_TOKEN_SETUP 3 // CH567/CH568
207
208 #define RB_DEV_TOKEN_OUT (DEV_TOKEN_OUT << 4)
209 #define RB_DEV_TOKEN_SOF (DEV_TOKEN_SOF << 4)
210 #define RB_DEV_TOKEN_IN (DEV_TOKEN_IN << 4)
211
212 /*
213 * RB_UEPn_ RB_UEPn_ RB_UEPn_ R32_UEPn_DMA as starting address, low to high
214 * RX_EN TX_EN BUF_MOD
215 * 0 0 x Endpoint is disabled, UEPn_DMA not used
216 * 1 0 0 1st address of RX (OUT) buffer is R32_UEPn_RX_DMA
217 * 1 0 1 RB_UEP_R_TOG_MASK=0, use R32_UEPn_RX_DMA
218 * RB_UEP_R_TOG_MASK=1, use R32_UEPn_TX_DMA
219 * 0 1 0 1st address of TX (IN) buffer is R32_UEPn_TX_DMA
220 * 0 1 1 RB_UEP_T_TOG_MASK=0, use R32_UEPn_TX_DMA
221 * RB_UEP_T_TOG_MASK=1, use R32_UEPn_RX_DMA
222 */
223 #define RB_UEP_BUF_MOD 0x01
224 #define RB_UEP_TX_EN 0x04
225 #define RB_UEP_RX_EN 0x08
226
227 /* UEP_MOD offset 0 */
228 #define RB_UEP4_BUF_MOD 0x01
229 #define RB_UEP4_TX_EN 0x04
230 #define RB_UEP4_RX_EN 0x08
231 #define RB_UEP1_BUF_MOD 0x10
232 #define RB_UEP1_TX_EN 0x40
233 #define RB_UEP1_RX_EN 0x80
234
235 /* UEP_MOD offset 1 */
236 #define RB_UEP2_BUF_MOD 0x01
237 #define RB_UEP2_TX_EN 0x04
238 #define RB_UEP2_RX_EN 0x08
239 #define RB_UEP3_BUF_MOD 0x10
240 #define RB_UEP3_TX_EN 0x40
241 #define RB_UEP3_RX_EN 0x80
242
243 /* UEP_MOD offset 2 */
244 #define RB_UEP5_BUF_MOD 0x01
245 #define RB_UEP5_TX_EN 0x04
246 #define RB_UEP5_RX_EN 0x08
247 #define RB_UEP6_BUF_MOD 0x10
248 #define RB_UEP6_TX_EN 0x40
249 #define RB_UEP6_RX_EN 0x80
250
251 /* UEP_MOD offset 3 */
252 #define RB_UEP7_BUF_MOD 0x01
253 #define RB_UEP7_TX_EN 0x04
254 #define RB_UEP7_RX_EN 0x08
255
256 /* each nibble is an ep index map : {hi_lo_nibble(1), reg_offset(3)} */
257 #define UEP_MOD_MAP 0x3a209180
258 #define uep_mod_offset(ep) (((UEP_MOD_MAP >> (ep * 4)) & 3))
259 #define uep_mod_shift(ep) (((UEP_MOD_MAP >> (ep * 4)) & 8) ? 4 : 0)
260
261 union _uep_rt_ctrl
262 {
263 uint8_t reg;
264 struct
265 {
266 uint8_t res_mask : 2; // RW, response control bits
267 uint8_t res_no : 1; // RW, not expecting response
268 uint8_t tog_mask : 2; // RW, transmit/expect DATAx
269 uint8_t autotog : 1; // RW, auto DATAx toggle (not for EP0)
270 uint8_t resv_6 : 2;
271 };
272 };
273 #define RB_UEP_RES_MASK 0x03
274 #define RB_UEP_RES_NO 0x04
275 #define RB_UEP_TOG_MASK 0x18
276 #define RB_UEP_AUTOTOG 0x20
277
278 #define UEP_RES_ACK 0
279 #define UEP_RES_NYET 1
280 #define UEP_RES_NAK 2
281 #define UEP_RES_STALL 3
282
283 #define UEP_TOG_DATA0 0
284 #define UEP_TOG_DATA1 1
285 #define UEP_TOG_DATA2 2
286 #define UEP_TOG_MDATA 3
287
288 #define RB_UEP_RES_ACK (UEP_RES_ACK << 0)
289 #define RB_UEP_RES_NYET (UEP_RES_NYET << 0)
290 #define RB_UEP_RES_NAK (UEP_RES_NAK << 0)
291 #define RB_UEP_RES_STALL (UEP_RES_STALL << 0)
292
293 #define RB_UEP_TOG_DATA0 (UEP_TOG_DATA0 << 3)
294 #define RB_UEP_TOG_DATA1 (UEP_TOG_DATA1 << 3)
295 #define RB_UEP_TOG_DATA2 (UEP_TOG_DATA2 << 3)
296 #define RB_UEP_TOG_MDATA (UEP_TOG_MDATA << 3)
297
298 union _uh_rt_ctrl
299 {
300 uint8_t reg;
301 struct
302 {
303 uint8_t res_mask : 2; // RW, response control bits
304 uint8_t res_no : 1; // RW, not expecting response
305 uint8_t tog_mask : 2; // RW, expected DATAx
306 uint8_t autotog : 1; // RW, auto DATAx toggle
307 uint8_t data_no : 1; // RW, not expecting data
308 uint8_t resv_7 : 1;
309 };
310 };
311 #define RB_UH_RES_MASK 0x03
312 #define RB_UH_RES_NO 0x04
313 #define RB_UH_TOG_MASK 0x18
314 #define RB_UH_AUTOTOG 0x20
315 #define RB_UH_DATA_NO 0x40
316
317 #define UH_RES_ACK 0
318 #define UH_RES_NYET 1
319 #define UH_RES_NAK 2
320 #define UH_RES_STALL 3
321
322 #define UH_TOG_DATA0 0
323 #define UH_TOG_DATA1 1
324 #define UH_TOG_DATA2 2
325 #define UH_TOG_MDATA 3
326
327 #define RB_UH_RES_ACK (UH_RES_ACK << 0)
328 #define RB_UH_RES_NYET (UH_RES_NYET << 0)
329 #define RB_UH_RES_NAK (UH_RES_NAK << 0)
330 #define RB_UH_RES_STALL (UH_RES_STALL << 0)
331
332 #define RB_UH_TOG_DATA0 (UH_TOG_DATA0 << 3)
333 #define RB_UH_TOG_DATA1 (UH_TOG_DATA1 << 3)
334 #define RB_UH_TOG_DATA2 (UH_TOG_DATA2 << 3)
335 #define RB_UH_TOG_MDATA (UH_TOG_MDATA << 3)
336
337 union _uhost_ctrl
338 {
339 uint8_t reg;
340 struct
341 {
342 uint8_t bus_reset : 1; // RW, USB host transmit bus reset signal
343 uint8_t bus_suspend : 1; // RW, USB host transmit suspend signal
344 uint8_t bus_resume : 1; // RW, wake up device when bus suspended
345 uint8_t resv_3 : 4;
346 uint8_t autosof_en : 1; // RW, Auto generate SOF packet enable (CH569)
347 };
348 };
349 #define RB_UH_BUS_RESET 0x01
350 #define RB_UH_BUS_SUSPEND 0x02
351 #define RB_UH_BUS_RESUME 0x04
352 #define RB_UH_AUTOSOF_EN 0x80
353
354 union _uh_ep_mod
355 {
356 uint8_t reg;
357 struct
358 {
359 uint8_t rbuf_mod : 1; // RW, CH567/CH568 only
360 uint8_t resv_1 : 2;
361 uint8_t rx_en : 1; // RW, enable HOST receiver (IN)
362 uint8_t tbuf_mod : 1; // RW, CH567/CH568 only
363 uint8_t resv_5 : 1;
364 uint8_t tx_en : 1; // RW, enable HOST transmitter (SETUP/OUT)
365 uint8_t resv_7 : 1;
366 };
367 };
368 #define RB_UH_RBUF_MOD 0x01
369 #define RB_UH_RX_EN 0x08
370 #define RB_UH_TBUF_MOD 0x10
371 #define RB_UH_TX_EN 0x40
372
373 union _uh_ep_pid
374 {
375 uint16_t reg;
376 struct
377 {
378 uint8_t epnum_mask : 4; // RW, Set endpoint number of the target device
379 uint8_t token_mask : 4; // RW, Set the token PID packet identification
380 uint8_t resv;
381 };
382 };
383 #define RB_UH_EPNUM_MASK 0x0f
384 #define RB_UH_TOKEN_MASK 0xf0
385
386 #ifndef SOC_SERIES_CH569
387 union _uh_setup
388 {
389 uint8_t reg;
390 struct
391 {
392 uint8_t resv_0 : 6;
393 uint8_t sof_en : 1; // WO, Auto generate SOF packet enable
394 uint8_t resv_7 : 1;
395 };
396 };
397 #define RB_UH_SOF_EN 0x40
398 #endif
399
400 /*
401 * USBHS Global Registers :
402 *
403 * 0x00 R8_USB_CTRL: USB control register
404 * 0x02 R8_USB_INT_EN: USB interrupt enable register
405 * 0x03 R8_USB_DEV_AD: USB addresss register
406 * 0x04 R16_USB_FRAME_NO: USBHS frame number register
407 * 0x06 R8_USB_SUSPEND: USB suspend control register
408 * 0x08 R8_USB_SPD_TYPE: USB current speed type register
409 * 0x09 R8_USB_MIS_ST: USB miscellaneous status register
410 * 0x0a R8_USB_INT_FG: USB interrupt flag register
411 * 0x0b R8_USB_INT_ST: USB interrpt status register
412 * 0x0c R16_USB_RX_LEN: USB reception length register
413 */
414
415 /*
416 * CH565/CH569 USBHS DEVICE Related Registers :
417 *
418 * 0x10 R8_UEP4_1_MOD: Endpoint 1(9) / 4(8/12) mode control register
419 * 0x11 R8_UEP2_3_MOD: Endpoint 2(10) / 3(11) mode control register
420 * 0x12 R8_UEP5_6_MOD: Endpoint 5(13) / 6(14) mode control register
421 * 0x13 R8_UEP7_MOD: Endpoint 7(15) mode control register
422 * 0x14 R32_UEP0_RT_DMA: Start address of endpoint0 buffer
423 * 0x18 R32_UEP1_RX_DMA: Start address of endpoint 1(9) receive buffer
424 * 0x1c R32_UEP2_RX_DMA: Start address of endpoint 2(10) receive buffer
425 * 0x20 R32_UEP3_RX_DMA: Start address of endpoint 3(11) receive buffer
426 * 0x24 R32_UEP4_RX_DMA: Start address of endpoint 4(8/12) receive buffer
427 * 0x28 R32_UEP5_RX_DMA: Start address of endpoint 5(13) receive buffer
428 * 0x2c R32_UEP6_RX_DMA: Start address of endpoint 6(14) receive buffer
429 * 0x30 R32_UEP7_RX_DMA: Start address of endpoint 7(15) receive buffer
430 * 0x34 R32_UEP1_TX_DMA: Start address of endpoint 1(9) transmit buffer
431 * 0x38 R32_UEP2_TX_DMA: Start address of endpoint 2(10) transmit buffer
432 * 0x3c R32_UEP3_TX_DMA: Start address of endpoint 3(11) transmit buffer
433 * 0x40 R32_UEP4_TX_DMA: Start address of endpoint 4(8/12) transmit buffer
434 * 0x44 R32_UEP5_TX_DMA: Start address of endpoint 5(13) transmit buffer
435 * 0x48 R32_UEP6_TX_DMA: Start address of endpoint 6(14) transmit buffer
436 * 0x4c R32_UEP7_TX_DMA: Start address of endpoint 7(15) transmit buffer
437 * 0x50 R16_UEP0_MAX_LEN: Endpoint 0 receive maximum length packet register
438 * 0x54 R16_UEP1_MAX_LEN: Endpoint 1(9) receive maximum length packet register
439 * 0x58 R16_UEP2_MAX_LEN: Endpoint 2(10) receive maximum length packet register
440 * 0x5c R16_UEP3_MAX_LEN: Endpoint 3(11) receive maximum length packet register
441 * 0x60 R16_UEP4_MAX_LEN: Endpoint 4(8/12) receive maximum length packet register
442 * 0x64 R16_UEP5_MAX_LEN: Endpoint 5(13) receive maximum length packet register
443 * 0x68 R16_UEP6_MAX_LEN: Endpoint 6(14) receive maximum length packet register
444 * 0x6c R16_UEP7_MAX_LEN: Endpoint 7(15) receive maximum length packet register
445 * 0x70 R16_UEP0_T_LEN: Endpoint 0 transmission length register
446 * 0x72 R8_UEP0_TX_CTRL: Endpoint 0 transmit control register
447 * 0x73 R8_UEP0_RX_CTRL: Endpoint 0 receive control register
448 * 0x74 R16_UEP1_T_LEN: Endpoint 1(9) transmission length register
449 * 0x76 R8_UEP1_TX_CTRL: Endpoint 1(9) transmit control register
450 * 0x77 R8_UEP1_RX_CTRL: Endpoint 1(9) receive control register
451 * 0x78 R16_UEP2_T_LEN: Endpoint 2(10) transmission length register
452 * 0x7a R8_UEP2_TX_CTRL: Endpoint 2(10) transmit control register
453 * 0x7b R8_UEP2_RX_CTRL: Endpoint 2(10) receive control register
454 * 0x7c R16_UEP3_T_LEN: Endpoint 3(11) transmission length register
455 * 0x7e R8_UEP3_TX_CTRL: Endpoint 3(11) transmit control register
456 * 0x7f R8_UEP3_RX_CTRL: Endpoint 3(11) receive control register
457 * 0x80 R16_UEP4_T_LEN: Endpoint 4(8/12) transmission length register
458 * 0x82 R8_UEP4_TX_CTRL: Endpoint 4(8/12) transmit control register
459 * 0x83 R8_UEP4_RX_CTRL: Endpoint 4(8/12) receive control register
460 * 0x84 R16_UEP5_T_LEN: Endpoint 5(13) transmission length register
461 * 0x86 R8_UEP5_TX_CTRL: Endpoint 5(13) transmit control register
462 * 0x87 R8_UEP5_RX_CTRL: Endpoint 5(13) receive control register
463 * 0x88 R16_UEP6_T_LEN: Endpoint 6(14) transmission length register
464 * 0x8a R8_UEP6_TX_CTRL: Endpoint 6(14) transmit control register
465 * 0x8b R8_UEP6_RX_CTRL: Endpoint 6(14) receive control register
466 * 0x8c R16_UEP7_T_LEN: Endpoint 7(15) transmission length register
467 * 0x8e R8_UEP7_TX_CTRL: Endpoint 7(15) transmit control register
468 * 0x8f R8_UEP7_RX_CTRL: Endpoint 7(15) receive control register
469 *
470 * CH567/CH568 USBHS DEVICE Related Registers :
471 *
472 * 0x10 UEP4_1_MOD: Endpoint 1/4 mode control register
473 * 0x11 UEP2_3_MOD: Endpoint 2/3 mode control register
474 * 0x14 UEP0_DMA: Endpoint 0 DMA buffer start address
475 * 0x18 UEP1_DMA: Endpoint 1 DMA buffer start address
476 * 0x1c UEP2_DMA: Endpoint 2 DMA buffer start address
477 * 0x20 UEP3_DMA: Endpoint 3 DMA buffer start address
478 * 0x24 UEP0_MAX_LEN: Endpoint 0 receive maximum length packet register
479 * 0x28 UEP1_MAX_LEN: Endpoint 1 receive maximum length packet register
480 * 0x2c UEP2_MAX_LEN: Endpoint 2 receive maximum length packet register
481 * 0x30 UEP3_MAX_LEN: Endpoint 3 receive maximum length packet register
482 * 0x34 UEP4_MAX_LEN: Endpoint 4 receive maximum length packet register
483 * 0x38 UEP0_T_LEN: Endpoint 0 transmission length register
484 * 0x3a UEP0_TX_CTRL: Endpoint 0 transmit control register
485 * 0x3b UEP0_RX_CTRL: Endpoint 0 receive control register
486 * 0x3c UEP1_T_LEN: Endpoint 1 transmission length register
487 * 0x3e UEP1_TX_CTRL: Endpoint 1 transmit control register
488 * 0x3f UEP1_RX_CTRL: Endpoint 1 receive control register
489 * 0x40 UEP2_T_LEN: Endpoint 2 transmission length register
490 * 0x42 UEP2_TX_CTRL: Endpoint 2 transmit control register
491 * 0x43 UEP2_RX_CTRL: Endpoint 2 receive control register
492 * 0x44 UEP2_T_LEN: Endpoint 3 transmission length register
493 * 0x46 UEP2_TX_CTRL: Endpoint 3 transmit control register
494 * 0x47 UEP2_RX_CTRL: Endpoint 3 receive control register
495 * 0x48 UEP4_T_LEN: Endpoint 4 transmission length register
496 * 0x4a UEP4_TX_CTRL: Endpoint 4 transmit control register
497 * 0x4b UEP4_RX_CTRL: Endpoint 4 receive control register
498 */
499
500 /*
501 * CH565/CH569 USBHS HOST Related Registers :
502 *
503 * 0x01 R8_UHOST_CTRL: USB host control register
504 * 0x11 R8_UH_EP_MOD: USB host endpoint mode register
505 * 0x1c R32_UH_RX_DMA: USB host receive buffer start address
506 * 0x3c R32_UH_TX_DMA: USB host transmit buffer start address
507 * 0x58 R16_UH_MAX_LEN: USB host reception maximum length packet register
508 * 0x78 R16_UH_EP_PID: USB host token setting register
509 * 0x7b R8_UH_RX_CTRL: USB host reception endpoint control register
510 * 0x7c R16_UH_TX_LEN: USB host transmission length register
511 * 0x7e R8_UH_TX_CTRL: USB host transmission endpoint control register
512 * 0x80 R16_UH_SPLIT_DATA: USB host transmit SPLIT packet data
513 *
514 * CH567/CH568 USBHS HOST Related Registers :
515 *
516 * 0x01 UHOST_CTRL: USB host control register
517 * 0x11 UH_EP_MOD: USB host endpoint mode register
518 * 0x1c UH_RX_DMA: USB host receive buffer start address
519 * 0x20 UH_TX_DMA: USB host transmit buffer start address
520 * 0x2c UH_RX_MAX_LEN: USB host reception maximum length packet register
521 * 0x3e UH_SETUP: USB host aux config register
522 * 0x40 UH_EP_PID: USB host token setting register
523 * 0x43 UH_RX_CTRL: USB host reception endpoint control register
524 * 0x44 UH_TX_LEN: USB host transmission length register
525 * 0x46 UH_TX_CTRL: USB host transmission endpoint control register
526 * 0x48 UH_SPLIT_DATA: USB host transmit SPLIT packet data
527 */
528 struct usbhs_registers
529 {
530 union
531 {
532 /* USB Global Registers */
533 struct
534 {
535 union _usb_ctrl CTRL;
536 uint8_t stuff_01;
537 union _usb_int_en INT_EN;
538 uint8_t DEV_AD;
539 uint16_t FRAME_NO;
540 union _usb_suspend SUSPEND;
541 uint8_t resv_07;
542 union _usb_spd_type SPD_TYPE;
543 union _usb_mis_st MIS_ST;
544 union _usb_int_fg INT_FG;
545 union _usb_int_st INT_ST;
546 uint16_t RX_LEN;
547 };
548
549 /* USB DEVICE Related Registers */
550 struct
551 {
552 uint32_t stuff_gr[4];
553 union
554 {
555 uint8_t UEP_MOD[4];
556 uint32_t R32_UEP_MOD;
557 };
558 #ifdef SOC_SERIES_CH569
559 union
560 {
561 struct
562 {
563 uint32_t UEP0_RT_DMA;
564 uint32_t stuff_rt[14];
565 };
566 struct
567 {
568 uint32_t UEP_RX_DMA[8]; // UEP_RX_DMA[0] NOT exist
569 uint32_t stuff_rx[7];
570 };
571 struct
572 {
573 uint32_t stuff_tx[7];
574 uint32_t UEP_TX_DMA[8]; // UEP_TX_DMA[0] NOT exist
575 };
576 };
577 #else
578 struct
579 {
580 uint16_t reg;
581 uint16_t resv;
582 } UEP_DMA[4];
583 #endif
584 struct
585 {
586 uint16_t reg;
587 uint16_t resv;
588 } UEP_MAX_LEN[UEP_ADDRESS_MAX + 1];
589 struct
590 {
591 uint16_t t_len; // MSB 5 bits are fixed to 0
592 union _uep_rt_ctrl TX_CTRL;
593 union _uep_rt_ctrl RX_CTRL;
594 } UEP_CTRL[UEP_ADDRESS_MAX + 1];
595 };
596
597 /* USB HOST Related Registers */
598 #ifdef SOC_SERIES_CH569
599 struct
600 {
601 uint8_t stuff_00;
602 union _uhost_ctrl UHOST_CTRL;
603 uint8_t stuff_02[15];
604 union _uh_ep_mod UH_EP_MOD;
605 uint8_t stuff_12[10];
606 uint32_t UH_RX_DMA;
607 uint32_t stuff_20[7];
608 uint32_t UH_TX_DMA;
609 uint32_t stuff_40[6];
610 uint16_t UH_MAX_LEN;
611 uint16_t stuff_5a[15];
612 union _uh_ep_pid UH_EP_PID;
613 uint8_t stuff_7a;
614 union _uh_rt_ctrl UH_RX_CTRL;
615 uint16_t UH_TX_LEN;
616 union _uh_rt_ctrl UH_TX_CTRL;
617 uint8_t stuff_7f;
618 uint16_t UH_SPLIT_DATA;
619 uint16_t stuff_82[7];
620 };
621 #else
622 struct
623 {
624 uint8_t stuff_00;
625 union _uhost_ctrl UHOST_CTRL;
626 uint8_t stuff_02[15];
627 union _uh_ep_mod UH_EP_MOD;
628 uint8_t stuff_12[10];
629 uint32_t UH_RX_DMA;
630 uint32_t UH_TX_DMA;
631 uint32_t stuff_24[2];
632 uint16_t UH_MAX_LEN;
633 uint16_t stuff_2e[8];
634 uint8_t UH_SETUP;
635 uint8_t stuff_3f;
636 union _uh_ep_pid UH_EP_PID;
637 uint8_t stuff_42;
638 union _uh_rt_ctrl UH_RX_CTRL;
639 uint16_t UH_TX_LEN;
640 union _uh_rt_ctrl UH_TX_CTRL;
641 uint8_t stuff_47;
642 uint16_t UH_SPLIT_DATA;
643 uint16_t stuff_4a;
644 };
645 #endif
646 };
647 } __packed;
648
649 #ifdef SOC_SERIES_CH569
650 CHECK_STRUCT_SIZE(struct usbhs_registers, 0x90);
651 #else
652 CHECK_STRUCT_SIZE(struct usbhs_registers, 0x4c);
653 #endif
654
_uep_mod_set(volatile struct usbhs_registers * usbhs,int ep_idx,uint8_t mod)655 rt_inline void _uep_mod_set(volatile struct usbhs_registers *usbhs,
656 int ep_idx, uint8_t mod)
657 {
658 int reg_n = uep_mod_offset(ep_idx);
659 int shift = uep_mod_shift(ep_idx);
660 int mask = 0x0f << shift;
661
662 /* ep_idx must be 1 ~ UEP_ADDRESS_MAX */
663 usbhs->UEP_MOD[reg_n] = (usbhs->UEP_MOD[reg_n] & ~mask) | (mod << shift);
664 }
665
_uep_mod_get(volatile struct usbhs_registers * usbhs,int ep_idx)666 rt_inline uint8_t _uep_mod_get(volatile struct usbhs_registers *usbhs, int ep_idx)
667 {
668 int reg_n = uep_mod_offset(ep_idx);
669 int shift = uep_mod_shift(ep_idx);
670
671 /* ep_idx should be 1 ~ UEP_ADDRESS_MAX */
672 return (usbhs->UEP_MOD[reg_n] >> shift) & 0x0f;
673 }
674
675 #ifdef __cplusplus
676 }
677 #endif
678
679 #endif
680