1 /* 2 * Copyright (c) 2024, sakumisu 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef __USB_KINETIS_REG_H__ 7 #define __USB_KINETIS_REG_H__ 8 9 #define __I volatile const /* Define "read-only" permission */ 10 #define __IO volatile /* Define "read-write" permission */ 11 12 /* ---------------------------------------------------------------------------- 13 -- USB Peripheral Access Layer 14 ---------------------------------------------------------------------------- */ 15 16 /*! 17 * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer 18 * @{ 19 */ 20 21 /** USB - Register Layout Typedef */ 22 typedef struct { 23 __I uint8_t PERID; /**< Peripheral ID, offset: 0x0 */ 24 uint8_t RESERVED_0[3]; 25 __I uint8_t IDCOMP; /**< Peripheral ID Complement, offset: 0x4 */ 26 uint8_t RESERVED_1[3]; 27 __I uint8_t REV; /**< Peripheral Revision, offset: 0x8 */ 28 uint8_t RESERVED_2[3]; 29 __I uint8_t ADDINFO; /**< Peripheral Additional Information, offset: 0xC */ 30 uint8_t RESERVED_3[3]; 31 __IO uint8_t OTGISTAT; /**< OTG Interrupt Status, offset: 0x10 */ 32 uint8_t RESERVED_4[3]; 33 __IO uint8_t OTGICR; /**< OTG Interrupt Control, offset: 0x14 */ 34 uint8_t RESERVED_5[3]; 35 __I uint8_t OTGSTAT; /**< OTG Status, offset: 0x18 */ 36 uint8_t RESERVED_6[3]; 37 __IO uint8_t OTGCTL; /**< OTG Control, offset: 0x1C */ 38 uint8_t RESERVED_7[99]; 39 __IO uint8_t ISTAT; /**< Interrupt Status, offset: 0x80 */ 40 uint8_t RESERVED_8[3]; 41 __IO uint8_t INTEN; /**< Interrupt Enable, offset: 0x84 */ 42 uint8_t RESERVED_9[3]; 43 __IO uint8_t ERRSTAT; /**< Error Interrupt Status, offset: 0x88 */ 44 uint8_t RESERVED_10[3]; 45 __IO uint8_t ERREN; /**< Error Interrupt Enable, offset: 0x8C */ 46 uint8_t RESERVED_11[3]; 47 __I uint8_t STAT; /**< Status, offset: 0x90 */ 48 uint8_t RESERVED_12[3]; 49 __IO uint8_t CTL; /**< Control, offset: 0x94 */ 50 uint8_t RESERVED_13[3]; 51 __IO uint8_t ADDR; /**< Address, offset: 0x98 */ 52 uint8_t RESERVED_14[3]; 53 __IO uint8_t BDTPAGE1; /**< BDT Page 1, offset: 0x9C */ 54 uint8_t RESERVED_15[3]; 55 __I uint8_t FRMNUML; /**< Frame Number Register Low, offset: 0xA0 */ 56 uint8_t RESERVED_16[3]; 57 __I uint8_t FRMNUMH; /**< Frame Number Register High, offset: 0xA4 */ 58 uint8_t RESERVED_17[3]; 59 __IO uint8_t TOKEN; /**< Token, offset: 0xA8 */ 60 uint8_t RESERVED_18[3]; 61 __IO uint8_t SOFTHLD; /**< SOF Threshold, offset: 0xAC */ 62 uint8_t RESERVED_19[3]; 63 __IO uint8_t BDTPAGE2; /**< BDT Page 2, offset: 0xB0 */ 64 uint8_t RESERVED_20[3]; 65 __IO uint8_t BDTPAGE3; /**< BDT Page 3, offset: 0xB4 */ 66 uint8_t RESERVED_21[11]; 67 struct { /* offset: 0xC0, array step: 0x4 */ 68 __IO uint8_t ENDPT; /**< Endpoint Control, array offset: 0xC0, array step: 0x4 */ 69 uint8_t RESERVED_0[3]; 70 } ENDPOINT[16]; 71 } KINETIS_TypeDef; 72 73 /* ---------------------------------------------------------------------------- 74 -- USB Register Masks 75 ---------------------------------------------------------------------------- */ 76 77 /*! 78 * @addtogroup USB_Register_Masks USB Register Masks 79 * @{ 80 */ 81 82 /*! @name PERID - Peripheral ID */ 83 /*! @{ */ 84 85 #define USB_PERID_ID_MASK (0x3FU) 86 #define USB_PERID_ID_SHIFT (0U) 87 /*! ID - Peripheral Identification */ 88 #define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_PERID_ID_SHIFT)) & USB_PERID_ID_MASK) 89 /*! @} */ 90 91 /*! @name IDCOMP - Peripheral ID Complement */ 92 /*! @{ */ 93 94 #define USB_IDCOMP_NID_MASK (0x3FU) 95 #define USB_IDCOMP_NID_SHIFT (0U) 96 /*! NID - Negative Peripheral ID */ 97 #define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x)) << USB_IDCOMP_NID_SHIFT)) & USB_IDCOMP_NID_MASK) 98 /*! @} */ 99 100 /*! @name REV - Peripheral Revision */ 101 /*! @{ */ 102 103 #define USB_REV_REV_MASK (0xFFU) 104 #define USB_REV_REV_SHIFT (0U) 105 /*! REV - Revision */ 106 #define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x)) << USB_REV_REV_SHIFT)) & USB_REV_REV_MASK) 107 /*! @} */ 108 109 /*! @name ADDINFO - Peripheral Additional Information */ 110 /*! @{ */ 111 112 #define USB_ADDINFO_IEHOST_MASK (0x1U) 113 #define USB_ADDINFO_IEHOST_SHIFT (0U) 114 /*! IEHOST - Host Mode Enable 115 * 0b0..Disabled 116 * 0b1..Enabled 117 */ 118 #define USB_ADDINFO_IEHOST(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IEHOST_SHIFT)) & USB_ADDINFO_IEHOST_MASK) 119 /*! @} */ 120 121 /*! @name OTGISTAT - OTG Interrupt Status */ 122 /*! @{ */ 123 124 #define USB_OTGISTAT_LINE_STATE_CHG_MASK (0x20U) 125 #define USB_OTGISTAT_LINE_STATE_CHG_SHIFT (5U) 126 /*! LINE_STATE_CHG - Line State Change Interrupt Flag 127 * 0b0..Interrupt did not occur 128 * 0b1..Interrupt occurred 129 * 0b0..No effect 130 * 0b1..Clear the flag 131 */ 132 #define USB_OTGISTAT_LINE_STATE_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_LINE_STATE_CHG_SHIFT)) & USB_OTGISTAT_LINE_STATE_CHG_MASK) 133 134 #define USB_OTGISTAT_ONEMSEC_MASK (0x40U) 135 #define USB_OTGISTAT_ONEMSEC_SHIFT (6U) 136 /*! ONEMSEC - One Millisecond Timer Timeout Flag 137 * 0b0..Not timed out 138 * 0b1..Timed out 139 * 0b0..No effect 140 * 0b1..Clear the flag 141 */ 142 #define USB_OTGISTAT_ONEMSEC(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_ONEMSEC_SHIFT)) & USB_OTGISTAT_ONEMSEC_MASK) 143 /*! @} */ 144 145 /*! @name OTGICR - OTG Interrupt Control */ 146 /*! @{ */ 147 148 #define USB_OTGICR_LINESTATEEN_MASK (0x20U) 149 #define USB_OTGICR_LINESTATEEN_SHIFT (5U) 150 /*! LINESTATEEN - Line State Change Interrupt Enable 151 * 0b0..Disable 152 * 0b1..Enable 153 */ 154 #define USB_OTGICR_LINESTATEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_LINESTATEEN_SHIFT)) & USB_OTGICR_LINESTATEEN_MASK) 155 156 #define USB_OTGICR_ONEMSECEN_MASK (0x40U) 157 #define USB_OTGICR_ONEMSECEN_SHIFT (6U) 158 /*! ONEMSECEN - 1-Millisecond Interrupt Enable 159 * 0b0..Disable 160 * 0b1..Enable 161 */ 162 #define USB_OTGICR_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_ONEMSECEN_SHIFT)) & USB_OTGICR_ONEMSECEN_MASK) 163 /*! @} */ 164 165 /*! @name OTGSTAT - OTG Status */ 166 /*! @{ */ 167 168 #define USB_OTGSTAT_LINESTATESTABLE_MASK (0x20U) 169 #define USB_OTGSTAT_LINESTATESTABLE_SHIFT (5U) 170 /*! LINESTATESTABLE - Line State Stable 171 * 0b0..Unstable 172 * 0b1..Stable 173 */ 174 #define USB_OTGSTAT_LINESTATESTABLE(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_LINESTATESTABLE_SHIFT)) & USB_OTGSTAT_LINESTATESTABLE_MASK) 175 176 #define USB_OTGSTAT_ONEMSEC_MASK (0x40U) 177 #define USB_OTGSTAT_ONEMSEC_SHIFT (6U) 178 /*! ONEMSEC - Reserved for 1 ms count */ 179 #define USB_OTGSTAT_ONEMSEC(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ONEMSEC_SHIFT)) & USB_OTGSTAT_ONEMSEC_MASK) 180 /*! @} */ 181 182 /*! @name OTGCTL - OTG Control */ 183 /*! @{ */ 184 185 #define USB_OTGCTL_OTGEN_MASK (0x4U) 186 #define USB_OTGCTL_OTGEN_SHIFT (2U) 187 /*! OTGEN - On-The-Go Pullup and Pulldown Resistor Enable 188 * 0b0..If USBENSOFEN is 1 and HOSTMODEEN is 0 in the Control Register (CTL), then the D+ Data line pullup 189 * resistors are enabled. If HOSTMODEEN is 1, then the D+ and D- Data line pulldown resistors are engaged. 190 * 0b1..Uses the pullup and pulldown controls in this register. 191 */ 192 #define USB_OTGCTL_OTGEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_OTGEN_SHIFT)) & USB_OTGCTL_OTGEN_MASK) 193 194 #define USB_OTGCTL_DMLOW_MASK (0x10U) 195 #define USB_OTGCTL_DMLOW_SHIFT (4U) 196 /*! DMLOW - D- Data Line Pulldown Resistor Enable 197 * 0b0..Disable 198 * 0b1..Enable 199 */ 200 #define USB_OTGCTL_DMLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DMLOW_SHIFT)) & USB_OTGCTL_DMLOW_MASK) 201 202 #define USB_OTGCTL_DPLOW_MASK (0x20U) 203 #define USB_OTGCTL_DPLOW_SHIFT (5U) 204 /*! DPLOW - D+ Data Line pulldown Resistor Enable 205 * 0b0..Disable 206 * 0b1..Enable 207 */ 208 #define USB_OTGCTL_DPLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPLOW_SHIFT)) & USB_OTGCTL_DPLOW_MASK) 209 210 #define USB_OTGCTL_DPHIGH_MASK (0x80U) 211 #define USB_OTGCTL_DPHIGH_SHIFT (7U) 212 /*! DPHIGH - D+ Data Line Pullup Resistor Enable 213 * 0b0..Disable 214 * 0b1..Enable 215 */ 216 #define USB_OTGCTL_DPHIGH(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPHIGH_SHIFT)) & USB_OTGCTL_DPHIGH_MASK) 217 /*! @} */ 218 219 /*! @name ISTAT - Interrupt Status */ 220 /*! @{ */ 221 222 #define USB_ISTAT_USBRST_MASK (0x1U) 223 #define USB_ISTAT_USBRST_SHIFT (0U) 224 /*! USBRST - USB Reset Flag 225 * 0b0..Not detected 226 * 0b1..Detected 227 * 0b0..No effect 228 * 0b1..Clear the flag 229 */ 230 #define USB_ISTAT_USBRST(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_USBRST_SHIFT)) & USB_ISTAT_USBRST_MASK) 231 232 #define USB_ISTAT_ERROR_MASK (0x2U) 233 #define USB_ISTAT_ERROR_SHIFT (1U) 234 /*! ERROR - Error Flag 235 * 0b0..Error did not occur 236 * 0b1..Error occurred 237 * 0b0..No effect 238 * 0b1..Clear the flag 239 */ 240 #define USB_ISTAT_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ERROR_SHIFT)) & USB_ISTAT_ERROR_MASK) 241 242 #define USB_ISTAT_SOFTOK_MASK (0x4U) 243 #define USB_ISTAT_SOFTOK_SHIFT (2U) 244 /*! SOFTOK - Start Of Frame (SOF) Token Flag 245 * 0b0..Did not receive 246 * 0b1..Received 247 * 0b0..No effect 248 * 0b1..Clear the flag 249 */ 250 #define USB_ISTAT_SOFTOK(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SOFTOK_SHIFT)) & USB_ISTAT_SOFTOK_MASK) 251 252 #define USB_ISTAT_TOKDNE_MASK (0x8U) 253 #define USB_ISTAT_TOKDNE_SHIFT (3U) 254 /*! TOKDNE - Current Token Processing Flag 255 * 0b0..Not processed 256 * 0b1..Processed 257 * 0b0..No effect 258 * 0b1..Clear the flag 259 */ 260 #define USB_ISTAT_TOKDNE(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_TOKDNE_SHIFT)) & USB_ISTAT_TOKDNE_MASK) 261 262 #define USB_ISTAT_SLEEP_MASK (0x10U) 263 #define USB_ISTAT_SLEEP_SHIFT (4U) 264 /*! SLEEP - Sleep Flag 265 * 0b0..Interrupt did not occur 266 * 0b1..Interrupt occurred 267 * 0b0..No effect 268 * 0b1..Clear the flag 269 */ 270 #define USB_ISTAT_SLEEP(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SLEEP_SHIFT)) & USB_ISTAT_SLEEP_MASK) 271 272 #define USB_ISTAT_RESUME_MASK (0x20U) 273 #define USB_ISTAT_RESUME_SHIFT (5U) 274 /*! RESUME - Resume Flag 275 * 0b0..Interrupt did not occur 276 * 0b1..Interrupt occurred 277 * 0b0..No effect 278 * 0b1..Clear the flag 279 */ 280 #define USB_ISTAT_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_RESUME_SHIFT)) & USB_ISTAT_RESUME_MASK) 281 282 #define USB_ISTAT_ATTACH_MASK (0x40U) 283 #define USB_ISTAT_ATTACH_SHIFT (6U) 284 /*! ATTACH - Attach Interrupt Flag 285 * 0b0..Not detected 286 * 0b1..Detected 287 * 0b0..No effect 288 * 0b1..Clear the flag 289 */ 290 #define USB_ISTAT_ATTACH(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ATTACH_SHIFT)) & USB_ISTAT_ATTACH_MASK) 291 292 #define USB_ISTAT_STALL_MASK (0x80U) 293 #define USB_ISTAT_STALL_SHIFT (7U) 294 /*! STALL - Stall Interrupt Flag 295 * 0b0..Interrupt did not occur 296 * 0b1..Interrupt occurred 297 * 0b0..No effect 298 * 0b1..Clear the flag 299 */ 300 #define USB_ISTAT_STALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_STALL_SHIFT)) & USB_ISTAT_STALL_MASK) 301 /*! @} */ 302 303 /*! @name INTEN - Interrupt Enable */ 304 /*! @{ */ 305 306 #define USB_INTEN_USBRSTEN_MASK (0x1U) 307 #define USB_INTEN_USBRSTEN_SHIFT (0U) 308 /*! USBRSTEN - USBRST Interrupt Enable 309 * 0b0..Disable 310 * 0b1..Enable 311 */ 312 #define USB_INTEN_USBRSTEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_USBRSTEN_SHIFT)) & USB_INTEN_USBRSTEN_MASK) 313 314 #define USB_INTEN_ERROREN_MASK (0x2U) 315 #define USB_INTEN_ERROREN_SHIFT (1U) 316 /*! ERROREN - ERROR Interrupt Enable 317 * 0b0..Disable 318 * 0b1..Enable 319 */ 320 #define USB_INTEN_ERROREN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ERROREN_SHIFT)) & USB_INTEN_ERROREN_MASK) 321 322 #define USB_INTEN_SOFTOKEN_MASK (0x4U) 323 #define USB_INTEN_SOFTOKEN_SHIFT (2U) 324 /*! SOFTOKEN - SOFTOK Interrupt Enable 325 * 0b0..Disable 326 * 0b1..Enable 327 */ 328 #define USB_INTEN_SOFTOKEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SOFTOKEN_SHIFT)) & USB_INTEN_SOFTOKEN_MASK) 329 330 #define USB_INTEN_TOKDNEEN_MASK (0x8U) 331 #define USB_INTEN_TOKDNEEN_SHIFT (3U) 332 /*! TOKDNEEN - TOKDNE Interrupt Enable 333 * 0b0..Disable 334 * 0b1..Enable 335 */ 336 #define USB_INTEN_TOKDNEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_TOKDNEEN_SHIFT)) & USB_INTEN_TOKDNEEN_MASK) 337 338 #define USB_INTEN_SLEEPEN_MASK (0x10U) 339 #define USB_INTEN_SLEEPEN_SHIFT (4U) 340 /*! SLEEPEN - SLEEP Interrupt Enable 341 * 0b0..Disable 342 * 0b1..Enable 343 */ 344 #define USB_INTEN_SLEEPEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SLEEPEN_SHIFT)) & USB_INTEN_SLEEPEN_MASK) 345 346 #define USB_INTEN_RESUMEEN_MASK (0x20U) 347 #define USB_INTEN_RESUMEEN_SHIFT (5U) 348 /*! RESUMEEN - RESUME Interrupt Enable 349 * 0b0..Disable 350 * 0b1..Enable 351 */ 352 #define USB_INTEN_RESUMEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_RESUMEEN_SHIFT)) & USB_INTEN_RESUMEEN_MASK) 353 354 #define USB_INTEN_ATTACHEN_MASK (0x40U) 355 #define USB_INTEN_ATTACHEN_SHIFT (6U) 356 /*! ATTACHEN - ATTACH Interrupt Enable 357 * 0b0..Disable 358 * 0b1..Enable 359 */ 360 #define USB_INTEN_ATTACHEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ATTACHEN_SHIFT)) & USB_INTEN_ATTACHEN_MASK) 361 362 #define USB_INTEN_STALLEN_MASK (0x80U) 363 #define USB_INTEN_STALLEN_SHIFT (7U) 364 /*! STALLEN - STALL Interrupt Enable 365 * 0b0..Disable 366 * 0b1..Enable 367 */ 368 #define USB_INTEN_STALLEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_STALLEN_SHIFT)) & USB_INTEN_STALLEN_MASK) 369 /*! @} */ 370 371 /*! @name ERRSTAT - Error Interrupt Status */ 372 /*! @{ */ 373 374 #define USB_ERRSTAT_PIDERR_MASK (0x1U) 375 #define USB_ERRSTAT_PIDERR_SHIFT (0U) 376 /*! PIDERR - PID Error Flag 377 * 0b0..Did not fail 378 * 0b1..Failed 379 * 0b0..No effect 380 * 0b1..Clear the flag 381 */ 382 #define USB_ERRSTAT_PIDERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_PIDERR_SHIFT)) & USB_ERRSTAT_PIDERR_MASK) 383 384 #define USB_ERRSTAT_CRC5EOF_MASK (0x2U) 385 #define USB_ERRSTAT_CRC5EOF_SHIFT (1U) 386 /*! CRC5EOF - CRC5 Error or End of Frame Error Flag 387 * 0b0..Interrupt did not occur 388 * 0b1..Interrupt occurred 389 * 0b0..No effect 390 * 0b1..Clear the flag 391 */ 392 #define USB_ERRSTAT_CRC5EOF(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC5EOF_SHIFT)) & USB_ERRSTAT_CRC5EOF_MASK) 393 394 #define USB_ERRSTAT_CRC16_MASK (0x4U) 395 #define USB_ERRSTAT_CRC16_SHIFT (2U) 396 /*! CRC16 - CRC16 Error Flag 397 * 0b0..Not rejected 398 * 0b1..Rejected 399 * 0b0..No effect 400 * 0b1..Clear the flag 401 */ 402 #define USB_ERRSTAT_CRC16(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC16_SHIFT)) & USB_ERRSTAT_CRC16_MASK) 403 404 #define USB_ERRSTAT_DFN8_MASK (0x8U) 405 #define USB_ERRSTAT_DFN8_SHIFT (3U) 406 /*! DFN8 - Data Field Not 8 Bits Flag 407 * 0b0..Integer number of bytes 408 * 0b1..Not an integer number of bytes 409 * 0b0..No effect 410 * 0b1..Clear the flag 411 */ 412 #define USB_ERRSTAT_DFN8(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DFN8_SHIFT)) & USB_ERRSTAT_DFN8_MASK) 413 414 #define USB_ERRSTAT_BTOERR_MASK (0x10U) 415 #define USB_ERRSTAT_BTOERR_SHIFT (4U) 416 /*! BTOERR - Bus Turnaround Timeout Error Flag 417 * 0b0..Not timed out 418 * 0b1..Timed out 419 * 0b0..No effect 420 * 0b1..Clear the flag 421 */ 422 #define USB_ERRSTAT_BTOERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTOERR_SHIFT)) & USB_ERRSTAT_BTOERR_MASK) 423 424 #define USB_ERRSTAT_DMAERR_MASK (0x20U) 425 #define USB_ERRSTAT_DMAERR_SHIFT (5U) 426 /*! DMAERR - DMA Access Error Flag 427 * 0b0..Interrupt did not occur 428 * 0b1..Interrupt occurred 429 * 0b0..No effect 430 * 0b1..Clear the flag 431 */ 432 #define USB_ERRSTAT_DMAERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DMAERR_SHIFT)) & USB_ERRSTAT_DMAERR_MASK) 433 434 #define USB_ERRSTAT_OWNERR_MASK (0x40U) 435 #define USB_ERRSTAT_OWNERR_SHIFT (6U) 436 /*! OWNERR - BD Unavailable Error Flag 437 * 0b0..Interrupt did not occur 438 * 0b1..Interrupt occurred 439 * 0b0..No effect 440 * 0b1..Clear the flag 441 */ 442 #define USB_ERRSTAT_OWNERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_OWNERR_SHIFT)) & USB_ERRSTAT_OWNERR_MASK) 443 444 #define USB_ERRSTAT_BTSERR_MASK (0x80U) 445 #define USB_ERRSTAT_BTSERR_SHIFT (7U) 446 /*! BTSERR - Bit Stuff Error Flag 447 * 0b0..Packet not rejected due to the error 448 * 0b1..Packet rejected due to the error 449 * 0b0..No effect 450 * 0b1..Clear the flag 451 */ 452 #define USB_ERRSTAT_BTSERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTSERR_SHIFT)) & USB_ERRSTAT_BTSERR_MASK) 453 /*! @} */ 454 455 /*! @name ERREN - Error Interrupt Enable */ 456 /*! @{ */ 457 458 #define USB_ERREN_PIDERREN_MASK (0x1U) 459 #define USB_ERREN_PIDERREN_SHIFT (0U) 460 /*! PIDERREN - PIDERR Interrupt Enable 461 * 0b0..Disable 462 * 0b1..Enable 463 */ 464 #define USB_ERREN_PIDERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_PIDERREN_SHIFT)) & USB_ERREN_PIDERREN_MASK) 465 466 #define USB_ERREN_CRC5EOFEN_MASK (0x2U) 467 #define USB_ERREN_CRC5EOFEN_SHIFT (1U) 468 /*! CRC5EOFEN - CRC5/EOF Interrupt Enable 469 * 0b0..Disable 470 * 0b1..Enable 471 */ 472 #define USB_ERREN_CRC5EOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC5EOFEN_SHIFT)) & USB_ERREN_CRC5EOFEN_MASK) 473 474 #define USB_ERREN_CRC16EN_MASK (0x4U) 475 #define USB_ERREN_CRC16EN_SHIFT (2U) 476 /*! CRC16EN - CRC16 Interrupt Enable 477 * 0b0..Disable 478 * 0b1..Enable 479 */ 480 #define USB_ERREN_CRC16EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC16EN_SHIFT)) & USB_ERREN_CRC16EN_MASK) 481 482 #define USB_ERREN_DFN8EN_MASK (0x8U) 483 #define USB_ERREN_DFN8EN_SHIFT (3U) 484 /*! DFN8EN - DFN8 (Data Field Not Integer Number of Bytes) Interrupt Enable 485 * 0b0..Disable 486 * 0b1..Enable 487 */ 488 #define USB_ERREN_DFN8EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DFN8EN_SHIFT)) & USB_ERREN_DFN8EN_MASK) 489 490 #define USB_ERREN_BTOERREN_MASK (0x10U) 491 #define USB_ERREN_BTOERREN_SHIFT (4U) 492 /*! BTOERREN - BTOERR (Bus Timeout Error) Interrupt Enable 493 * 0b0..Disable 494 * 0b1..Enable 495 */ 496 #define USB_ERREN_BTOERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTOERREN_SHIFT)) & USB_ERREN_BTOERREN_MASK) 497 498 #define USB_ERREN_DMAERREN_MASK (0x20U) 499 #define USB_ERREN_DMAERREN_SHIFT (5U) 500 /*! DMAERREN - DMAERR Interrupt Enable 501 * 0b0..Disable 502 * 0b1..Enable 503 */ 504 #define USB_ERREN_DMAERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DMAERREN_SHIFT)) & USB_ERREN_DMAERREN_MASK) 505 506 #define USB_ERREN_OWNERREN_MASK (0x40U) 507 #define USB_ERREN_OWNERREN_SHIFT (6U) 508 /*! OWNERREN - OWNERR Interrupt Enable 509 * 0b0..Disable 510 * 0b1..Enable 511 */ 512 #define USB_ERREN_OWNERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_OWNERREN_SHIFT)) & USB_ERREN_OWNERREN_MASK) 513 514 #define USB_ERREN_BTSERREN_MASK (0x80U) 515 #define USB_ERREN_BTSERREN_SHIFT (7U) 516 /*! BTSERREN - BTSERR (Bit Stuff Error) Interrupt Enable 517 * 0b0..Disable 518 * 0b1..Enable 519 */ 520 #define USB_ERREN_BTSERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTSERREN_SHIFT)) & USB_ERREN_BTSERREN_MASK) 521 /*! @} */ 522 523 /*! @name STAT - Status */ 524 /*! @{ */ 525 526 #define USB_STAT_ODD_MASK (0x4U) 527 #define USB_STAT_ODD_SHIFT (2U) 528 /*! ODD - Odd Bank 529 * 0b0..Not in the odd bank 530 * 0b1..In the odd bank 531 */ 532 #define USB_STAT_ODD(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ODD_SHIFT)) & USB_STAT_ODD_MASK) 533 534 #define USB_STAT_TX_MASK (0x8U) 535 #define USB_STAT_TX_SHIFT (3U) 536 /*! TX - Transmit Indicator 537 * 0b0..Receive 538 * 0b1..Transmit 539 */ 540 #define USB_STAT_TX(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_TX_SHIFT)) & USB_STAT_TX_MASK) 541 542 #define USB_STAT_ENDP_MASK (0xF0U) 543 #define USB_STAT_ENDP_SHIFT (4U) 544 /*! ENDP - Endpoint address */ 545 #define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ENDP_SHIFT)) & USB_STAT_ENDP_MASK) 546 /*! @} */ 547 548 /*! @name CTL - Control */ 549 /*! @{ */ 550 551 #define USB_CTL_USBENSOFEN_MASK (0x1U) 552 #define USB_CTL_USBENSOFEN_SHIFT (0U) 553 /*! USBENSOFEN - USB Enable 554 * 0b0..Disable 555 * 0b1..Enable 556 */ 557 #define USB_CTL_USBENSOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_USBENSOFEN_SHIFT)) & USB_CTL_USBENSOFEN_MASK) 558 559 #define USB_CTL_ODDRST_MASK (0x2U) 560 #define USB_CTL_ODDRST_SHIFT (1U) 561 /*! ODDRST - Odd Reset */ 562 #define USB_CTL_ODDRST(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_ODDRST_SHIFT)) & USB_CTL_ODDRST_MASK) 563 564 #define USB_CTL_RESUME_MASK (0x4U) 565 #define USB_CTL_RESUME_SHIFT (2U) 566 /*! RESUME - Resume */ 567 #define USB_CTL_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESUME_SHIFT)) & USB_CTL_RESUME_MASK) 568 569 #define USB_CTL_HOSTMODEEN_MASK (0x8U) 570 #define USB_CTL_HOSTMODEEN_SHIFT (3U) 571 /*! HOSTMODEEN - Host Mode Enable 572 * 0b0..USBFS operates in Device mode. 573 * 0b1..USBFS operates in Host mode. In Host mode, USBFS performs USB transactions under the programmed control of the host processor. 574 */ 575 #define USB_CTL_HOSTMODEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_HOSTMODEEN_SHIFT)) & USB_CTL_HOSTMODEEN_MASK) 576 577 #define USB_CTL_RESET_MASK (0x10U) 578 #define USB_CTL_RESET_SHIFT (4U) 579 /*! RESET - Reset Signaling Enable 580 * 0b0..Disable 581 * 0b1..Enable 582 */ 583 #define USB_CTL_RESET(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESET_SHIFT)) & USB_CTL_RESET_MASK) 584 585 #define USB_CTL_TXSUSPENDTOKENBUSY_MASK (0x20U) 586 #define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT (5U) 587 /*! TXSUSPENDTOKENBUSY - TXD Suspend And Token Busy */ 588 #define USB_CTL_TXSUSPENDTOKENBUSY(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_TXSUSPENDTOKENBUSY_SHIFT)) & USB_CTL_TXSUSPENDTOKENBUSY_MASK) 589 590 #define USB_CTL_SE0_MASK (0x40U) 591 #define USB_CTL_SE0_SHIFT (6U) 592 /*! SE0 - Live USB Single-Ended Zero signal */ 593 #define USB_CTL_SE0(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_SE0_SHIFT)) & USB_CTL_SE0_MASK) 594 595 #define USB_CTL_JSTATE_MASK (0x80U) 596 #define USB_CTL_JSTATE_SHIFT (7U) 597 /*! JSTATE - Live USB Differential Receiver JSTATE Signal */ 598 #define USB_CTL_JSTATE(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_JSTATE_SHIFT)) & USB_CTL_JSTATE_MASK) 599 /*! @} */ 600 601 /*! @name ADDR - Address */ 602 /*! @{ */ 603 604 #define USB_ADDR_ADDR_MASK (0x7FU) 605 #define USB_ADDR_ADDR_SHIFT (0U) 606 /*! ADDR - USB Address */ 607 #define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_ADDR_SHIFT)) & USB_ADDR_ADDR_MASK) 608 609 #define USB_ADDR_LSEN_MASK (0x80U) 610 #define USB_ADDR_LSEN_SHIFT (7U) 611 /*! LSEN - Low Speed Enable */ 612 #define USB_ADDR_LSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_LSEN_SHIFT)) & USB_ADDR_LSEN_MASK) 613 /*! @} */ 614 615 /*! @name BDTPAGE1 - BDT Page 1 */ 616 /*! @{ */ 617 618 #define USB_BDTPAGE1_BDTBA_MASK (0xFEU) 619 #define USB_BDTPAGE1_BDTBA_SHIFT (1U) 620 /*! BDTBA - BDT Base Address */ 621 #define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE1_BDTBA_SHIFT)) & USB_BDTPAGE1_BDTBA_MASK) 622 /*! @} */ 623 624 /*! @name FRMNUML - Frame Number Register Low */ 625 /*! @{ */ 626 627 #define USB_FRMNUML_FRM_MASK (0xFFU) 628 #define USB_FRMNUML_FRM_SHIFT (0U) 629 /*! FRM - Frame Number, Bits 0-7 */ 630 #define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUML_FRM_SHIFT)) & USB_FRMNUML_FRM_MASK) 631 /*! @} */ 632 633 /*! @name FRMNUMH - Frame Number Register High */ 634 /*! @{ */ 635 636 #define USB_FRMNUMH_FRM_MASK (0x7U) 637 #define USB_FRMNUMH_FRM_SHIFT (0U) 638 /*! FRM - Frame Number, Bits 8-10 */ 639 #define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUMH_FRM_SHIFT)) & USB_FRMNUMH_FRM_MASK) 640 /*! @} */ 641 642 /*! @name TOKEN - Token */ 643 /*! @{ */ 644 645 #define USB_TOKEN_TOKENENDPT_MASK (0xFU) 646 #define USB_TOKEN_TOKENENDPT_SHIFT (0U) 647 /*! TOKENENDPT - Token Endpoint Address */ 648 #define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENENDPT_SHIFT)) & USB_TOKEN_TOKENENDPT_MASK) 649 650 #define USB_TOKEN_TOKENPID_MASK (0xF0U) 651 #define USB_TOKEN_TOKENPID_SHIFT (4U) 652 /*! TOKENPID - Token Type 653 * 0b0001..OUT token. USBFS performs an OUT (TX) transaction. 654 * 0b1001..IN token. USBFS performs an IN (RX) transaction. 655 * 0b1101..SETUP token. USBFS performs a SETUP (TX) transaction 656 */ 657 #define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENPID_SHIFT)) & USB_TOKEN_TOKENPID_MASK) 658 /*! @} */ 659 660 /*! @name SOFTHLD - SOF Threshold */ 661 /*! @{ */ 662 663 #define USB_SOFTHLD_CNT_MASK (0xFFU) 664 #define USB_SOFTHLD_CNT_SHIFT (0U) 665 /*! CNT - SOF Count Threshold */ 666 #define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x)) << USB_SOFTHLD_CNT_SHIFT)) & USB_SOFTHLD_CNT_MASK) 667 /*! @} */ 668 669 /*! @name BDTPAGE2 - BDT Page 2 */ 670 /*! @{ */ 671 672 #define USB_BDTPAGE2_BDTBA_MASK (0xFFU) 673 #define USB_BDTPAGE2_BDTBA_SHIFT (0U) 674 /*! BDTBA - BDT Base Address */ 675 #define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE2_BDTBA_SHIFT)) & USB_BDTPAGE2_BDTBA_MASK) 676 /*! @} */ 677 678 /*! @name BDTPAGE3 - BDT Page 3 */ 679 /*! @{ */ 680 681 #define USB_BDTPAGE3_BDTBA_MASK (0xFFU) 682 #define USB_BDTPAGE3_BDTBA_SHIFT (0U) 683 /*! BDTBA - BDT Base Address */ 684 #define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE3_BDTBA_SHIFT)) & USB_BDTPAGE3_BDTBA_MASK) 685 /*! @} */ 686 687 /*! @name ENDPT - Endpoint Control */ 688 /*! @{ */ 689 690 #define USB_ENDPT_EPHSHK_MASK (0x1U) 691 #define USB_ENDPT_EPHSHK_SHIFT (0U) 692 /*! EPHSHK - Endpoint Handshaking Enable */ 693 #define USB_ENDPT_EPHSHK(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPHSHK_SHIFT)) & USB_ENDPT_EPHSHK_MASK) 694 695 #define USB_ENDPT_EPSTALL_MASK (0x2U) 696 #define USB_ENDPT_EPSTALL_SHIFT (1U) 697 /*! EPSTALL - Endpoint Stalled */ 698 #define USB_ENDPT_EPSTALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPSTALL_SHIFT)) & USB_ENDPT_EPSTALL_MASK) 699 700 #define USB_ENDPT_EPTXEN_MASK (0x4U) 701 #define USB_ENDPT_EPTXEN_SHIFT (2U) 702 /*! EPTXEN - Endpoint for TX transfers enable */ 703 #define USB_ENDPT_EPTXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPTXEN_SHIFT)) & USB_ENDPT_EPTXEN_MASK) 704 705 #define USB_ENDPT_EPRXEN_MASK (0x8U) 706 #define USB_ENDPT_EPRXEN_SHIFT (3U) 707 /*! EPRXEN - Endpoint for RX transfers enable */ 708 #define USB_ENDPT_EPRXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPRXEN_SHIFT)) & USB_ENDPT_EPRXEN_MASK) 709 710 #define USB_ENDPT_EPCTLDIS_MASK (0x10U) 711 #define USB_ENDPT_EPCTLDIS_SHIFT (4U) 712 /*! EPCTLDIS - Control Transfer Disable 713 * 0b0..Enable 714 * 0b1..Disable 715 */ 716 #define USB_ENDPT_EPCTLDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPCTLDIS_SHIFT)) & USB_ENDPT_EPCTLDIS_MASK) 717 718 #define USB_ENDPT_RETRYDIS_MASK (0x40U) 719 #define USB_ENDPT_RETRYDIS_SHIFT (6U) 720 /*! RETRYDIS - Retry Disable 721 * 0b0..Retried NAK'ed transactions in hardware. 722 * 0b1..Do not retry NAK'ed transactions. When a transaction is NAK'ed, the BDT PID field is updated with the NAK 723 * PID, and the TOKEN_DNE interrupt becomes 1. 724 */ 725 #define USB_ENDPT_RETRYDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_RETRYDIS_SHIFT)) & USB_ENDPT_RETRYDIS_MASK) 726 727 #define USB_ENDPT_HOSTWOHUB_MASK (0x80U) 728 #define USB_ENDPT_HOSTWOHUB_SHIFT (7U) 729 /*! HOSTWOHUB - Host Without A Hub 730 * 0b0..Connected using a hub (USBFS generates PRE_PID as required) 731 * 0b1..Connected directly to host without a hub, or was used to attach 732 */ 733 #define USB_ENDPT_HOSTWOHUB(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_HOSTWOHUB_SHIFT)) & USB_ENDPT_HOSTWOHUB_MASK) 734 /*! @} */ 735 736 /* The count of USB_ENDPT */ 737 #define USB_ENDPT_COUNT (16U) 738 739 /*! @name USBCTRL - USB Control */ 740 /*! @{ */ 741 742 #define USB_USBCTRL_DPDM_LANE_REVERSE_MASK (0x4U) 743 #define USB_USBCTRL_DPDM_LANE_REVERSE_SHIFT (2U) 744 /*! DPDM_LANE_REVERSE - DP and DM Lane Reversal Control 745 * 0b0..Standard USB DP and DM package pin assignment 746 * 0b1..Reverse roles of USB DP and DM package pins 747 */ 748 #define USB_USBCTRL_DPDM_LANE_REVERSE(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_DPDM_LANE_REVERSE_SHIFT)) & USB_USBCTRL_DPDM_LANE_REVERSE_MASK) 749 750 #define USB_USBCTRL_HOST_LS_EOP_MASK (0x8U) 751 #define USB_USBCTRL_HOST_LS_EOP_SHIFT (3U) 752 /*! HOST_LS_EOP - Host-Mode-Only Low-Speed Device EOP Signaling 753 * 0b0..Full-speed device or a low-speed device through a hub 754 * 0b1..Directly-connected low-speed device 755 */ 756 #define USB_USBCTRL_HOST_LS_EOP(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_HOST_LS_EOP_SHIFT)) & USB_USBCTRL_HOST_LS_EOP_MASK) 757 758 #define USB_USBCTRL_UARTSEL_MASK (0x10U) 759 #define USB_USBCTRL_UARTSEL_SHIFT (4U) 760 /*! UARTSEL - UART Select 761 * 0b0..USB DP and DM external package pins are used for USB signaling. 762 * 0b1..USB DP and DM external package pins are used for UART signaling. 763 */ 764 #define USB_USBCTRL_UARTSEL(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_UARTSEL_SHIFT)) & USB_USBCTRL_UARTSEL_MASK) 765 766 #define USB_USBCTRL_UARTCHLS_MASK (0x20U) 767 #define USB_USBCTRL_UARTCHLS_SHIFT (5U) 768 /*! UARTCHLS - UART Signal Channel Select 769 * 0b0..USB DP and DM signals are used as UART TX/RX. 770 * 0b1..USB DP and DM signals are used as UART RX/TX. 771 */ 772 #define USB_USBCTRL_UARTCHLS(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_UARTCHLS_SHIFT)) & USB_USBCTRL_UARTCHLS_MASK) 773 774 #define USB_USBCTRL_PDE_MASK (0x40U) 775 #define USB_USBCTRL_PDE_SHIFT (6U) 776 /*! PDE - Pulldown Enable 777 * 0b0..Disable on D+ and D- 778 * 0b1..Enable on D+ and D- 779 */ 780 #define USB_USBCTRL_PDE(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_PDE_SHIFT)) & USB_USBCTRL_PDE_MASK) 781 782 #define USB_USBCTRL_SUSP_MASK (0x80U) 783 #define USB_USBCTRL_SUSP_SHIFT (7U) 784 /*! SUSP - Suspend 785 * 0b0..Not in Suspend state 786 * 0b1..In Suspend state 787 */ 788 #define USB_USBCTRL_SUSP(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_SUSP_SHIFT)) & USB_USBCTRL_SUSP_MASK) 789 /*! @} */ 790 791 /*! @name OBSERVE - USB OTG Observe */ 792 /*! @{ */ 793 794 #define USB_OBSERVE_DMPD_MASK (0x10U) 795 #define USB_OBSERVE_DMPD_SHIFT (4U) 796 /*! DMPD - D- Pulldown 797 * 0b0..Disabled 798 * 0b1..Enabled 799 */ 800 #define USB_OBSERVE_DMPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DMPD_SHIFT)) & USB_OBSERVE_DMPD_MASK) 801 802 #define USB_OBSERVE_DPPD_MASK (0x40U) 803 #define USB_OBSERVE_DPPD_SHIFT (6U) 804 /*! DPPD - D+ Pulldown 805 * 0b0..Disabled 806 * 0b1..Enabled 807 */ 808 #define USB_OBSERVE_DPPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPD_SHIFT)) & USB_OBSERVE_DPPD_MASK) 809 810 #define USB_OBSERVE_DPPU_MASK (0x80U) 811 #define USB_OBSERVE_DPPU_SHIFT (7U) 812 /*! DPPU - D+ Pullup 813 * 0b0..Disabled 814 * 0b1..Enabled 815 */ 816 #define USB_OBSERVE_DPPU(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPU_SHIFT)) & USB_OBSERVE_DPPU_MASK) 817 /*! @} */ 818 819 /*! @name CONTROL - USB OTG Control */ 820 /*! @{ */ 821 822 #define USB_CONTROL_VBUS_SOURCE_SEL_MASK (0x1U) 823 #define USB_CONTROL_VBUS_SOURCE_SEL_SHIFT (0U) 824 /*! VBUS_SOURCE_SEL - VBUS Monitoring Source Select 825 * 0b0..Reserved 826 * 0b1..Resistive divider attached to a GPIO pin 827 */ 828 #define USB_CONTROL_VBUS_SOURCE_SEL(x) (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_VBUS_SOURCE_SEL_SHIFT)) & USB_CONTROL_VBUS_SOURCE_SEL_MASK) 829 830 #define USB_CONTROL_SESS_VLD_MASK (0x2U) 831 #define USB_CONTROL_SESS_VLD_SHIFT (1U) 832 /*! SESS_VLD - VBUS Session Valid status 833 * 0b1..Above 834 * 0b0..Below 835 */ 836 #define USB_CONTROL_SESS_VLD(x) (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_SESS_VLD_SHIFT)) & USB_CONTROL_SESS_VLD_MASK) 837 838 #define USB_CONTROL_DPPULLUPNONOTG_MASK (0x10U) 839 #define USB_CONTROL_DPPULLUPNONOTG_SHIFT (4U) 840 /*! DPPULLUPNONOTG - DP Pullup in Non-OTG Device Mode 841 * 0b0..Disable 842 * 0b1..Enabled 843 */ 844 #define USB_CONTROL_DPPULLUPNONOTG(x) (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_DPPULLUPNONOTG_SHIFT)) & USB_CONTROL_DPPULLUPNONOTG_MASK) 845 /*! @} */ 846 847 /*! @name USBTRC0 - USB Transceiver Control 0 */ 848 /*! @{ */ 849 850 #define USB_USBTRC0_USB_RESUME_INT_MASK (0x1U) 851 #define USB_USBTRC0_USB_RESUME_INT_SHIFT (0U) 852 /*! USB_RESUME_INT - USB Asynchronous Interrupt 853 * 0b0..Not generated 854 * 0b1..Generated because of the USB asynchronous interrupt 855 */ 856 #define USB_USBTRC0_USB_RESUME_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_RESUME_INT_SHIFT)) & USB_USBTRC0_USB_RESUME_INT_MASK) 857 858 #define USB_USBTRC0_SYNC_DET_MASK (0x2U) 859 #define USB_USBTRC0_SYNC_DET_SHIFT (1U) 860 /*! SYNC_DET - Synchronous USB Interrupt Detect 861 * 0b0..Not detected 862 * 0b1..Detected 863 */ 864 #define USB_USBTRC0_SYNC_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_SYNC_DET_SHIFT)) & USB_USBTRC0_SYNC_DET_MASK) 865 866 #define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK (0x4U) 867 #define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT (2U) 868 /*! USB_CLK_RECOVERY_INT - Combined USB Clock Recovery interrupt status */ 869 #define USB_USBTRC0_USB_CLK_RECOVERY_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT)) & USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK) 870 871 #define USB_USBTRC0_VREDG_DET_MASK (0x8U) 872 #define USB_USBTRC0_VREDG_DET_SHIFT (3U) 873 /*! VREDG_DET - VREGIN Rising Edge Interrupt Detect 874 * 0b0..Not detected 875 * 0b1..Detected 876 */ 877 #define USB_USBTRC0_VREDG_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_VREDG_DET_SHIFT)) & USB_USBTRC0_VREDG_DET_MASK) 878 879 #define USB_USBTRC0_VFEDG_DET_MASK (0x10U) 880 #define USB_USBTRC0_VFEDG_DET_SHIFT (4U) 881 /*! VFEDG_DET - VREGIN Falling Edge Interrupt Detect 882 * 0b0..Not detected 883 * 0b1..Detected 884 */ 885 #define USB_USBTRC0_VFEDG_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_VFEDG_DET_SHIFT)) & USB_USBTRC0_VFEDG_DET_MASK) 886 887 #define USB_USBTRC0_USBRESMEN_MASK (0x20U) 888 #define USB_USBTRC0_USBRESMEN_SHIFT (5U) 889 /*! USBRESMEN - Asynchronous Resume Interrupt Enable 890 * 0b0..Disable 891 * 0b1..Enable 892 */ 893 #define USB_USBTRC0_USBRESMEN(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESMEN_SHIFT)) & USB_USBTRC0_USBRESMEN_MASK) 894 895 #define USB_USBTRC0_VREGIN_STS_MASK (0x40U) 896 #define USB_USBTRC0_VREGIN_STS_SHIFT (6U) 897 /*! VREGIN_STS - VREGIN Status */ 898 #define USB_USBTRC0_VREGIN_STS(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_VREGIN_STS_SHIFT)) & USB_USBTRC0_VREGIN_STS_MASK) 899 900 #define USB_USBTRC0_USBRESET_MASK (0x80U) 901 #define USB_USBTRC0_USBRESET_SHIFT (7U) 902 /*! USBRESET - USB Reset 903 * 0b0..Normal USBFS operation 904 * 0b1..Returns USBFS to its reset state 905 */ 906 #define USB_USBTRC0_USBRESET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESET_SHIFT)) & USB_USBTRC0_USBRESET_MASK) 907 /*! @} */ 908 909 /*! @name USBFRMADJUST - Frame Adjust */ 910 /*! @{ */ 911 912 #define USB_USBFRMADJUST_ADJ_MASK (0xFFU) 913 #define USB_USBFRMADJUST_ADJ_SHIFT (0U) 914 /*! ADJ - Frame Adjustment */ 915 #define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x)) << USB_USBFRMADJUST_ADJ_SHIFT)) & USB_USBFRMADJUST_ADJ_MASK) 916 /*! @} */ 917 918 /*! @name KEEP_ALIVE_CTRL - Keep Alive Mode Control */ 919 /*! @{ */ 920 921 #define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN_MASK (0x1U) 922 #define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN_SHIFT (0U) 923 /*! KEEP_ALIVE_EN - Keep Alive Mode Enable 924 * 0b0..Everything remains same as before. 925 * 0b1..USB shall enter USB_KEEP_ALIVE mode after asserting ipg_stop. 926 */ 927 #define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN_MASK) 928 929 #define USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN_MASK (0x2U) 930 #define USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN_SHIFT (1U) 931 /*! OWN_OVERRD_EN - OWN Bit Override Enable */ 932 #define USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN_MASK) 933 934 #define USB_KEEP_ALIVE_CTRL_STOP_ACK_DLY_EN_MASK (0x4U) 935 #define USB_KEEP_ALIVE_CTRL_STOP_ACK_DLY_EN_SHIFT (2U) 936 /*! STOP_ACK_DLY_EN - Stop Acknowledge Delay Enable 937 * 0b0..Enter KEEP_ALIVE mode immediately when there is no USB AHB transfer. 938 * 0b1..Enter KEEP_ALIVE mode until the USB core is idle and there is no USB AHB transfer. 939 */ 940 #define USB_KEEP_ALIVE_CTRL_STOP_ACK_DLY_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_STOP_ACK_DLY_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_STOP_ACK_DLY_EN_MASK) 941 942 #define USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN_MASK (0x8U) 943 #define USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN_SHIFT (3U) 944 /*! WAKE_REQ_EN - Wakeup Request Enable 945 * 0b0..Disable 946 * 0b1..Enable 947 */ 948 #define USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN_MASK) 949 950 #define USB_KEEP_ALIVE_CTRL_WAKE_INT_EN_MASK (0x10U) 951 #define USB_KEEP_ALIVE_CTRL_WAKE_INT_EN_SHIFT (4U) 952 /*! WAKE_INT_EN - Wakeup Interrupt Enable */ 953 #define USB_KEEP_ALIVE_CTRL_WAKE_INT_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_WAKE_INT_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_WAKE_INT_EN_MASK) 954 955 #define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_STS_MASK (0x40U) 956 #define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_STS_SHIFT (6U) 957 /*! KEEP_ALIVE_STS - Keep Alive Status 958 * 0b0..Not in Keep Alive mode 959 * 0b1..In Keep Alive mode 960 */ 961 #define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_STS(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_STS_SHIFT)) & USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_STS_MASK) 962 963 #define USB_KEEP_ALIVE_CTRL_WAKE_INT_STS_MASK (0x80U) 964 #define USB_KEEP_ALIVE_CTRL_WAKE_INT_STS_SHIFT (7U) 965 /*! WAKE_INT_STS - Wakeup Interrupt Status Flag 966 * 0b0..Interrupt did not occur 967 * 0b1..Interrupt occurred 968 * 0b0..No effect 969 * 0b1..Clear the flag 970 */ 971 #define USB_KEEP_ALIVE_CTRL_WAKE_INT_STS(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_WAKE_INT_STS_SHIFT)) & USB_KEEP_ALIVE_CTRL_WAKE_INT_STS_MASK) 972 /*! @} */ 973 974 /*! @name KEEP_ALIVE_WKCTRL - Keep Alive Mode Wakeup Control */ 975 /*! @{ */ 976 977 #define USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_MASK (0xFU) 978 #define USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_SHIFT (0U) 979 /*! WAKE_ON_THIS - Token PID for the wakeup request 980 * 0b0001..Wake up after receiving OUT or SETUP token packet. 981 * 0b1101..Wake up after receiving SETUP token packet. All other values are reserved. 982 */ 983 #define USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_SHIFT)) & USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_MASK) 984 985 #define USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT_MASK (0xF0U) 986 #define USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT_SHIFT (4U) 987 /*! WAKE_ENDPT - Endpoint address for the wakeup request */ 988 #define USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT_SHIFT)) & USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT_MASK) 989 /*! @} */ 990 991 /*! @name MISCCTRL - Miscellaneous Control */ 992 /*! @{ */ 993 994 #define USB_MISCCTRL_SOFDYNTHLD_MASK (0x1U) 995 #define USB_MISCCTRL_SOFDYNTHLD_SHIFT (0U) 996 /*! SOFDYNTHLD - Dynamic SOF Threshold Compare mode 997 * 0b0..When the byte-times SOF threshold is reached 998 * 0b1..When 8 byte-times SOF threshold is reached or overstepped 999 */ 1000 #define USB_MISCCTRL_SOFDYNTHLD(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_SOFDYNTHLD_SHIFT)) & USB_MISCCTRL_SOFDYNTHLD_MASK) 1001 1002 #define USB_MISCCTRL_SOFBUSSET_MASK (0x2U) 1003 #define USB_MISCCTRL_SOFBUSSET_SHIFT (1U) 1004 /*! SOFBUSSET - SOF_TOK Interrupt Generation Mode Select 1005 * 0b0..According to the SOF threshold value 1006 * 0b1..When the SOF counter reaches 0 1007 */ 1008 #define USB_MISCCTRL_SOFBUSSET(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_SOFBUSSET_SHIFT)) & USB_MISCCTRL_SOFBUSSET_MASK) 1009 1010 #define USB_MISCCTRL_OWNERRISODIS_MASK (0x4U) 1011 #define USB_MISCCTRL_OWNERRISODIS_SHIFT (2U) 1012 /*! OWNERRISODIS - OWN Error Detect for ISO IN and ISO OUT Disable 1013 * 0b0..Enable 1014 * 0b1..Disable 1015 */ 1016 #define USB_MISCCTRL_OWNERRISODIS(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_OWNERRISODIS_SHIFT)) & USB_MISCCTRL_OWNERRISODIS_MASK) 1017 1018 #define USB_MISCCTRL_VREDG_EN_MASK (0x8U) 1019 #define USB_MISCCTRL_VREDG_EN_SHIFT (3U) 1020 /*! VREDG_EN - VREGIN Rising Edge Interrupt Enable 1021 * 0b0..Disable 1022 * 0b1..Enable 1023 */ 1024 #define USB_MISCCTRL_VREDG_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_VREDG_EN_SHIFT)) & USB_MISCCTRL_VREDG_EN_MASK) 1025 1026 #define USB_MISCCTRL_VFEDG_EN_MASK (0x10U) 1027 #define USB_MISCCTRL_VFEDG_EN_SHIFT (4U) 1028 /*! VFEDG_EN - VREGIN Falling Edge Interrupt Enable 1029 * 0b0..Disable 1030 * 0b1..Enable 1031 */ 1032 #define USB_MISCCTRL_VFEDG_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_VFEDG_EN_SHIFT)) & USB_MISCCTRL_VFEDG_EN_MASK) 1033 1034 #define USB_MISCCTRL_STL_ADJ_EN_MASK (0x80U) 1035 #define USB_MISCCTRL_STL_ADJ_EN_SHIFT (7U) 1036 /*! STL_ADJ_EN - USB Peripheral Mode Stall Adjust Enable 1037 * 0b0..If ENDPTn[END_STALL] = 1, both IN and OUT directions for the associated endpoint stalls. 1038 * 0b1..If ENDPTn[END_STALL] = 1, the STALL_xx_DIS registers control which directions for the associated endpoint stalls. 1039 */ 1040 #define USB_MISCCTRL_STL_ADJ_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_STL_ADJ_EN_SHIFT)) & USB_MISCCTRL_STL_ADJ_EN_MASK) 1041 /*! @} */ 1042 1043 /*! @name STALL_IL_DIS - Peripheral Mode Stall Disable for Endpoints 7 to 0 in IN Direction */ 1044 /*! @{ */ 1045 1046 #define USB_STALL_IL_DIS_STALL_I_DIS0_MASK (0x1U) 1047 #define USB_STALL_IL_DIS_STALL_I_DIS0_SHIFT (0U) 1048 /*! STALL_I_DIS0 - Disable Endpoint 0 IN Direction 1049 * 0b0..Enable 1050 * 0b1..Disable 1051 */ 1052 #define USB_STALL_IL_DIS_STALL_I_DIS0(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS0_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS0_MASK) 1053 1054 #define USB_STALL_IL_DIS_STALL_I_DIS1_MASK (0x2U) 1055 #define USB_STALL_IL_DIS_STALL_I_DIS1_SHIFT (1U) 1056 /*! STALL_I_DIS1 - Disable Endpoint 1 IN Direction 1057 * 0b0..Enable 1058 * 0b1..Disable 1059 */ 1060 #define USB_STALL_IL_DIS_STALL_I_DIS1(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS1_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS1_MASK) 1061 1062 #define USB_STALL_IL_DIS_STALL_I_DIS2_MASK (0x4U) 1063 #define USB_STALL_IL_DIS_STALL_I_DIS2_SHIFT (2U) 1064 /*! STALL_I_DIS2 - Disable Endpoint 2 IN Direction 1065 * 0b0..Enable 1066 * 0b1..Disable 1067 */ 1068 #define USB_STALL_IL_DIS_STALL_I_DIS2(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS2_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS2_MASK) 1069 1070 #define USB_STALL_IL_DIS_STALL_I_DIS3_MASK (0x8U) 1071 #define USB_STALL_IL_DIS_STALL_I_DIS3_SHIFT (3U) 1072 /*! STALL_I_DIS3 - Disable Endpoint 3 IN Direction 1073 * 0b0..Enable 1074 * 0b1..Disable 1075 */ 1076 #define USB_STALL_IL_DIS_STALL_I_DIS3(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS3_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS3_MASK) 1077 1078 #define USB_STALL_IL_DIS_STALL_I_DIS4_MASK (0x10U) 1079 #define USB_STALL_IL_DIS_STALL_I_DIS4_SHIFT (4U) 1080 /*! STALL_I_DIS4 - Disable Endpoint 4 IN Direction 1081 * 0b0..Enable 1082 * 0b1..Disable 1083 */ 1084 #define USB_STALL_IL_DIS_STALL_I_DIS4(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS4_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS4_MASK) 1085 1086 #define USB_STALL_IL_DIS_STALL_I_DIS5_MASK (0x20U) 1087 #define USB_STALL_IL_DIS_STALL_I_DIS5_SHIFT (5U) 1088 /*! STALL_I_DIS5 - Disable Endpoint 5 IN Direction 1089 * 0b0..Enable 1090 * 0b1..Disable 1091 */ 1092 #define USB_STALL_IL_DIS_STALL_I_DIS5(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS5_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS5_MASK) 1093 1094 #define USB_STALL_IL_DIS_STALL_I_DIS6_MASK (0x40U) 1095 #define USB_STALL_IL_DIS_STALL_I_DIS6_SHIFT (6U) 1096 /*! STALL_I_DIS6 - Disable Endpoint 6 IN Direction 1097 * 0b0..Enable 1098 * 0b1..Disable 1099 */ 1100 #define USB_STALL_IL_DIS_STALL_I_DIS6(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS6_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS6_MASK) 1101 1102 #define USB_STALL_IL_DIS_STALL_I_DIS7_MASK (0x80U) 1103 #define USB_STALL_IL_DIS_STALL_I_DIS7_SHIFT (7U) 1104 /*! STALL_I_DIS7 - Disable Endpoint 7 IN Direction 1105 * 0b0..Enable 1106 * 0b1..Disable 1107 */ 1108 #define USB_STALL_IL_DIS_STALL_I_DIS7(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS7_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS7_MASK) 1109 /*! @} */ 1110 1111 /*! @name STALL_IH_DIS - Peripheral Mode Stall Disable for Endpoints 15 to 8 in IN Direction */ 1112 /*! @{ */ 1113 1114 #define USB_STALL_IH_DIS_STALL_I_DIS8_MASK (0x1U) 1115 #define USB_STALL_IH_DIS_STALL_I_DIS8_SHIFT (0U) 1116 /*! STALL_I_DIS8 - Disable Endpoint 8 IN Direction 1117 * 0b0..Enable 1118 * 0b1..Disable 1119 */ 1120 #define USB_STALL_IH_DIS_STALL_I_DIS8(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS8_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS8_MASK) 1121 1122 #define USB_STALL_IH_DIS_STALL_I_DIS9_MASK (0x2U) 1123 #define USB_STALL_IH_DIS_STALL_I_DIS9_SHIFT (1U) 1124 /*! STALL_I_DIS9 - Disable Endpoint 9 IN Direction 1125 * 0b0..Enable 1126 * 0b1..Disable 1127 */ 1128 #define USB_STALL_IH_DIS_STALL_I_DIS9(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS9_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS9_MASK) 1129 1130 #define USB_STALL_IH_DIS_STALL_I_DIS10_MASK (0x4U) 1131 #define USB_STALL_IH_DIS_STALL_I_DIS10_SHIFT (2U) 1132 /*! STALL_I_DIS10 - Disable Endpoint 10 IN Direction 1133 * 0b0..Enable 1134 * 0b1..Disable 1135 */ 1136 #define USB_STALL_IH_DIS_STALL_I_DIS10(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS10_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS10_MASK) 1137 1138 #define USB_STALL_IH_DIS_STALL_I_DIS11_MASK (0x8U) 1139 #define USB_STALL_IH_DIS_STALL_I_DIS11_SHIFT (3U) 1140 /*! STALL_I_DIS11 - Disable Endpoint 11 IN Direction 1141 * 0b0..Enable 1142 * 0b1..Disable 1143 */ 1144 #define USB_STALL_IH_DIS_STALL_I_DIS11(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS11_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS11_MASK) 1145 1146 #define USB_STALL_IH_DIS_STALL_I_DIS12_MASK (0x10U) 1147 #define USB_STALL_IH_DIS_STALL_I_DIS12_SHIFT (4U) 1148 /*! STALL_I_DIS12 - Disable Endpoint 12 IN Direction 1149 * 0b0..Enable 1150 * 0b1..Disable 1151 */ 1152 #define USB_STALL_IH_DIS_STALL_I_DIS12(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS12_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS12_MASK) 1153 1154 #define USB_STALL_IH_DIS_STALL_I_DIS13_MASK (0x20U) 1155 #define USB_STALL_IH_DIS_STALL_I_DIS13_SHIFT (5U) 1156 /*! STALL_I_DIS13 - Disable Endpoint 13 IN Direction 1157 * 0b0..Enable 1158 * 0b1..Disable 1159 */ 1160 #define USB_STALL_IH_DIS_STALL_I_DIS13(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS13_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS13_MASK) 1161 1162 #define USB_STALL_IH_DIS_STALL_I_DIS14_MASK (0x40U) 1163 #define USB_STALL_IH_DIS_STALL_I_DIS14_SHIFT (6U) 1164 /*! STALL_I_DIS14 - Disable Endpoint 14 IN Direction 1165 * 0b0..Enable 1166 * 0b1..Disable 1167 */ 1168 #define USB_STALL_IH_DIS_STALL_I_DIS14(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS14_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS14_MASK) 1169 1170 #define USB_STALL_IH_DIS_STALL_I_DIS15_MASK (0x80U) 1171 #define USB_STALL_IH_DIS_STALL_I_DIS15_SHIFT (7U) 1172 /*! STALL_I_DIS15 - Disable Endpoint 15 IN Direction 1173 * 0b0..Enable 1174 * 0b1..Disable 1175 */ 1176 #define USB_STALL_IH_DIS_STALL_I_DIS15(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS15_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS15_MASK) 1177 /*! @} */ 1178 1179 /*! @name STALL_OL_DIS - Peripheral Mode Stall Disable for Endpoints 7 to 0 in OUT Direction */ 1180 /*! @{ */ 1181 1182 #define USB_STALL_OL_DIS_STALL_O_DIS0_MASK (0x1U) 1183 #define USB_STALL_OL_DIS_STALL_O_DIS0_SHIFT (0U) 1184 /*! STALL_O_DIS0 - Disable Endpoint 0 OUT Direction 1185 * 0b0..Enable 1186 * 0b1..Disable 1187 */ 1188 #define USB_STALL_OL_DIS_STALL_O_DIS0(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS0_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS0_MASK) 1189 1190 #define USB_STALL_OL_DIS_STALL_O_DIS1_MASK (0x2U) 1191 #define USB_STALL_OL_DIS_STALL_O_DIS1_SHIFT (1U) 1192 /*! STALL_O_DIS1 - Disable Endpoint 1 OUT Direction 1193 * 0b0..Enable 1194 * 0b1..Disable 1195 */ 1196 #define USB_STALL_OL_DIS_STALL_O_DIS1(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS1_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS1_MASK) 1197 1198 #define USB_STALL_OL_DIS_STALL_O_DIS2_MASK (0x4U) 1199 #define USB_STALL_OL_DIS_STALL_O_DIS2_SHIFT (2U) 1200 /*! STALL_O_DIS2 - Disable Endpoint 2 OUT Direction 1201 * 0b0..Enable 1202 * 0b1..Disable 1203 */ 1204 #define USB_STALL_OL_DIS_STALL_O_DIS2(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS2_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS2_MASK) 1205 1206 #define USB_STALL_OL_DIS_STALL_O_DIS3_MASK (0x8U) 1207 #define USB_STALL_OL_DIS_STALL_O_DIS3_SHIFT (3U) 1208 /*! STALL_O_DIS3 - Disable Endpoint 3 OUT Direction 1209 * 0b0..Enable 1210 * 0b1..Disable 1211 */ 1212 #define USB_STALL_OL_DIS_STALL_O_DIS3(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS3_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS3_MASK) 1213 1214 #define USB_STALL_OL_DIS_STALL_O_DIS4_MASK (0x10U) 1215 #define USB_STALL_OL_DIS_STALL_O_DIS4_SHIFT (4U) 1216 /*! STALL_O_DIS4 - Disable Endpoint 4 OUT Direction 1217 * 0b0..Enable 1218 * 0b1..Disable 1219 */ 1220 #define USB_STALL_OL_DIS_STALL_O_DIS4(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS4_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS4_MASK) 1221 1222 #define USB_STALL_OL_DIS_STALL_O_DIS5_MASK (0x20U) 1223 #define USB_STALL_OL_DIS_STALL_O_DIS5_SHIFT (5U) 1224 /*! STALL_O_DIS5 - Disable Endpoint 5 OUT Direction 1225 * 0b0..Enable 1226 * 0b1..Disable 1227 */ 1228 #define USB_STALL_OL_DIS_STALL_O_DIS5(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS5_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS5_MASK) 1229 1230 #define USB_STALL_OL_DIS_STALL_O_DIS6_MASK (0x40U) 1231 #define USB_STALL_OL_DIS_STALL_O_DIS6_SHIFT (6U) 1232 /*! STALL_O_DIS6 - Disable Endpoint 6 OUT Direction 1233 * 0b0..Enable 1234 * 0b1..Disable 1235 */ 1236 #define USB_STALL_OL_DIS_STALL_O_DIS6(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS6_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS6_MASK) 1237 1238 #define USB_STALL_OL_DIS_STALL_O_DIS7_MASK (0x80U) 1239 #define USB_STALL_OL_DIS_STALL_O_DIS7_SHIFT (7U) 1240 /*! STALL_O_DIS7 - Disable Endpoint 7 OUT Direction 1241 * 0b0..Enable 1242 * 0b1..Disable 1243 */ 1244 #define USB_STALL_OL_DIS_STALL_O_DIS7(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS7_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS7_MASK) 1245 /*! @} */ 1246 1247 /*! @name STALL_OH_DIS - Peripheral Mode Stall Disable for Endpoints 15 to 8 in OUT Direction */ 1248 /*! @{ */ 1249 1250 #define USB_STALL_OH_DIS_STALL_O_DIS8_MASK (0x1U) 1251 #define USB_STALL_OH_DIS_STALL_O_DIS8_SHIFT (0U) 1252 /*! STALL_O_DIS8 - Disable Endpoint 8 OUT Direction 1253 * 0b0..Enable 1254 * 0b1..Disable 1255 */ 1256 #define USB_STALL_OH_DIS_STALL_O_DIS8(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS8_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS8_MASK) 1257 1258 #define USB_STALL_OH_DIS_STALL_O_DIS9_MASK (0x2U) 1259 #define USB_STALL_OH_DIS_STALL_O_DIS9_SHIFT (1U) 1260 /*! STALL_O_DIS9 - Disable Endpoint 9 OUT Direction 1261 * 0b0..Enable 1262 * 0b1..Disable 1263 */ 1264 #define USB_STALL_OH_DIS_STALL_O_DIS9(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS9_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS9_MASK) 1265 1266 #define USB_STALL_OH_DIS_STALL_O_DIS10_MASK (0x4U) 1267 #define USB_STALL_OH_DIS_STALL_O_DIS10_SHIFT (2U) 1268 /*! STALL_O_DIS10 - Disable Endpoint 10 OUT Direction 1269 * 0b0..Enable 1270 * 0b1..Disable 1271 */ 1272 #define USB_STALL_OH_DIS_STALL_O_DIS10(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS10_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS10_MASK) 1273 1274 #define USB_STALL_OH_DIS_STALL_O_DIS11_MASK (0x8U) 1275 #define USB_STALL_OH_DIS_STALL_O_DIS11_SHIFT (3U) 1276 /*! STALL_O_DIS11 - Disable Endpoint 11 OUT Direction 1277 * 0b0..Enable 1278 * 0b1..Disable 1279 */ 1280 #define USB_STALL_OH_DIS_STALL_O_DIS11(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS11_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS11_MASK) 1281 1282 #define USB_STALL_OH_DIS_STALL_O_DIS12_MASK (0x10U) 1283 #define USB_STALL_OH_DIS_STALL_O_DIS12_SHIFT (4U) 1284 /*! STALL_O_DIS12 - Disable endpoint 12 OUT direction 1285 * 0b0..Enable 1286 * 0b1..Disable 1287 */ 1288 #define USB_STALL_OH_DIS_STALL_O_DIS12(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS12_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS12_MASK) 1289 1290 #define USB_STALL_OH_DIS_STALL_O_DIS13_MASK (0x20U) 1291 #define USB_STALL_OH_DIS_STALL_O_DIS13_SHIFT (5U) 1292 /*! STALL_O_DIS13 - Disable Endpoint 13 OUT Direction 1293 * 0b0..Enable 1294 * 0b1..Disable 1295 */ 1296 #define USB_STALL_OH_DIS_STALL_O_DIS13(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS13_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS13_MASK) 1297 1298 #define USB_STALL_OH_DIS_STALL_O_DIS14_MASK (0x40U) 1299 #define USB_STALL_OH_DIS_STALL_O_DIS14_SHIFT (6U) 1300 /*! STALL_O_DIS14 - Disable Endpoint 14 OUT Direction 1301 * 0b0..Enable 1302 * 0b1..Disable 1303 */ 1304 #define USB_STALL_OH_DIS_STALL_O_DIS14(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS14_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS14_MASK) 1305 1306 #define USB_STALL_OH_DIS_STALL_O_DIS15_MASK (0x80U) 1307 #define USB_STALL_OH_DIS_STALL_O_DIS15_SHIFT (7U) 1308 /*! STALL_O_DIS15 - Disable Endpoint 15 OUT Direction 1309 * 0b0..Enable 1310 * 0b1..Disable 1311 */ 1312 #define USB_STALL_OH_DIS_STALL_O_DIS15(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS15_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS15_MASK) 1313 /*! @} */ 1314 1315 /*! @name CLK_RECOVER_CTRL - USB Clock Recovery Control */ 1316 /*! @{ */ 1317 1318 #define USB_CLK_RECOVER_CTRL_TRIM_INIT_VAL_SEL_MASK (0x8U) 1319 #define USB_CLK_RECOVER_CTRL_TRIM_INIT_VAL_SEL_SHIFT (3U) 1320 /*! TRIM_INIT_VAL_SEL - Selects the source for the initial FIRC trim fine value used after a reset. 1321 * 0b0..Mid-scale 1322 * 0b1..IFR 1323 */ 1324 #define USB_CLK_RECOVER_CTRL_TRIM_INIT_VAL_SEL(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_TRIM_INIT_VAL_SEL_SHIFT)) & USB_CLK_RECOVER_CTRL_TRIM_INIT_VAL_SEL_MASK) 1325 1326 #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK (0x20U) 1327 #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT (5U) 1328 /*! RESTART_IFRTRIM_EN - Restart from IFR Trim Value 1329 * 0b0..Trim fine adjustment always works based on the previous updated trim fine value. 1330 * 0b1..Trim fine restarts from the IFR trim value whenever you detect bus_reset or bus_resume or deassert module enable. 1331 */ 1332 #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK) 1333 1334 #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK (0x40U) 1335 #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT (6U) 1336 /*! RESET_RESUME_ROUGH_EN - Reset or Resume to Rough Phase Enable 1337 * 0b0..Always works in tracking phase after the first time rough phase, to track transition. 1338 * 0b1..Go back to rough stage whenever a bus reset or bus resume occurs. 1339 */ 1340 #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK) 1341 1342 #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK (0x80U) 1343 #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT (7U) 1344 /*! CLOCK_RECOVER_EN - Crystal-Less USB Enable 1345 * 0b0..Disable 1346 * 0b1..Enable 1347 */ 1348 #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK) 1349 /*! @} */ 1350 1351 /*! @name CLK_RECOVER_IRC_EN - FIRC Oscillator Enable */ 1352 /*! @{ */ 1353 1354 #define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK (0x2U) 1355 #define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT (1U) 1356 /*! IRC_EN - Fast IRC enable 1357 * 0b0..Disable 1358 * 0b1..Enable 1359 */ 1360 #define USB_CLK_RECOVER_IRC_EN_IRC_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK) 1361 /*! @} */ 1362 1363 /*! @name CLK_RECOVER_INT_EN - Clock Recovery Combined Interrupt Enable */ 1364 /*! @{ */ 1365 1366 #define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK (0x10U) 1367 #define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT (4U) 1368 /*! OVF_ERROR_EN - Overflow error interrupt enable 1369 * 0b0..The interrupt is masked 1370 * 0b1..The interrupt is enabled 1371 */ 1372 #define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT)) & USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK) 1373 /*! @} */ 1374 1375 /*! @name CLK_RECOVER_INT_STATUS - Clock Recovery Separated Interrupt Status */ 1376 /*! @{ */ 1377 1378 #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK (0x10U) 1379 #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT (4U) 1380 /*! OVF_ERROR - Overflow Error Interrupt Status Flag 1381 * 0b0..Interrupt did not occur 1382 * 0b1..Unmasked interrupt occurred 1383 * 0b0..No effect 1384 * 0b1..Clear the flag 1385 */ 1386 #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT)) & USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK) 1387 /*! @} */ 1388 1389 /*! 1390 * @} 1391 */ 1392 /* end of group USB_Register_Masks */ 1393 1394 /*! 1395 * @brief This type of structure instance is used to implement the buffer descriptor for USB. 1396 */ 1397 typedef struct 1398 { 1399 union { 1400 uint32_t head; /*!< Head. */ 1401 struct 1402 { 1403 uint32_t reserved0 : 2; /*!< RESEVED. */ 1404 uint32_t bdt_stall : 1; /*!< Stall. */ 1405 uint32_t dts : 1; /*!< Data shift sync. */ 1406 uint32_t ninc : 1; /*!< DMA addr cannot increasing. */ 1407 uint32_t keep : 1; /*!< Keep BD held by USB. */ 1408 uint32_t data : 1; /*!< DATA0 or DATA1. */ 1409 uint32_t own : 1; /*!< Owner, 0 is CPU, 1 is USB. */ 1410 uint32_t reserved1 : 8; /*!< RESEVED. */ 1411 uint32_t bc : 10; /*!< Packet size. */ 1412 uint32_t reserved2 : 6; /*!< RESEVED. */ 1413 }; 1414 struct 1415 { 1416 uint32_t reserved3 : 2; /*!< RESEVED. */ 1417 uint32_t tok_pid : 4; /*!< Token pid. */ 1418 uint32_t reserved4 : 26; /*!< RESEVED. */ 1419 }; 1420 }; 1421 uint32_t addr; /*!< Buffer addr. */ 1422 } kinetis_bd_t; 1423 1424 /*! 1425 * @brief This type of structure instance is used to implement the buffer descriptor table for USB. 1426 */ 1427 typedef union { 1428 kinetis_bd_t table[16][2][2]; /*!< [EndPoint] [Direction] [Odd_Even]. */ 1429 uint8_t buffer[512]; /*!< buffer. */ 1430 } kinetis_bd_table_t; 1431 1432 /** 1433 * @brief USBFS TokenPid type. 1434 */ 1435 typedef enum { 1436 USB_TOKEN_PID_OUT = 0x1u, /*!< USB Token Pid: OUT. */ 1437 USB_TOKEN_PID_IN = 0x9u, /*!< USB Token Pid: IN. */ 1438 USB_TOKEN_PID_SETUP = 0xDu, /*!< USB Token Pid: SETUP. */ 1439 USB_TOKEN_PID_DATA0 = 0x03, /*!< USB Token Pid: DATA0. */ 1440 USB_TOKEN_PID_DATA1 = 0x0B, /*!< USB Token Pid: DATA1. */ 1441 USB_TOKEN_PID_ACK = 0x02, /*!< USB Token Pid: ACK. */ 1442 USB_TOKEN_PID_STALL = 0x0E, /*!< USB Token Pid: STALL. */ 1443 USB_TOKEN_PID_NAK = 0x0A, /*!< USB Token Pid: NAK. */ 1444 USB_TOKEN_PID_BUSTIMEOUT = 0x00, /*!< USB Token Pid: BUSTO. */ 1445 USB_TOKEN_PID_ERR = 0x0f, /*!< USB Token Pid: ERR. */ 1446 } USB_TOKEN_PID_Type; 1447 1448 typedef struct { 1449 KINETIS_TypeDef base; 1450 __IO uint8_t USBCTRL; /**< USB Control, offset: 0x100 */ 1451 uint8_t RESERVED_22[3]; 1452 __I uint8_t OBSERVE; /**< USB OTG Observe, offset: 0x104 */ 1453 uint8_t RESERVED_23[3]; 1454 __IO uint8_t CONTROL; /**< USB OTG Control, offset: 0x108 */ 1455 uint8_t RESERVED_24[3]; 1456 __IO uint8_t USBTRC0; /**< USB Transceiver Control 0, offset: 0x10C */ 1457 uint8_t RESERVED_25[7]; 1458 __IO uint8_t USBFRMADJUST; /**< Frame Adjust, offset: 0x114 */ 1459 uint8_t RESERVED_26[15]; 1460 __IO uint8_t KEEP_ALIVE_CTRL; /**< Keep Alive Mode Control, offset: 0x124 */ 1461 uint8_t RESERVED_27[3]; 1462 __IO uint8_t KEEP_ALIVE_WKCTRL; /**< Keep Alive Mode Wakeup Control, offset: 0x128 */ 1463 uint8_t RESERVED_28[3]; 1464 __IO uint8_t MISCCTRL; /**< Miscellaneous Control, offset: 0x12C */ 1465 uint8_t RESERVED_29[3]; 1466 __IO uint8_t STALL_IL_DIS; /**< Peripheral Mode Stall Disable for Endpoints 7 to 0 in IN Direction, offset: 0x130 */ 1467 uint8_t RESERVED_30[3]; 1468 __IO uint8_t STALL_IH_DIS; /**< Peripheral Mode Stall Disable for Endpoints 15 to 8 in IN Direction, offset: 0x134 */ 1469 uint8_t RESERVED_31[3]; 1470 __IO uint8_t STALL_OL_DIS; /**< Peripheral Mode Stall Disable for Endpoints 7 to 0 in OUT Direction, offset: 0x138 */ 1471 uint8_t RESERVED_32[3]; 1472 __IO uint8_t STALL_OH_DIS; /**< Peripheral Mode Stall Disable for Endpoints 15 to 8 in OUT Direction, offset: 0x13C */ 1473 uint8_t RESERVED_33[3]; 1474 __IO uint8_t CLK_RECOVER_CTRL; /**< USB Clock Recovery Control, offset: 0x140 */ 1475 uint8_t RESERVED_34[3]; 1476 __IO uint8_t CLK_RECOVER_IRC_EN; /**< FIRC Oscillator Enable, offset: 0x144 */ 1477 uint8_t RESERVED_35[15]; 1478 __IO uint8_t CLK_RECOVER_INT_EN; /**< Clock Recovery Combined Interrupt Enable, offset: 0x154 */ 1479 uint8_t RESERVED_36[7]; 1480 __IO uint8_t CLK_RECOVER_INT_STATUS; /**< Clock Recovery Separated Interrupt Status, offset: 0x15C */ 1481 } KINETIS_MCX_TypeDef; 1482 1483 void usb_dc_low_level_init(uint8_t busid); 1484 void usb_dc_low_level_deinit(uint8_t busid); 1485 1486 void usbd_kinetis_delay_ms(uint8_t ms); 1487 #endif