1 /*
2  *  Copyright (C) 2017-2024 Alibaba Group Holding Limited
3  */
4 
5 /*******************************************************
6  * @file    dw_timer_ll.h
7  * @brief   header file for timer ll driver
8  * @version V1.0
9  * @date    9. April 2020
10  * ******************************************************/
11 
12 #ifndef _DW_TIMER_LL_H_
13 #define _DW_TIMER_LL_H_
14 
15 #include <stdio.h>
16 #include <soc.h>
17 #include <csi_core.h>
18 
19 #ifdef __cplusplus
20 extern "C"
21 {
22 #endif
23 
24 /*! Timer1 Control Reg,     offset: 0x08 */
25 #define DW_TIMER_CTL_ENABLE_SEL_Pos                                    (0U)
26 #define DW_TIMER_CTL_ENABLE_SEL_Msk                                    (0x1U << DW_TIMER_CTL_ENABLE_SEL_Pos)
27 #define DW_TIMER_CTL_ENABLE_SEL_EN                                     DW_TIMER_CTL_ENABLE_SEL_Msk
28 
29 #define DW_TIMER_CTL_MODE_SEL_Pos                                      (1U)
30 #define DW_TIMER_CTL_MODE_SEL_Msk                                      (0x1U << DW_TIMER_CTL_MODE_SEL_Pos)
31 #define DW_TIMER_CTL_MODE_SEL_EN                                       DW_TIMER_CTL_MODE_SEL_Msk
32 
33 #define DW_TIMER_CTL_INT_MASK_Pos                                      (2U)
34 #define DW_TIMER_CTL_INT_MASK_Msk                                      (0x1U << DW_TIMER_CTL_INT_MASK_Pos)
35 #define DW_TIMER_CTL_INT_MAKS_EN                                       DW_TIMER_CTL_INT_MASK_Msk
36 
37 #define DW_TIMER_CTL_HARD_TRIG_Pos                                     (4U)
38 #define DW_TIMER_CTL_HARD_TRIG_Msk                                     (0x1U << DW_TIMER_CTL_HARD_TRIG_Pos)
39 #define DW_TIMER_CTL_HARD_TRIG_EN                                      DW_TIMER_CTL_HARD_TRIG_Msk
40 
41 /*! Timer EOI,            offset: 0x0c */
42 #define DW_TIMER_EOI_REG_Pos                                           (0U)
43 #define DW_TIMER_EOI_REG_Msk                                           (0x1U << DW_TIMER_EOI_REG_Pos)
44 #define DW_TIMER_EOI_REG_EN                                            DW_TIMER_EOI_REG_Msk
45 
46 /*! Timer Int Status,     offset: 0x10 */
47 #define DW_TIMER_INT_STATUS_Pos                                        (0U)
48 #define DW_TIMER_INT_STATUS_Msk                                        (0x1U << DW_TIMER_INT_STATUS_Pos)
49 #define DW_TIMER_INT_STATUS_EN                                         DW_TIMER_INT_STATUS_Msk
50 
51 /*! Timers Int Status,    offset: 0xa0 */
52 #define DW_TIMERS_INT_STATUS_Pos                                       (0U)
53 #define DW_TIMERS_INT_STATUS_Msk                                       (0x2U << DW_TIMERS_INT_STATUS_Pos)
54 #define DW_TIMERS_INT_STATUS_EN                                        DW_TIMERS_INT_STATUS_Msk
55 
56 /*! Timers EOI,           offset: 0xa4 */
57 #define DW_TIMERS_EOI_REG_Pos                                          (0U)
58 #define DW_TIMERS_EOI_REG_Msk                                          (0x2U << DW_TIMERS_EOI_REG_Pos)
59 #define DW_TIMERS_EOI_REG_EN                                           DW_TIMERS_EOI_REG_Msk
60 
61 /*! Timers Raw Int Status,offset: 0xa8 */
62 #define DW_TIMERS_RAW_INT_STA_Pos                                      (0U)
63 #define DW_TIMERS_RAW_INT_STA_Msk                                      (0x2U << DW_TIMERS_RAW_INT_STA_Pos)
64 #define DW_TIMERS_RAW_INT_STA_EN                                       DW_TIMERS_RAW_INT_STA_Msk
65 
66 typedef struct {
67     __IOM uint32_t TLC;                                                /* Offset: 0x000 (R/W) TimerLoadCount */
68     __IM  uint32_t TCV;                                                /* Offset: 0x004 (R/ ) TimerCurrentValue */
69     __IOM uint32_t TCR;                                                /* Offset: 0x008 (R/W) TimerControlReg */
70     __IM  uint32_t TEOI;                                               /* Offset: 0x00c (R/ ) TimerEOI */
71     __IM  uint32_t TIS;                                                /* Offset: 0x010 (R/ ) TimerIntStatus */
72 } dw_timer_regs_t;
73 
74 typedef struct {
75     dw_timer_regs_t timer[8];
76     __IM  uint32_t TSIS;                                               /* Offset: 0x0a0 (R/ ) TimersIntStatus */
77     __IM  uint32_t TSEOI;                                              /* Offset: 0x0a4 (R/ ) TimersEOI */
78     __IM  uint32_t TSRIS;                                              /* Offset: 0x0a8 (R/ ) TimersRawIntStatus */
79 } dw_timer_general_regs_t;
80 
dw_timer_read_load(dw_timer_regs_t * timer_base)81 static inline uint32_t dw_timer_read_load(dw_timer_regs_t *timer_base)
82 {
83     return (timer_base->TLC);
84 }
dw_timer_write_load(dw_timer_regs_t * timer_base,uint32_t value)85 static inline void dw_timer_write_load(dw_timer_regs_t *timer_base, uint32_t value)
86 {
87     timer_base->TLC = value;
88 }
dw_timer_get_current(dw_timer_regs_t * timer_base)89 static inline uint32_t dw_timer_get_current(dw_timer_regs_t *timer_base)
90 {
91     return (timer_base->TCV);
92 }
dw_timer_set_enable(dw_timer_regs_t * timer_base)93 static inline void dw_timer_set_enable(dw_timer_regs_t *timer_base)
94 {
95     timer_base->TCR |= (DW_TIMER_CTL_ENABLE_SEL_EN);
96 }
dw_timer_set_disable(dw_timer_regs_t * timer_base)97 static inline void dw_timer_set_disable(dw_timer_regs_t *timer_base)
98 {
99     timer_base->TCR &= ~(DW_TIMER_CTL_ENABLE_SEL_EN);
100 }
dw_timer_get_enable(dw_timer_regs_t * timer_base)101 static inline uint32_t dw_timer_get_enable(dw_timer_regs_t *timer_base)
102 {
103     return (((timer_base->TCR) & DW_TIMER_CTL_ENABLE_SEL_EN) ? (uint32_t)1 : (uint32_t)0);
104 }
dw_timer_set_mode_free(dw_timer_regs_t * timer_base)105 static inline void dw_timer_set_mode_free(dw_timer_regs_t *timer_base)
106 {
107     timer_base->TCR &= ~(DW_TIMER_CTL_MODE_SEL_EN);
108 }
dw_timer_set_mode_load(dw_timer_regs_t * timer_base)109 static inline void dw_timer_set_mode_load(dw_timer_regs_t *timer_base)
110 {
111     timer_base->TCR |= (DW_TIMER_CTL_MODE_SEL_EN);
112 }
dw_timer_get_model(dw_timer_regs_t * timer_base)113 static inline uint32_t dw_timer_get_model(dw_timer_regs_t *timer_base)
114 {
115     return (((timer_base->TCR) & DW_TIMER_CTL_MODE_SEL_EN) ? (uint32_t)1 : (uint32_t)0);
116 }
dw_timer_set_mask(dw_timer_regs_t * timer_base)117 static inline void dw_timer_set_mask(dw_timer_regs_t *timer_base)
118 {
119     timer_base->TCR |= (DW_TIMER_CTL_INT_MAKS_EN);
120 }
dw_timer_set_unmask(dw_timer_regs_t * timer_base)121 static inline void dw_timer_set_unmask(dw_timer_regs_t *timer_base)
122 {
123     timer_base->TCR &= ~(DW_TIMER_CTL_INT_MAKS_EN);
124 }
dw_timer_get_mask(dw_timer_regs_t * timer_base)125 static inline uint32_t dw_timer_get_mask(dw_timer_regs_t *timer_base)
126 {
127     return (((timer_base->TCR) & DW_TIMER_CTL_INT_MAKS_EN) ? (uint32_t)1 : (uint32_t)0);
128 }
dw_timer_set_hardtrigger_en(dw_timer_regs_t * timer_base)129 static inline void dw_timer_set_hardtrigger_en(dw_timer_regs_t *timer_base)
130 {
131     timer_base->TCR |= (DW_TIMER_CTL_HARD_TRIG_EN);
132 }
dw_timer_set_hardtrigger_dis(dw_timer_regs_t * timer_base)133 static inline void dw_timer_set_hardtrigger_dis(dw_timer_regs_t *timer_base)
134 {
135     timer_base->TCR &= ~(DW_TIMER_CTL_HARD_TRIG_EN);
136 }
dw_timer_get_hardtrigger(dw_timer_regs_t * timer_base)137 static inline uint32_t dw_timer_get_hardtrigger(dw_timer_regs_t *timer_base)
138 {
139     return (((timer_base->TCR) & DW_TIMER_CTL_HARD_TRIG_EN) ? (uint32_t)1 : (uint32_t)0);
140 }
dw_timer_clear_irq(dw_timer_regs_t * timer_base)141 static inline uint32_t dw_timer_clear_irq(dw_timer_regs_t *timer_base)
142 {
143     return (((timer_base->TEOI) & DW_TIMER_EOI_REG_EN) ? (uint32_t)1 : (uint32_t)0);
144 }
dw_timer_get_int_status(dw_timer_regs_t * timer_base)145 static inline uint32_t dw_timer_get_int_status(dw_timer_regs_t *timer_base)
146 {
147     return (((timer_base->TIS) & DW_TIMER_INT_STATUS_EN) ? (uint32_t)1 : (uint32_t)0);
148 }
dw_timer_general_active_after_mask(dw_timer_general_regs_t * timer_base)149 static inline uint32_t dw_timer_general_active_after_mask(dw_timer_general_regs_t *timer_base)
150 {
151     return ((timer_base->TSIS) & DW_TIMERS_INT_STATUS_EN);
152 }
dw_timer_general_clear_irq(dw_timer_general_regs_t * timer_base)153 static inline uint32_t dw_timer_general_clear_irq(dw_timer_general_regs_t *timer_base)
154 {
155     return ((timer_base->TSEOI) & DW_TIMERS_EOI_REG_EN);
156 }
dw_timer_general_active_prior_mask(dw_timer_general_regs_t * timer_base)157 static inline uint32_t dw_timer_general_active_prior_mask(dw_timer_general_regs_t *timer_base)
158 {
159     return ((timer_base->TSRIS) & DW_TIMERS_RAW_INT_STA_EN);
160 }
161 
162 
163 #ifdef __cplusplus
164 }
165 #endif
166 
167 #endif /* _DW_TIMER_LL_H_ */
168