1 /*
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * Copyright 2016-2017 NXP
4 *
5 * Redistribution and use in source and binary forms, with or without modification,
6 * are permitted provided that the following conditions are met:
7 *
8 * o Redistributions of source code must retain the above copyright notice, this list
9 * of conditions and the following disclaimer.
10 *
11 * o Redistributions in binary form must reproduce the above copyright notice, this
12 * list of conditions and the following disclaimer in the documentation and/or
13 * other materials provided with the distribution.
14 *
15 * o Neither the name of the copyright holder nor the names of its
16 * contributors may be used to endorse or promote products derived from this
17 * software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
31 #ifndef _FSL_ADC16_H_
32 #define _FSL_ADC16_H_
33
34 #include "fsl_common.h"
35
36 /*!
37 * @addtogroup adc16
38 * @{
39 */
40
41
42 /*******************************************************************************
43 * Definitions
44 ******************************************************************************/
45
46 /*! @name Driver version */
47 /*@{*/
48 /*! @brief ADC16 driver version 2.0.0. */
49 #define FSL_ADC16_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
50 /*@}*/
51
52 /*!
53 * @brief Channel status flags.
54 */
55 enum _adc16_channel_status_flags
56 {
57 kADC16_ChannelConversionDoneFlag = ADC_SC1_COCO_MASK, /*!< Conversion done. */
58 };
59
60 /*!
61 * @brief Converter status flags.
62 */
63 enum _adc16_status_flags
64 {
65 kADC16_ActiveFlag = ADC_SC2_ADACT_MASK, /*!< Converter is active. */
66 #if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && FSL_FEATURE_ADC16_HAS_CALIBRATION
67 kADC16_CalibrationFailedFlag = ADC_SC3_CALF_MASK, /*!< Calibration is failed. */
68 #endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */
69 };
70
71 #if defined(FSL_FEATURE_ADC16_HAS_MUX_SELECT) && FSL_FEATURE_ADC16_HAS_MUX_SELECT
72 /*!
73 * @brief Channel multiplexer mode for each channel.
74 *
75 * For some ADC16 channels, there are two pin selections in channel multiplexer. For example, ADC0_SE4a and ADC0_SE4b
76 * are the different channels that share the same channel number.
77 */
78 typedef enum _adc_channel_mux_mode
79 {
80 kADC16_ChannelMuxA = 0U, /*!< For channel with channel mux a. */
81 kADC16_ChannelMuxB = 1U, /*!< For channel with channel mux b. */
82 } adc16_channel_mux_mode_t;
83 #endif /* FSL_FEATURE_ADC16_HAS_MUX_SELECT */
84
85 /*!
86 * @brief Clock divider for the converter.
87 */
88 typedef enum _adc16_clock_divider
89 {
90 kADC16_ClockDivider1 = 0U, /*!< For divider 1 from the input clock to the module. */
91 kADC16_ClockDivider2 = 1U, /*!< For divider 2 from the input clock to the module. */
92 kADC16_ClockDivider4 = 2U, /*!< For divider 4 from the input clock to the module. */
93 kADC16_ClockDivider8 = 3U, /*!< For divider 8 from the input clock to the module. */
94 } adc16_clock_divider_t;
95
96 /*!
97 *@brief Converter's resolution.
98 */
99 typedef enum _adc16_resolution
100 {
101 /* This group of enumeration is for internal use which is related to register setting. */
102 kADC16_Resolution8or9Bit = 0U, /*!< Single End 8-bit or Differential Sample 9-bit. */
103 kADC16_Resolution12or13Bit = 1U, /*!< Single End 12-bit or Differential Sample 13-bit. */
104 kADC16_Resolution10or11Bit = 2U, /*!< Single End 10-bit or Differential Sample 11-bit. */
105
106 /* This group of enumeration is for a public user. */
107 kADC16_ResolutionSE8Bit = kADC16_Resolution8or9Bit, /*!< Single End 8-bit. */
108 kADC16_ResolutionSE12Bit = kADC16_Resolution12or13Bit, /*!< Single End 12-bit. */
109 kADC16_ResolutionSE10Bit = kADC16_Resolution10or11Bit, /*!< Single End 10-bit. */
110 #if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE
111 kADC16_ResolutionDF9Bit = kADC16_Resolution8or9Bit, /*!< Differential Sample 9-bit. */
112 kADC16_ResolutionDF13Bit = kADC16_Resolution12or13Bit, /*!< Differential Sample 13-bit. */
113 kADC16_ResolutionDF11Bit = kADC16_Resolution10or11Bit, /*!< Differential Sample 11-bit. */
114 #endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */
115
116 #if defined(FSL_FEATURE_ADC16_MAX_RESOLUTION) && (FSL_FEATURE_ADC16_MAX_RESOLUTION >= 16U)
117 /* 16-bit is supported by default. */
118 kADC16_Resolution16Bit = 3U, /*!< Single End 16-bit or Differential Sample 16-bit. */
119 kADC16_ResolutionSE16Bit = kADC16_Resolution16Bit, /*!< Single End 16-bit. */
120 #if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE
121 kADC16_ResolutionDF16Bit = kADC16_Resolution16Bit, /*!< Differential Sample 16-bit. */
122 #endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */
123 #endif /* FSL_FEATURE_ADC16_MAX_RESOLUTION >= 16U */
124 } adc16_resolution_t;
125
126 /*!
127 * @brief Clock source.
128 */
129 typedef enum _adc16_clock_source
130 {
131 kADC16_ClockSourceAlt0 = 0U, /*!< Selection 0 of the clock source. */
132 kADC16_ClockSourceAlt1 = 1U, /*!< Selection 1 of the clock source. */
133 kADC16_ClockSourceAlt2 = 2U, /*!< Selection 2 of the clock source. */
134 kADC16_ClockSourceAlt3 = 3U, /*!< Selection 3 of the clock source. */
135
136 /* Chip defined clock source */
137 kADC16_ClockSourceAsynchronousClock = kADC16_ClockSourceAlt3, /*!< Using internal asynchronous clock. */
138 } adc16_clock_source_t;
139
140 /*!
141 * @brief Long sample mode.
142 */
143 typedef enum _adc16_long_sample_mode
144 {
145 kADC16_LongSampleCycle24 = 0U, /*!< 20 extra ADCK cycles, 24 ADCK cycles total. */
146 kADC16_LongSampleCycle16 = 1U, /*!< 12 extra ADCK cycles, 16 ADCK cycles total. */
147 kADC16_LongSampleCycle10 = 2U, /*!< 6 extra ADCK cycles, 10 ADCK cycles total. */
148 kADC16_LongSampleCycle6 = 3U, /*!< 2 extra ADCK cycles, 6 ADCK cycles total. */
149 kADC16_LongSampleDisabled = 4U, /*!< Disable the long sample feature. */
150 } adc16_long_sample_mode_t;
151
152 /*!
153 * @brief Reference voltage source.
154 */
155 typedef enum _adc16_reference_voltage_source
156 {
157 kADC16_ReferenceVoltageSourceVref = 0U, /*!< For external pins pair of VrefH and VrefL. */
158 kADC16_ReferenceVoltageSourceValt = 1U, /*!< For alternate reference pair of ValtH and ValtL. */
159 } adc16_reference_voltage_source_t;
160
161 #if defined(FSL_FEATURE_ADC16_HAS_HW_AVERAGE) && FSL_FEATURE_ADC16_HAS_HW_AVERAGE
162 /*!
163 * @brief Hardware average mode.
164 */
165 typedef enum _adc16_hardware_average_mode
166 {
167 kADC16_HardwareAverageCount4 = 0U, /*!< For hardware average with 4 samples. */
168 kADC16_HardwareAverageCount8 = 1U, /*!< For hardware average with 8 samples. */
169 kADC16_HardwareAverageCount16 = 2U, /*!< For hardware average with 16 samples. */
170 kADC16_HardwareAverageCount32 = 3U, /*!< For hardware average with 32 samples. */
171 kADC16_HardwareAverageDisabled = 4U, /*!< Disable the hardware average feature.*/
172 } adc16_hardware_average_mode_t;
173 #endif /* FSL_FEATURE_ADC16_HAS_HW_AVERAGE */
174
175 /*!
176 * @brief Hardware compare mode.
177 */
178 typedef enum _adc16_hardware_compare_mode
179 {
180 kADC16_HardwareCompareMode0 = 0U, /*!< x < value1. */
181 kADC16_HardwareCompareMode1 = 1U, /*!< x > value1. */
182 kADC16_HardwareCompareMode2 = 2U, /*!< if value1 <= value2, then x < value1 || x > value2;
183 else, value1 > x > value2. */
184 kADC16_HardwareCompareMode3 = 3U, /*!< if value1 <= value2, then value1 <= x <= value2;
185 else x >= value1 || x <= value2. */
186 } adc16_hardware_compare_mode_t;
187
188 #if defined(FSL_FEATURE_ADC16_HAS_PGA) && FSL_FEATURE_ADC16_HAS_PGA
189 /*!
190 * @brief PGA's Gain mode.
191 */
192 typedef enum _adc16_pga_gain
193 {
194 kADC16_PGAGainValueOf1 = 0U, /*!< For amplifier gain of 1. */
195 kADC16_PGAGainValueOf2 = 1U, /*!< For amplifier gain of 2. */
196 kADC16_PGAGainValueOf4 = 2U, /*!< For amplifier gain of 4. */
197 kADC16_PGAGainValueOf8 = 3U, /*!< For amplifier gain of 8. */
198 kADC16_PGAGainValueOf16 = 4U, /*!< For amplifier gain of 16. */
199 kADC16_PGAGainValueOf32 = 5U, /*!< For amplifier gain of 32. */
200 kADC16_PGAGainValueOf64 = 6U, /*!< For amplifier gain of 64. */
201 } adc16_pga_gain_t;
202 #endif /* FSL_FEATURE_ADC16_HAS_PGA */
203
204 /*!
205 * @brief ADC16 converter configuration.
206 */
207 typedef struct _adc16_config
208 {
209 adc16_reference_voltage_source_t referenceVoltageSource; /*!< Select the reference voltage source. */
210 adc16_clock_source_t clockSource; /*!< Select the input clock source to converter. */
211 bool enableAsynchronousClock; /*!< Enable the asynchronous clock output. */
212 adc16_clock_divider_t clockDivider; /*!< Select the divider of input clock source. */
213 adc16_resolution_t resolution; /*!< Select the sample resolution mode. */
214 adc16_long_sample_mode_t longSampleMode; /*!< Select the long sample mode. */
215 bool enableHighSpeed; /*!< Enable the high-speed mode. */
216 bool enableLowPower; /*!< Enable low power. */
217 bool enableContinuousConversion; /*!< Enable continuous conversion mode. */
218 } adc16_config_t;
219
220 /*!
221 * @brief ADC16 Hardware comparison configuration.
222 */
223 typedef struct _adc16_hardware_compare_config
224 {
225 adc16_hardware_compare_mode_t hardwareCompareMode; /*!< Select the hardware compare mode.
226 See "adc16_hardware_compare_mode_t". */
227 int16_t value1; /*!< Setting value1 for hardware compare mode. */
228 int16_t value2; /*!< Setting value2 for hardware compare mode. */
229 } adc16_hardware_compare_config_t;
230
231 /*!
232 * @brief ADC16 channel conversion configuration.
233 */
234 typedef struct _adc16_channel_config
235 {
236 uint32_t channelNumber; /*!< Setting the conversion channel number. The available range is 0-31.
237 See channel connection information for each chip in Reference
238 Manual document. */
239 bool enableInterruptOnConversionCompleted; /*!< Generate an interrupt request once the conversion is completed. */
240 #if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE
241 bool enableDifferentialConversion; /*!< Using Differential sample mode. */
242 #endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */
243 } adc16_channel_config_t;
244
245 #if defined(FSL_FEATURE_ADC16_HAS_PGA) && FSL_FEATURE_ADC16_HAS_PGA
246 /*!
247 * @brief ADC16 programmable gain amplifier configuration.
248 */
249 typedef struct _adc16_pga_config
250 {
251 adc16_pga_gain_t pgaGain; /*!< Setting PGA gain. */
252 bool enableRunInNormalMode; /*!< Enable PGA working in normal mode, or low power mode by default. */
253 #if defined(FSL_FEATURE_ADC16_HAS_PGA_CHOPPING) && FSL_FEATURE_ADC16_HAS_PGA_CHOPPING
254 bool disablePgaChopping; /*!< Disable the PGA chopping function.
255 The PGA employs chopping to remove/reduce offset and 1/f noise and offers
256 an offset measurement configuration that aids the offset calibration. */
257 #endif /* FSL_FEATURE_ADC16_HAS_PGA_CHOPPING */
258 #if defined(FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT) && FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT
259 bool enableRunInOffsetMeasurement; /*!< Enable the PGA working in offset measurement mode.
260 When this feature is enabled, the PGA disconnects itself from the external
261 inputs and auto-configures into offset measurement mode. With this field
262 set, run the ADC in the recommended settings and enable the maximum hardware
263 averaging to get the PGA offset number. The output is the
264 (PGA offset * (64+1)) for the given PGA setting. */
265 #endif /* FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT */
266 } adc16_pga_config_t;
267 #endif /* FSL_FEATURE_ADC16_HAS_PGA */
268
269 #if defined(__cplusplus)
270 extern "C" {
271 #endif
272
273 /*******************************************************************************
274 * API
275 ******************************************************************************/
276
277 /*!
278 * @name Initialization
279 * @{
280 */
281
282 /*!
283 * @brief Initializes the ADC16 module.
284 *
285 * @param base ADC16 peripheral base address.
286 * @param config Pointer to configuration structure. See "adc16_config_t".
287 */
288 void ADC16_Init(ADC_Type *base, const adc16_config_t *config);
289
290 /*!
291 * @brief De-initializes the ADC16 module.
292 *
293 * @param base ADC16 peripheral base address.
294 */
295 void ADC16_Deinit(ADC_Type *base);
296
297 /*!
298 * @brief Gets an available pre-defined settings for the converter's configuration.
299 *
300 * This function initializes the converter configuration structure with available settings. The default values are as follows.
301 * @code
302 * config->referenceVoltageSource = kADC16_ReferenceVoltageSourceVref;
303 * config->clockSource = kADC16_ClockSourceAsynchronousClock;
304 * config->enableAsynchronousClock = true;
305 * config->clockDivider = kADC16_ClockDivider8;
306 * config->resolution = kADC16_ResolutionSE12Bit;
307 * config->longSampleMode = kADC16_LongSampleDisabled;
308 * config->enableHighSpeed = false;
309 * config->enableLowPower = false;
310 * config->enableContinuousConversion = false;
311 * @endcode
312 * @param config Pointer to the configuration structure.
313 */
314 void ADC16_GetDefaultConfig(adc16_config_t *config);
315
316 #if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && FSL_FEATURE_ADC16_HAS_CALIBRATION
317 /*!
318 * @brief Automates the hardware calibration.
319 *
320 * This auto calibration helps to adjust the plus/minus side gain automatically.
321 * Execute the calibration before using the converter. Note that the hardware trigger should be used
322 * during the calibration.
323 *
324 * @param base ADC16 peripheral base address.
325 *
326 * @return Execution status.
327 * @retval kStatus_Success Calibration is done successfully.
328 * @retval kStatus_Fail Calibration has failed.
329 */
330 status_t ADC16_DoAutoCalibration(ADC_Type *base);
331 #endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */
332
333 #if defined(FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION) && FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION
334 /*!
335 * @brief Sets the offset value for the conversion result.
336 *
337 * This offset value takes effect on the conversion result. If the offset value is not zero, the reading result
338 * is subtracted by it. Note, the hardware calibration fills the offset value automatically.
339 *
340 * @param base ADC16 peripheral base address.
341 * @param value Setting offset value.
342 */
ADC16_SetOffsetValue(ADC_Type * base,int16_t value)343 static inline void ADC16_SetOffsetValue(ADC_Type *base, int16_t value)
344 {
345 base->OFS = (uint32_t)(value);
346 }
347 #endif /* FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION */
348
349 /* @} */
350
351 /*!
352 * @name Advanced Features
353 * @{
354 */
355
356 #if defined(FSL_FEATURE_ADC16_HAS_DMA) && FSL_FEATURE_ADC16_HAS_DMA
357 /*!
358 * @brief Enables generating the DMA trigger when the conversion is complete.
359 *
360 * @param base ADC16 peripheral base address.
361 * @param enable Switcher of the DMA feature. "true" means enabled, "false" means not enabled.
362 */
ADC16_EnableDMA(ADC_Type * base,bool enable)363 static inline void ADC16_EnableDMA(ADC_Type *base, bool enable)
364 {
365 if (enable)
366 {
367 base->SC2 |= ADC_SC2_DMAEN_MASK;
368 }
369 else
370 {
371 base->SC2 &= ~ADC_SC2_DMAEN_MASK;
372 }
373 }
374 #endif /* FSL_FEATURE_ADC16_HAS_DMA */
375
376 /*!
377 * @brief Enables the hardware trigger mode.
378 *
379 * @param base ADC16 peripheral base address.
380 * @param enable Switcher of the hardware trigger feature. "true" means enabled, "false" means not enabled.
381 */
ADC16_EnableHardwareTrigger(ADC_Type * base,bool enable)382 static inline void ADC16_EnableHardwareTrigger(ADC_Type *base, bool enable)
383 {
384 if (enable)
385 {
386 base->SC2 |= ADC_SC2_ADTRG_MASK;
387 }
388 else
389 {
390 base->SC2 &= ~ADC_SC2_ADTRG_MASK;
391 }
392 }
393
394 #if defined(FSL_FEATURE_ADC16_HAS_MUX_SELECT) && FSL_FEATURE_ADC16_HAS_MUX_SELECT
395 /*!
396 * @brief Sets the channel mux mode.
397 *
398 * Some sample pins share the same channel index. The channel mux mode decides which pin is used for an
399 * indicated channel.
400 *
401 * @param base ADC16 peripheral base address.
402 * @param mode Setting channel mux mode. See "adc16_channel_mux_mode_t".
403 */
404 void ADC16_SetChannelMuxMode(ADC_Type *base, adc16_channel_mux_mode_t mode);
405 #endif /* FSL_FEATURE_ADC16_HAS_MUX_SELECT */
406
407 /*!
408 * @brief Configures the hardware compare mode.
409 *
410 * The hardware compare mode provides a way to process the conversion result automatically by using hardware. Only the result
411 * in the compare range is available. To compare the range, see "adc16_hardware_compare_mode_t" or the appopriate reference
412 * manual for more information.
413 *
414 * @param base ADC16 peripheral base address.
415 * @param config Pointer to the "adc16_hardware_compare_config_t" structure. Passing "NULL" disables the feature.
416 */
417 void ADC16_SetHardwareCompareConfig(ADC_Type *base, const adc16_hardware_compare_config_t *config);
418
419 #if defined(FSL_FEATURE_ADC16_HAS_HW_AVERAGE) && FSL_FEATURE_ADC16_HAS_HW_AVERAGE
420 /*!
421 * @brief Sets the hardware average mode.
422 *
423 * The hardware average mode provides a way to process the conversion result automatically by using hardware. The multiple
424 * conversion results are accumulated and averaged internally making them easier to read.
425 *
426 * @param base ADC16 peripheral base address.
427 * @param mode Setting the hardware average mode. See "adc16_hardware_average_mode_t".
428 */
429 void ADC16_SetHardwareAverage(ADC_Type *base, adc16_hardware_average_mode_t mode);
430 #endif /* FSL_FEATURE_ADC16_HAS_HW_AVERAGE */
431
432 #if defined(FSL_FEATURE_ADC16_HAS_PGA) && FSL_FEATURE_ADC16_HAS_PGA
433 /*!
434 * @brief Configures the PGA for the converter's front end.
435 *
436 * @param base ADC16 peripheral base address.
437 * @param config Pointer to the "adc16_pga_config_t" structure. Passing "NULL" disables the feature.
438 */
439 void ADC16_SetPGAConfig(ADC_Type *base, const adc16_pga_config_t *config);
440 #endif /* FSL_FEATURE_ADC16_HAS_PGA */
441
442 /*!
443 * @brief Gets the status flags of the converter.
444 *
445 * @param base ADC16 peripheral base address.
446 *
447 * @return Flags' mask if indicated flags are asserted. See "_adc16_status_flags".
448 */
449 uint32_t ADC16_GetStatusFlags(ADC_Type *base);
450
451 /*!
452 * @brief Clears the status flags of the converter.
453 *
454 * @param base ADC16 peripheral base address.
455 * @param mask Mask value for the cleared flags. See "_adc16_status_flags".
456 */
457 void ADC16_ClearStatusFlags(ADC_Type *base, uint32_t mask);
458
459 /* @} */
460
461 /*!
462 * @name Conversion Channel
463 * @{
464 */
465
466 /*!
467 * @brief Configures the conversion channel.
468 *
469 * This operation triggers the conversion when in software trigger mode. When in hardware trigger mode, this API
470 * configures the channel while the external trigger source helps to trigger the conversion.
471 *
472 * Note that the "Channel Group" has a detailed description.
473 * To allow sequential conversions of the ADC to be triggered by internal peripherals, the ADC has more than one
474 * group of status and control registers, one for each conversion. The channel group parameter indicates which group of
475 * registers are used, for example, channel group 0 is for Group A registers and channel group 1 is for Group B registers. The
476 * channel groups are used in a "ping-pong" approach to control the ADC operation. At any point, only one of
477 * the channel groups is actively controlling ADC conversions. The channel group 0 is used for both software and hardware
478 * trigger modes. Channel group 1 and greater indicates multiple channel group registers for
479 * use only in hardware trigger mode. See the chip configuration information in the appropriate MCU reference manual for the
480 * number of SC1n registers (channel groups) specific to this device. Channel group 1 or greater are not used
481 * for software trigger operation. Therefore, writing to these channel groups does not initiate a new conversion.
482 * Updating the channel group 0 while a different channel group is actively controlling a conversion is allowed and
483 * vice versa. Writing any of the channel group registers while that specific channel group is actively controlling a
484 * conversion aborts the current conversion.
485 *
486 * @param base ADC16 peripheral base address.
487 * @param channelGroup Channel group index.
488 * @param config Pointer to the "adc16_channel_config_t" structure for the conversion channel.
489 */
490 void ADC16_SetChannelConfig(ADC_Type *base, uint32_t channelGroup, const adc16_channel_config_t *config);
491
492 /*!
493 * @brief Gets the conversion value.
494 *
495 * @param base ADC16 peripheral base address.
496 * @param channelGroup Channel group index.
497 *
498 * @return Conversion value.
499 */
ADC16_GetChannelConversionValue(ADC_Type * base,uint32_t channelGroup)500 static inline uint32_t ADC16_GetChannelConversionValue(ADC_Type *base, uint32_t channelGroup)
501 {
502 assert(channelGroup < ADC_R_COUNT);
503
504 return base->R[channelGroup];
505 }
506
507 /*!
508 * @brief Gets the status flags of channel.
509 *
510 * @param base ADC16 peripheral base address.
511 * @param channelGroup Channel group index.
512 *
513 * @return Flags' mask if indicated flags are asserted. See "_adc16_channel_status_flags".
514 */
515 uint32_t ADC16_GetChannelStatusFlags(ADC_Type *base, uint32_t channelGroup);
516
517 /* @} */
518
519 #if defined(__cplusplus)
520 }
521 #endif
522 /*!
523 * @}
524 */
525 #endif /* _FSL_ADC16_H_ */
526