1 /* 2 * Copyright (c) 2006-2021, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2018-10-03 Bernard The first version 9 */ 10 #ifndef RISCV_STACKFRAME_H 11 12 #define RISCV_STACKFRAME_H 13 14 #include "cpuport.h" 15 16 typedef struct rt_hw_stack_frame 17 { 18 rt_ubase_t epc; /* epc - epc - program counter */ 19 rt_ubase_t ra; /* x1 - ra - return address for jumps */ 20 rt_ubase_t mstatus; /* - machine status register */ 21 rt_ubase_t gp; /* x3 - gp - global pointer */ 22 rt_ubase_t tp; /* x4 - tp - thread pointer */ 23 rt_ubase_t t0; /* x5 - t0 - temporary register 0 */ 24 rt_ubase_t t1; /* x6 - t1 - temporary register 1 */ 25 rt_ubase_t t2; /* x7 - t2 - temporary register 2 */ 26 rt_ubase_t s0_fp; /* x8 - s0/fp - saved register 0 or frame pointer */ 27 rt_ubase_t s1; /* x9 - s1 - saved register 1 */ 28 rt_ubase_t a0; /* x10 - a0 - return value or function argument 0 */ 29 rt_ubase_t a1; /* x11 - a1 - return value or function argument 1 */ 30 rt_ubase_t a2; /* x12 - a2 - function argument 2 */ 31 rt_ubase_t a3; /* x13 - a3 - function argument 3 */ 32 rt_ubase_t a4; /* x14 - a4 - function argument 4 */ 33 rt_ubase_t a5; /* x15 - a5 - function argument 5 */ 34 #ifndef __riscv_32e 35 rt_ubase_t a6; /* x16 - a6 - function argument 6 */ 36 rt_ubase_t a7; /* x17 - a7 - function argument 7 */ 37 rt_ubase_t s2; /* x18 - s2 - saved register 2 */ 38 rt_ubase_t s3; /* x19 - s3 - saved register 3 */ 39 rt_ubase_t s4; /* x20 - s4 - saved register 4 */ 40 rt_ubase_t s5; /* x21 - s5 - saved register 5 */ 41 rt_ubase_t s6; /* x22 - s6 - saved register 6 */ 42 rt_ubase_t s7; /* x23 - s7 - saved register 7 */ 43 rt_ubase_t s8; /* x24 - s8 - saved register 8 */ 44 rt_ubase_t s9; /* x25 - s9 - saved register 9 */ 45 rt_ubase_t s10; /* x26 - s10 - saved register 10 */ 46 rt_ubase_t s11; /* x27 - s11 - saved register 11 */ 47 rt_ubase_t t3; /* x28 - t3 - temporary register 3 */ 48 rt_ubase_t t4; /* x29 - t4 - temporary register 4 */ 49 rt_ubase_t t5; /* x30 - t5 - temporary register 5 */ 50 rt_ubase_t t6; /* x31 - t6 - temporary register 6 */ 51 #endif 52 #ifdef ARCH_RISCV_FPU 53 rv_floatreg_t f0; /* f0 */ 54 rv_floatreg_t f1; /* f1 */ 55 rv_floatreg_t f2; /* f2 */ 56 rv_floatreg_t f3; /* f3 */ 57 rv_floatreg_t f4; /* f4 */ 58 rv_floatreg_t f5; /* f5 */ 59 rv_floatreg_t f6; /* f6 */ 60 rv_floatreg_t f7; /* f7 */ 61 rv_floatreg_t f8; /* f8 */ 62 rv_floatreg_t f9; /* f9 */ 63 rv_floatreg_t f10; /* f10 */ 64 rv_floatreg_t f11; /* f11 */ 65 rv_floatreg_t f12; /* f12 */ 66 rv_floatreg_t f13; /* f13 */ 67 rv_floatreg_t f14; /* f14 */ 68 rv_floatreg_t f15; /* f15 */ 69 rv_floatreg_t f16; /* f16 */ 70 rv_floatreg_t f17; /* f17 */ 71 rv_floatreg_t f18; /* f18 */ 72 rv_floatreg_t f19; /* f19 */ 73 rv_floatreg_t f20; /* f20 */ 74 rv_floatreg_t f21; /* f21 */ 75 rv_floatreg_t f22; /* f22 */ 76 rv_floatreg_t f23; /* f23 */ 77 rv_floatreg_t f24; /* f24 */ 78 rv_floatreg_t f25; /* f25 */ 79 rv_floatreg_t f26; /* f26 */ 80 rv_floatreg_t f27; /* f27 */ 81 rv_floatreg_t f28; /* f28 */ 82 rv_floatreg_t f29; /* f29 */ 83 rv_floatreg_t f30; /* f30 */ 84 rv_floatreg_t f31; /* f31 */ 85 #endif 86 }rt_hw_stack_frame_t; 87 88 #endif /* RISCV_STACKFRAME_H */ 89