1/*
2 * Copyright (c) 2006-2020, YICHIP Development Team
3 * @file     yc_startup_yc3122.s
4 * @brief    source file for setting startup_yc3122
5 *
6 * Change Logs:
7 * Date           Author             Version        Notes
8 * 2020-11-06     wushengyan         V1.0.0         the first version
9 */
10
11#define REGBYTES (4)
12/* Enable interrupts when returning from the handler */
13#define MSTATUS_PRV1 0x1880
14#define MSTATUS_MIE  0x00000008
15#define MSTATUS_FS   0x00006000
16
17	.equ __stack_size,0x9000
18
19	.text
20	.globl flash_start
21	.globl delay
22	.globl __stack_size
23	.section .text.startup
24flash_start:
25	la sp, _stack
26
27	/* set exception and irq mtvec */
28	la a0,trap
29	ori a0,a0,1
30	csrw mtvec,a0
31
32	/* enable fs */
33	li t0,MSTATUS_FS
34	csrs mstatus,t0
35	csrw fcsr,x0
36
37	/* Load data section */
38	la a0, _sidata
39	la a1, _sdata
40	la a2, _edata
41	bgeu a1,a2,2f
421:
43	lw t0, (a0)
44	sw t0, (a1)
45	addi a0,a0,4
46	addi a1,a1,4
47	bltu a1,a2,1b
482:
49	/* clear bss section */
50	la a0,_sbss
51	la a1,_ebss
52	bgeu a0,a1,2f
531:
54	sw zero,(a0)
55	addi a0,a0,4
56	bltu a0,a1,1b
572:
58	/*clear heap/statck*/
59	la a0,_ebss
60	la a1,_stack
61	bgeu a0,a1,2f
621:
63	sw zero,(a0)
64	addi a0,a0,4
65	bltu a0,a1,1b
662:
67
68#ifndef __NO_SYSTEM_INIT
69//        jal systeminit
70#endif
71
72#ifndef __NO_BOARD_INIT
73//        jal board_init
74#endif
75	li t0, 0x00000800
76	csrs 0x304,t0
77
78	li t0, MSTATUS_MIE
79	csrs mstatus, t0
80
81	jal main
82
83        /* never retch here*/
84__exit:
85	j __exit
86
87
88
89
90
91
92.macro DISABLE_MIE
93    csrc mstatus, MSTATUS_MIE
94.endm
95
96.macro ENABLE_MIE
97    csrs mstatus, MSTATUS_MIE
98.endm
99
100.macro GET_IRQ_NUM
101    li t1,0x000E4004
102    lw t1,0(t1)
103    li t3,0x01
104    li t5,0x00
105get_irq_num_loop:
106    and t4, t1, t3
107    blt  x0, t4, get_irq_num_end
108    addi t5, t5, 1
109    slli t3, t3, 1
110    j get_irq_num_loop
111get_irq_num_end:
112    mv   t1,  t5
113.endm
114
115
116
117.macro SAVE_CONTEXT
118    addi sp,sp,-40*4
119    sw x1 , 0 *REGBYTES(sp) /* ra */
120    sw x4 , 1 *REGBYTES(sp) /* tp */
121    sw x5 , 2 *REGBYTES(sp) /* t0 */
122    sw x6 , 3 *REGBYTES(sp) /* t1 */
123    sw x7 , 4 *REGBYTES(sp) /* t2 */
124    sw x10, 5 *REGBYTES(sp) /* a0 */
125    sw x11, 6 *REGBYTES(sp) /* a1 */
126    sw x12, 7 *REGBYTES(sp) /* a2 */
127    sw x13, 8 *REGBYTES(sp) /* a3 */
128    sw x14, 9 *REGBYTES(sp) /* a4 */
129    sw x15, 10*REGBYTES(sp) /* a5 */
130    sw x16, 11*REGBYTES(sp) /* a6 */
131    sw x17, 12*REGBYTES(sp) /* a7 */
132    sw x28, 13*REGBYTES(sp) /* t3 */
133    sw x29, 14*REGBYTES(sp) /* t4 */
134    sw x30, 15*REGBYTES(sp) /* t5 */
135    sw x31, 16*REGBYTES(sp) /* t6 */
136
137    fsw f0, 17*REGBYTES(sp) /* ft0 */
138    fsw f1, 18*REGBYTES(sp) /* ft1 */
139    fsw f2, 19*REGBYTES(sp) /* ft2 */
140    fsw f3, 20*REGBYTES(sp) /* ft3 */
141    fsw f4, 21*REGBYTES(sp) /* ft4 */
142    fsw f5, 22*REGBYTES(sp) /* ft5 */
143    fsw f6, 23*REGBYTES(sp) /* ft6 */
144    fsw f7, 24*REGBYTES(sp) /* ft7 */
145    fsw f10,25*REGBYTES(sp) /* fa0 */
146    fsw f11,26*REGBYTES(sp) /* fa1 */
147    fsw f12,27*REGBYTES(sp) /* fa2 */
148    fsw f13,28*REGBYTES(sp) /* fa3 */
149    fsw f14,29*REGBYTES(sp) /* fa4 */
150    fsw f15,30*REGBYTES(sp) /* fa5 */
151    fsw f16,31*REGBYTES(sp) /* fa6 */
152    fsw f17,32*REGBYTES(sp) /* fa7 */
153    fsw f28,33*REGBYTES(sp) /* ft8 */
154    fsw f29,34*REGBYTES(sp) /* ft9 */
155    fsw f30,35*REGBYTES(sp) /* ft10*/
156    fsw f31,36*REGBYTES(sp) /* ft11*/
157.endm
158
159.macro RESTORE_CONTEXT
160    lw x1 , 0 *REGBYTES(sp) /* ra */
161    lw x4 , 1 *REGBYTES(sp) /* tp */
162    lw x5 , 2 *REGBYTES(sp) /* t0 */
163    lw x6 , 3 *REGBYTES(sp) /* t1 */
164    lw x7 , 4 *REGBYTES(sp) /* t2 */
165    lw x10, 5 *REGBYTES(sp) /* a0 */
166    lw x11, 6 *REGBYTES(sp) /* a1 */
167    lw x12, 7 *REGBYTES(sp) /* a2 */
168    lw x13, 8 *REGBYTES(sp) /* a3 */
169    lw x14, 9 *REGBYTES(sp) /* a4 */
170    lw x15, 10*REGBYTES(sp) /* a5 */
171    lw x16, 11*REGBYTES(sp) /* a6 */
172    lw x17, 12*REGBYTES(sp) /* a7 */
173    lw x28, 13*REGBYTES(sp) /* t3 */
174    lw x29, 14*REGBYTES(sp) /* t4 */
175    lw x30, 15*REGBYTES(sp) /* t5 */
176    lw x31, 16*REGBYTES(sp) /* t6 */
177
178    flw f0, 17*REGBYTES(sp) /* ft0 */
179    flw f1, 18*REGBYTES(sp) /* ft1 */
180    flw f2, 19*REGBYTES(sp) /* ft2 */
181    flw f3, 20*REGBYTES(sp) /* ft3 */
182    flw f4, 21*REGBYTES(sp) /* ft4 */
183    flw f5, 22*REGBYTES(sp) /* ft5 */
184    flw f6, 23*REGBYTES(sp) /* ft6 */
185    flw f7, 24*REGBYTES(sp) /* ft7 */
186    flw f10,25*REGBYTES(sp) /* fa0 */
187    flw f11,26*REGBYTES(sp) /* fa1 */
188    flw f12,27*REGBYTES(sp) /* fa2 */
189    flw f13,28*REGBYTES(sp) /* fa3 */
190    flw f14,29*REGBYTES(sp) /* fa4 */
191    flw f15,30*REGBYTES(sp) /* fa5 */
192    flw f16,31*REGBYTES(sp) /* fa6 */
193    flw f17,32*REGBYTES(sp) /* fa7 */
194    flw f28,33*REGBYTES(sp) /* ft8 */
195    flw f29,34*REGBYTES(sp) /* ft9 */
196    flw f30,35*REGBYTES(sp) /* ft10*/
197    flw f31,36*REGBYTES(sp) /* ft11*/
198    addi sp, sp, 40*REGBYTES
199.endm
200
201.macro SAVE_CSR_CONTEXT
202    csrr t0,mepc
203    csrr t1,mcause
204    sw   t0,37*REGBYTES(sp) /* mepc */
205    sw   t1,38*REGBYTES(sp) /* mcause */
206.endm
207
208.macro RESTORE_CSR_CONTEXT
209    lw   t0,37*REGBYTES(sp) /* mepc */
210    lw   t1,38*REGBYTES(sp) /* mcause */
211    csrw mcause, t1
212    csrw mepc,   t0
213.endm
214
215
216
217    .align 2
218    .global Default_IRQHandler
219    .weak   Default_IRQHandler
220    .type   Default_IRQHandler, %function
221Default_IRQHandler:
222
223    SAVE_CONTEXT
224
225    SAVE_CSR_CONTEXT
226
227    /* get irq */
228    la t0,isr_table
229//    GET_IRQ_NUM    		/* t1: irq num */
230    li t1,0x000E4004		/* t1: irq num */
231    lw t1,0(t1)
232    slli t2, t1, 2
233    add t0, t0, t2
234    lw t2, (t0)
235    sw t1,39*REGBYTES(sp)
236
237
238    ENABLE_MIE
239
240    jalr t2         /* jump to irq */
241
242    DISABLE_MIE
243
244    /* clear pending mask*/
245    lw t1,39*REGBYTES(sp)
246    li t0,0x000E4004
247    sw t1,(t0)
248
249    /* enable pri mie*/
250    li      t0, MSTATUS_PRV1
251    csrs    mstatus, t0
252
253    RESTORE_CSR_CONTEXT
254
255    RESTORE_CONTEXT
256
257    mret
258
259
260/* trap start*/
261.section .text.trap
262/* In CLIC mode, the exeception entry must be 64bytes aligned */
263.align 6
264.global trap
265.weak trap
266.type trap, %function
267trap:
268    /* check for interrupt */
269    addi sp,sp,-4
270    sw   t0,0x0(sp)
271    csrr t0,mcause
272    blt  t0,x0, .Interrupt /* go to Interrupt*/
273    addi sp,sp,4
274
275    /* save regs */
276    addi sp,sp,-22*4
277    sw   x1 , 0 *REGBYTES(sp)
278    sw   x2 , 1 *REGBYTES(sp)
279    sw   x3 , 2 *REGBYTES(sp)
280    sw   x4 , 3 *REGBYTES(sp)
281    sw   x5 , 4 *REGBYTES(sp)
282    sw   x6 , 5 *REGBYTES(sp)
283    sw   x7 , 6 *REGBYTES(sp)
284    sw   x8 , 7 *REGBYTES(sp)
285    sw   x9 , 8 *REGBYTES(sp)
286    sw   x10, 9 *REGBYTES(sp)
287    sw   x11, 10*REGBYTES(sp)
288    sw   x12, 11*REGBYTES(sp)
289    sw   x13, 12*REGBYTES(sp)
290    sw   x14, 13*REGBYTES(sp)
291    sw   x15, 14*REGBYTES(sp)
292    sw   x16, 15*REGBYTES(sp)
293    sw   x17, 16*REGBYTES(sp)
294    sw   x28, 17*REGBYTES(sp)
295    sw   x29, 18*REGBYTES(sp)
296    sw   x30, 19*REGBYTES(sp)
297    sw   x31, 20*REGBYTES(sp)
298
299    csrr a0,  mepc
300    sw   a0,  21*REGBYTES(sp)
301    csrr a0,  mstatus
302    sw   a0,  22*REGBYTES(sp)
303    mv   a0,  sp
304
305
306    jal trap_c
307
308    /*never reatch here */
309    j .
310
311.Interrupt:
312    lw    t0, 0x0(sp)
313    addi  sp, sp, 4
314
315    j    Default_IRQHandler
316/* trap end*/
317
318
319
320	.global trap_c
321	.weak trap_c
322	.type trap_c,%function
323trap_c:
324	j trap_c
325
326
327    .align  6
328    .weak   Default_Handler
329    .global Default_Handler
330    .type   Default_Handler, %function
331Default_Handler:
332    j       Default_Handler
333    .size   Default_Handler, . - Default_Handler
334
335/*    Macro to define default handlers. Default handler
336 *    will be weak symbol and just dead loops. They can be
337 *    overwritten by other handlers */
338    .macro  def_irq_handler handler_name
339    .weak   \handler_name
340    .globl  \handler_name
341    .set    \handler_name, Default_Handler
342    .endm
343
344
345    def_irq_handler USB_IRQHandler
346    def_irq_handler I2C0_IRQHandler
347    def_irq_handler I2C1_IRQHandler
348    def_irq_handler QSPI_IRQHandler
349    def_irq_handler SPI0_IRQHandler
350    def_irq_handler SPI1_IRQHandler
351    def_irq_handler HSPI_IRQHandler
352    def_irq_handler SEC_IRQHandler
353    def_irq_handler UART0_IRQHandler
354    def_irq_handler UART1_IRQHandler
355    def_irq_handler UART2_IRQHandler
356    def_irq_handler UART3_IRQHandler
357    def_irq_handler MEMCP_IRQHandler
358    def_irq_handler SCI0_IRQHandler
359    def_irq_handler SCI1_IRQHandler
360    def_irq_handler MSR_IRQHandler
361    def_irq_handler GPIO_IRQHandler
362    def_irq_handler TMRG0_IRQHandler
363    def_irq_handler TMRG1_IRQHandler
364    def_irq_handler SDIO_IRQHandler
365    def_irq_handler PSARM_IRQHandler
366    def_irq_handler RSA_IRQHandler
367    def_irq_handler SM4_IRQHandler
368    def_irq_handler TRNG_IRQHandler
369    def_irq_handler WDT_IRQHandler
370    def_irq_handler DCMI_IRQHandler
371    def_irq_handler ADC_IRQHandler
372    def_irq_handler RTC_IRQHandler
373    def_irq_handler BIN_IRQHandler
374    def_irq_handler POWER_IRQHandler
375    def_irq_handler SOFTWARE_IRQHandler
376    def_irq_handler IPC_IRQHandler
377    def_irq_handler QR_IRQHandler
378    def_irq_handler ONE_BIN_IRQHandler
379    def_irq_handler SYSTICK_IRQHandler
380    def_irq_handler VBAT_IRQHandler
381    def_irq_handler EXTI0_IRQHandler
382    def_irq_handler EXTI1_IRQHandler
383    def_irq_handler EXTI2_IRQHandler
384    def_irq_handler EXTI3_IRQHandler
385    def_irq_handler EXTI4_IRQHandler
386
387    .align 4
388isr_table:
389    .long USB_IRQHandler
390    .long I2C0_IRQHandler
391    .long I2C1_IRQHandler
392    .long QSPI_IRQHandler
393    .long SPI0_IRQHandler
394    .long SPI1_IRQHandler
395    .long HSPI_IRQHandler
396    .long SEC_IRQHandler
397    .long UART0_IRQHandler
398    .long UART1_IRQHandler
399    .long UART2_IRQHandler
400    .long UART3_IRQHandler
401    .long MEMCP_IRQHandler
402    .long SCI0_IRQHandler
403    .long SCI1_IRQHandler
404    .long MSR_IRQHandler
405    .long GPIO_IRQHandler
406    .long TMRG0_IRQHandler
407    .long TMRG1_IRQHandler
408    .long SDIO_IRQHandler
409    .long PSARM_IRQHandler
410    .long RSA_IRQHandler
411    .long SM4_IRQHandler
412    .long TRNG_IRQHandler
413    .long WDT_IRQHandler
414    .long DCMI_IRQHandler
415    .long ADC_IRQHandler
416    .long RTC_IRQHandler
417    .long BIN_IRQHandler
418    .long POWER_IRQHandler
419    .long SOFTWARE_IRQHandler
420    .long IPC_IRQHandler
421    .long QR_IRQHandler
422    .long ONE_BIN_IRQHandler
423    .long SYSTICK_IRQHandler
424