1 /*
2 * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2021-10-12 Steven Liu first implementation
9 */
10
11 #include <rthw.h>
12 #include <rtthread.h>
13
14 #include "board.h"
15 #include "hal_base.h"
16 #include "hal_bsp.h"
17 #include "drv_cache.h"
18 #include "drv_heap.h"
19
20 #ifdef RT_USING_CRU
21 #include "drv_clock.h"
22 #endif
23
24 #ifdef RT_USING_PIN
25 #include "iomux.h"
26 #endif
27
28 #ifdef RT_USING_UART
29 #include "drv_uart.h"
30 #endif
31
32 #ifdef RT_USING_MODULE
33 #define DATA_EXEC_FLAG 0U
34 #else
35 #define DATA_EXEC_FLAG 1U
36 #endif
37
38 #ifdef RT_USING_CRU
39 rt_weak const struct clk_init clk_inits[] =
40 {
41 INIT_CLK("SCLK_SHRM", SCLK_SHRM, 10 * MHZ),
42 INIT_CLK("PCLK_SHRM", PCLK_SHRM, 10 * MHZ),
43 INIT_CLK("PCLK_ALIVE", PCLK_ALIVE, 10 * MHZ),
44 INIT_CLK("HCLK_ALIVE", HCLK_ALIVE, 10 * MHZ),
45 INIT_CLK("HCLK_M4", HCLK_M4, 10 * MHZ),
46 INIT_CLK("ACLK_LOGIC", ACLK_LOGIC, 10 * MHZ),
47 INIT_CLK("HCLK_LOGIC", HCLK_LOGIC, 10 * MHZ),
48 INIT_CLK("PCLK_LOGIC", PCLK_LOGIC, 10 * MHZ),
49 INIT_CLK("SCLK_SFC_SRC", SCLK_SFC_SRC, 5 * MHZ),
50 INIT_CLK("SCLK_SFC1_SRC", SCLK_SFC1_SRC, 5 * MHZ),
51 INIT_CLK("PLL_GPLL", PLL_GPLL, 1188 * MHZ),
52 INIT_CLK("PLL_CPLL", PLL_CPLL, 1188 * MHZ),
53 INIT_CLK("SCLK_SFC_SRC", SCLK_SFC_SRC, 50 * MHZ),
54 INIT_CLK("HCLK_M4", HCLK_M4, 300 * MHZ),
55 INIT_CLK("ACLK_DSP", ACLK_DSP, 400 * MHZ),
56 INIT_CLK("ACLK_LOGIC", ACLK_LOGIC, 300 * MHZ),
57 INIT_CLK("HCLK_LOGIC", HCLK_LOGIC, 150 * MHZ),
58 INIT_CLK("PCLK_LOGIC", PCLK_LOGIC, 150 * MHZ),
59 INIT_CLK("SCLK_SHRM", SCLK_SHRM, 300 * MHZ),
60 INIT_CLK("PCLK_SHRM", PCLK_SHRM, 100 * MHZ),
61 INIT_CLK("PCLK_ALIVE", PCLK_ALIVE, 100 * MHZ),
62 INIT_CLK("HCLK_ALIVE", HCLK_ALIVE, 100 * MHZ),
63 { /* sentinel */ },
64 };
65
66 rt_weak const struct clk_unused clks_unused[] =
67 {
68 {0, 0, 0x00030003},
69 {0, 5, 0x00ee00ee},
70 {0, 6, 0x048d048d},
71 {0, 7, 0x00110011},
72 {0, 11, 0x40e040e0},
73 {0, 12, 0x90709070},
74 {0, 13, 0xe203e203},
75 {0, 14, 0xa6e1a6e1},
76 { /* sentinel */ },
77 };
78 #endif
79
80 #if defined(RT_USING_UART0)
81 rt_weak const struct uart_board g_uart0_board =
82 {
83 .baud_rate = ROCKCHIP_UART_BAUD_RATE_DEFAULT,
84 .dev_flag = ROCKCHIP_UART_SUPPORT_FLAG_DEFAULT,
85 .bufer_size = RT_SERIAL_RB_BUFSZ,
86 .name = "uart0",
87 };
88 #endif /* RT_USING_UART0 */
89
90 #if defined(RT_USING_UART1)
91 rt_weak const struct uart_board g_uart1_board =
92 {
93 .baud_rate = ROCKCHIP_UART_BAUD_RATE_DEFAULT,
94 .dev_flag = ROCKCHIP_UART_SUPPORT_FLAG_DEFAULT,
95 .bufer_size = RT_SERIAL_RB_BUFSZ,
96 .name = "uart1",
97 };
98 #endif /* RT_USING_UART1 */
99
100 #if defined(RT_USING_UART2)
101 rt_weak const struct uart_board g_uart2_board =
102 {
103 .baud_rate = ROCKCHIP_UART_BAUD_RATE_DEFAULT,
104 .dev_flag = ROCKCHIP_UART_SUPPORT_FLAG_DEFAULT,
105 .bufer_size = RT_SERIAL_RB_BUFSZ,
106 .name = "uart2",
107 };
108 #endif /* RT_USING_UART2 */
109
110 extern void SysTick_Handler(void);
tick_isr(int vector,void * param)111 rt_weak void tick_isr(int vector, void *param)
112 {
113 /* enter interrupt */
114 rt_interrupt_enter();
115
116 HAL_IncTick();
117 rt_tick_increase();
118 #ifdef TICK_TIMER
119 HAL_TIMER_ClrInt(TICK_TIMER);
120 #endif
121
122 /* leave interrupt */
123 rt_interrupt_leave();
124 }
125
BSP_MPU_Init(void)126 void BSP_MPU_Init(void)
127 {
128 static const ARM_MPU_Region_t table[] =
129 {
130 {
131 .RBAR = ARM_MPU_RBAR(0U, 0x04000000U),
132 .RASR = ARM_MPU_RASR(0U, ARM_MPU_AP_FULL, 0U, 0U, 1U, 0U, 0U, ARM_MPU_REGION_SIZE_1MB)
133 },
134 {
135 .RBAR = ARM_MPU_RBAR(1U, 0x18000000U),
136 .RASR = ARM_MPU_RASR(0U, ARM_MPU_AP_FULL, 0U, 0U, 1U, 0U, 0U, ARM_MPU_REGION_SIZE_32MB)
137 },
138 {
139 .RBAR = ARM_MPU_RBAR(2U, 0x20000000U),
140 .RASR = ARM_MPU_RASR(DATA_EXEC_FLAG, ARM_MPU_AP_FULL, 0U, 0U, 1U, 1U, 0U, ARM_MPU_REGION_SIZE_1MB)
141 },
142 {
143 .RBAR = ARM_MPU_RBAR(3U, 0x40000000U),
144 .RASR = ARM_MPU_RASR(1U, ARM_MPU_AP_FULL, 0U, 0U, 0U, 0U, 0U, ARM_MPU_REGION_SIZE_256MB)
145 },
146 {
147 .RBAR = ARM_MPU_RBAR(4U, 0x60000000U),
148 .RASR = ARM_MPU_RASR(1U, ARM_MPU_AP_FULL, 0U, 0U, 1U, 1U, 0U, ARM_MPU_REGION_SIZE_256MB)
149 },
150 };
151
152 ARM_MPU_Load(&(table[0]), 5U);
153
154 #ifdef RT_USING_UNCACHE_HEAP
155 ARM_MPU_Region_t uncache_region;
156
157 uncache_region.RBAR = ARM_MPU_RBAR(5U, RK_UNCACHE_HEAP_START);
158 uncache_region.RASR = ARM_MPU_RASR(1U, ARM_MPU_AP_FULL, 0U, 0U, 0U, 0U, 0U, RT_UNCACHE_HEAP_ORDER);
159 ARM_MPU_SetRegionEx(5, uncache_region.RBAR, uncache_region.RASR);
160 #endif
161
162 ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
163 }
164
165 /**
166 * Initialize the Hardware related stuffs. Called from rtthread_startup()
167 * after interrupt disabled.
168 */
rt_hw_board_init(void)169 void rt_hw_board_init(void)
170 {
171 /* HAL_Init */
172 HAL_Init();
173
174 /* hal bsp init */
175 BSP_Init();
176
177 /* tick init */
178 HAL_SetTickFreq(1000 / RT_TICK_PER_SECOND);
179 rt_hw_interrupt_install(TICK_IRQn, tick_isr, RT_NULL, "tick");
180 rt_hw_interrupt_umask(TICK_IRQn);
181 HAL_NVIC_SetPriority(TICK_IRQn, NVIC_PERIPH_PRIO_LOWEST, NVIC_PERIPH_SUB_PRIO_LOWEST);
182 #ifdef RT_USING_SYSTICK
183 HAL_SYSTICK_CLKSourceConfig(HAL_SYSTICK_CLKSRC_EXT);
184 HAL_SYSTICK_Config((PLL_INPUT_OSC_RATE / RT_TICK_PER_SECOND) - 1);
185 HAL_SYSTICK_Enable();
186 #else
187 HAL_TIMER_Init(TICK_TIMER, TIMER_FREE_RUNNING);
188 HAL_TIMER_SetCount(TICK_TIMER, (PLL_INPUT_OSC_RATE / RT_TICK_PER_SECOND) - 1);
189 HAL_TIMER_Start_IT(TICK_TIMER);
190 #endif
191
192 rt_hw_cpu_cache_init();
193
194 #ifdef RT_USING_PIN
195 #ifdef RK_BSP_TEMP
196 rt_hw_iomux_config();
197 #endif
198 #endif
199
200 #ifdef RT_USING_CRU
201 #ifdef RK_BSP_TEMP
202 clk_init(clk_inits, false);
203
204 /* disable some clks when init, and enabled by device when needed */
205 clk_disable_unused(clks_unused);
206 if (RT_CONSOLE_DEVICE_UART(0))
207 CRU->CRU_CLKGATE_CON[2] = 0x08860886;
208 else if (RT_CONSOLE_DEVICE_UART(1))
209 CRU->CRU_CLKGATE_CON[2] = 0x080d080d;
210 else if (RT_CONSOLE_DEVICE_UART(2))
211 CRU->CRU_CLKGATE_CON[2] = 0x008b008b;
212 else
213 CRU->CRU_CLKGATE_CON[2] = 0x088f088f;
214 #endif
215 #endif
216
217 #ifdef RT_USING_UART
218 rt_hw_usart_init();
219 #endif
220
221 #ifdef RT_USING_CONSOLE
222 rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
223 #endif
224
225 #ifdef RT_USING_HEAP
226 /* initialize memory system */
227 rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
228 #endif
229
230 #ifdef RT_USING_COMPONENTS_INIT
231 rt_components_board_init();
232 #endif
233 }
234
235