1 /**
2 ******************************************************************************
3 * @file HAL_rcc.c
4 * @author IC Applications Department
5 * @version V0.8
6 * @date 2019_08_02
7 * @brief This file provides all the RCC firmware functions.
8 ******************************************************************************
9 * @copy
10 *
11 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
12 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
13 * TIME. AS A RESULT, HOLOCENE SHALL NOT BE HELD LIABLE FOR ANY
14 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
15 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
16 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
17 *
18 * <h2><center>© COPYRIGHT 2016 HOLOCENE</center></h2>
19 */
20
21 /* Includes ------------------------------------------------------------------*/
22 #include "HAL_rcc.h"
23
24 u32 TK499_SYS_CLK = 48000000;
25 u32 TK499_PLL_FACTOR = 0x00004;
26 /** @addtogroup StdPeriph_Driver
27 * @{
28 */
29
30 /** @defgroup RCC
31 * @brief RCC driver modules
32 * @{
33 */
34
35 /** @defgroup RCC_Private_TypesDefinitions
36 * @{
37 */
38
39 /**
40 * @}
41 */
42
43 /** @defgroup RCC_Private_Defines
44 * @{
45 */
46
47 /* ------------ RCC registers bit address in the alias region ----------- */
48 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
49
50 /* --- CR Register ---*/
51
52 /* Alias word address of HSION bit */
53 #define CR_OFFSET (RCC_OFFSET + 0x00)
54 #define HSION_BitNumber 0x00
55 #define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
56
57 /* Alias word address of PLLON bit */
58 #define PLLON_BitNumber 0x18
59 #define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
60
61 /* Alias word address of CSSON bit */
62 #define CSSON_BitNumber 0x13
63 #define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
64
65 /* --- CFGR Register ---*/
66
67 /* Alias word address of USBPRE bit */
68 #define CFGR_OFFSET (RCC_OFFSET + 0x04)
69 #define USBPRE_BitNumber 0x16
70 #define CFGR_USBPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4))
71
72 /* --- BDCR Register ---*/
73
74 /* Alias word address of RTCEN bit */
75 #define BDCR_OFFSET (RCC_OFFSET + 0x20)
76 #define RTCEN_BitNumber 0x0F
77 #define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
78
79 /* Alias word address of BDRST bit */
80 #define BDRST_BitNumber 0x10
81 #define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
82
83 /* --- CSR Register ---*/
84
85 /* Alias word address of LSION bit */
86 #define CSR_OFFSET (RCC_OFFSET + 0x24)
87 #define LSION_BitNumber 0x00
88 #define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
89
90 /* ---------------------- RCC registers bit mask ------------------------ */
91
92 /* CR register bit mask */
93 #define CR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF)
94 #define CR_HSEBYP_Set ((uint32_t)0x00040000)
95 #define CR_HSEON_Reset ((uint32_t)0xFFFEFFFF)
96 #define CR_HSEON_Set ((uint32_t)0x00010000)
97 #define CR_HSITRIM_Mask ((uint32_t)0xFFFFFF07)
98
99 /* CFGR register bit mask */
100 #define CFGR_PLL_Mask ((uint32_t)0xFFC0FFFF)
101 #define CFGR_PLLMull_Mask ((uint32_t)0x003C0000)
102 #define CFGR_PLLSRC_Mask ((uint32_t)0x00400000)
103 #define CFGR_PLLXTPRE_Mask ((uint32_t)0x00020000)
104 #define CFGR_SWS_Mask ((uint32_t)0x0000000C)
105 #define CFGR_SW_Mask ((uint32_t)0xFFFFFFFC)
106 #define CFGR_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F)
107 #define CFGR_HPRE_Set_Mask ((uint32_t)0x000000F0)
108 #define CFGR_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF)
109 #define CFGR_PPRE1_Set_Mask ((uint32_t)0x00000700)
110 #define CFGR_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF)
111 #define CFGR_PPRE2_Set_Mask ((uint32_t)0x00003800)
112 #define CFGR_ADCPRE_Reset_Mask ((uint32_t)0xFFFF3FFF)
113 #define CFGR_ADCPRE_Set_Mask ((uint32_t)0x0000C000)
114
115 /* CSR register bit mask */
116 #define CSR_RMVF_Set ((uint32_t)0x01000000)
117
118 /* RCC Flag Mask */
119 #define FLAG_Mask ((uint8_t)0x1F)
120
121 /* Typical Value of the HSI in Hz */
122 #define HSI_Value ((uint32_t)8000000)
123
124 /* CIR register byte 2 (Bits[15:8]) base address */
125 #define CIR_BYTE2_ADDRESS ((uint32_t)0x40021009)
126
127 /* CIR register byte 3 (Bits[23:16]) base address */
128 #define CIR_BYTE3_ADDRESS ((uint32_t)0x4002100A)
129
130 /* CFGR register byte 4 (Bits[31:24]) base address */
131 #define CFGR_BYTE4_ADDRESS ((uint32_t)0x40021007)
132
133 /* BDCR register base address */
134 #define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET)
135
136 #ifndef HSEStartUp_TimeOut
137 /* Time out for HSE start up */
138 #define HSEStartUp_TimeOut ((uint16_t)0x0500)
139 #endif
140
141 /**
142 * @}
143 */
144
145 /** @defgroup RCC_Private_Macros
146 * @{
147 */
148
149 /**
150 * @}
151 */
152
153 /** @defgroup RCC_Private_Variables
154 * @{
155 */
156
157 static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
158 static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8};
159
160 /**
161 * @}
162 */
163
164 /** @defgroup RCC_Private_FunctionPrototypes
165 * @{
166 */
167
168 /**
169 * @}
170 */
171
172 /** @defgroup RCC_Private_Functions
173 * @{
174 */
SystemClk_HSEInit(uint32_t PLL_DN)175 void SystemClk_HSEInit(uint32_t PLL_DN)
176 {
177 RCC_DeInit();
178 //HSE on
179 //CR寄存器BIT16位（HSEON位）置1，作用是连接外部时钟HSE作为系统时钟
180 RCC_HSEConfig(RCC_HSE_ON);
181
182 while(1)
183 {
184 if(RCC_WaitForHSEStartUp()!=0)
185 {
186 break;
187 }
188 }
189 RCC_PLLCmd(DISABLE);
190 RCC_PLLConfig(RCC_PLLSource_HSE_Div1,PLL_DN);
191 RCC_PLLCmd(ENABLE);
192 RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);//选择外部时钟作为系统时钟
193 }
194 /**
195 * @brief Resets the RCC clock configuration to the default reset state.
196 * @param None
197 * @retval : None
198 */
RCC_DeInit(void)199 void RCC_DeInit(void)
200 {
201 /* Set HSION bit */
202 RCC->CR |= (uint32_t)0x00000001;
203 /* Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], ADCPRE[1:0] and MCO[2:0] bits */
204 RCC->CFGR &= (uint32_t)0xF8FF0000;
205
206 /* Reset HSEON, CSSON and PLLON bits */
207 RCC->CR &= (uint32_t)0xFEF6FFFF;
208 /* Reset HSEBYP bit */
209 RCC->CR &= (uint32_t)0xFFFBFFFF;
210 /* Reset PLLSRC, PLLXTPRE, PLLMUL[3:0] and USBPRE bits */
211 RCC->CFGR &= (uint32_t)0xFF80FFFF;
212 /* Disable all interrupts */
213 RCC->CIR = 0x00000000;
214 }
215
216 /**
217 * @brief Configures the External High Speed oscillator (HSE).
218 * HSE can not be stopped if it is used directly or through the
219 * PLL as system clock.
220 * @param RCC_HSE: specifies the new state of the HSE.
221 * This parameter can be one of the following values:
222 * @arg RCC_HSE_OFF: HSE oscillator OFF
223 * @arg RCC_HSE_ON: HSE oscillator ON
224 * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external
225 * clock
226 * @retval : None
227 */
RCC_HSEConfig(uint32_t RCC_HSE)228 void RCC_HSEConfig(uint32_t RCC_HSE)
229 {
230 /* Check the parameters */
231 assert_param(IS_RCC_HSE(RCC_HSE));
232 /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
233 /* Reset HSEON bit */
234 RCC->CR &= CR_HSEON_Reset;
235 /* Reset HSEBYP bit */
236 RCC->CR &= CR_HSEBYP_Reset;
237 /* Configure HSE (RCC_HSE_OFF is already covered by the code section above) */
238 switch(RCC_HSE)
239 {
240 case RCC_HSE_ON:
241 /* Set HSEON bit */
242 RCC->CR |= CR_HSEON_Set;
243 break;
244
245 case RCC_HSE_Bypass:
246 /* Set HSEBYP and HSEON bits */
247 RCC->CR |= CR_HSEBYP_Set | CR_HSEON_Set;
248 break;
249
250 default:
251 break;
252 }
253 }
254
255 /**
256 * @brief Waits for HSE start-up.
257 * @param None
258 * @retval : An ErrorStatus enumuration value:
259 * - SUCCESS: HSE oscillator is stable and ready to use
260 * - ERROR: HSE oscillator not yet ready
261 */
RCC_WaitForHSEStartUp(void)262 ErrorStatus RCC_WaitForHSEStartUp(void)
263 {
264 __IO uint32_t StartUpCounter = 0;
265 ErrorStatus status = ERROR;
266 FlagStatus HSEStatus = RESET;
267
268 /* Wait till HSE is ready and if Time out is reached exit */
269 do
270 {
271 HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
272 StartUpCounter++;
273 } while((HSEStatus == RESET) && (StartUpCounter != HSEStartUp_TimeOut));
274 if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
275 {
276 status = SUCCESS;
277 }
278 else
279 {
280 status = ERROR;
281 }
282 return (status);
283 }
284
285 /**
286 * @brief Adjusts the Internal High Speed oscillator (HSI) calibration
287 * value.
288 * @param HSICalibrationValue: specifies the calibration trimming value.
289 * This parameter must be a number between 0 and 0x1F.
290 * @retval : None
291 */
RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)292 void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
293 {
294 uint32_t tmpreg = 0;
295 /* Check the parameters */
296 assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue));
297 tmpreg = RCC->CR;
298 /* Clear HSITRIM[4:0] bits */
299 tmpreg &= CR_HSITRIM_Mask;
300 /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
301 tmpreg |= (uint32_t)HSICalibrationValue << 3;
302 /* Store the new value */
303 RCC->CR = tmpreg;
304 }
305
306 /**
307 * @brief Enables or disables the Internal High Speed oscillator (HSI).
308 * HSI can not be stopped if it is used directly or through the
309 * PLL as system clock.
310 * @param NewState: new state of the HSI.
311 * This parameter can be: ENABLE or DISABLE.
312 * @retval : None
313 */
RCC_HSICmd(FunctionalState NewState)314 void RCC_HSICmd(FunctionalState NewState)
315 {
316 /* Check the parameters */
317 assert_param(IS_FUNCTIONAL_STATE(NewState));
318
319 if(NewState==ENABLE)
320 {
321 RCC->CR |= 0x01;
322 }
323 else
324 {
325 RCC->CR &= 0xfffffffe;
326 }
327 }
328 /**
329 * @brief Configures the PLL clock source and DM DN factor.
330 * This function must be used only when the PLL is disabled.
331 * @param RCC_PLLSource: specifies the PLL entry clock source.
332 * This parameter can be one of the following values:
333 * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided
334 * by 2 selected as PLL clock entry
335 * @arg RCC_PLLSource_HSE_Div1: HSE oscillator clock selected
336 * as PLL clock entry
337 * @arg RCC_PLLSource_HSE_Div2: HSE oscillator clock divided
338 * by 2 selected as PLL clock entry
339 * @param RCC_PLLDN: specifies the PLL multiplication factor.
340 * This parameter can be RCC_PLLMul_x where x:[31:26]
341 * @param RCC_PLLDM: specifies the PLL Divsior factor.
342 * This parameter can be RCC_Divsior_x where x:[22:20]
343 * @retval : None
344 */
RCC_PLLDMDNConfig(uint32_t RCC_PLLSource,uint32_t RCC_PLLDN,uint32_t RCC_PLLDP,uint32_t RCC_PLLDM)345 void RCC_PLLDMDNConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLDN,uint32_t RCC_PLLDP, uint32_t RCC_PLLDM)
346 {
347 uint32_t tmpreg0 = 0;
348
349 /* Check the parameters */
350 assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
351 assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));
352
353 if(RCC_PLLSource == 0)
354 {
355 tmpreg0 &= ~(1<<22);
356 }
357 else
358 {
359 TK499_PLL_FACTOR |= 0x10000;
360 tmpreg0 |= (1<<22);
361 }
362
363 RCC_PLLDN &= 0x7f;
364 RCC_PLLDP &= 0x3;
365 RCC_PLLDM &= 0xf;
366 /* Set the PLL configuration bits */
367 tmpreg0 |= (u32)((u32)(RCC_PLLDN<<6))|((u32)(RCC_PLLDP<<4))|((u32)RCC_PLLDM);
368
369 RCC->PLLCFGR = tmpreg0;
370 // RCC->PLLCFGR = 0x4004d1;
371 }
372
373
374 /**
375 * @brief Configures the PLL clock source and multiplication factor.
376 * This function must be used only when the PLL is disabled.
377 * @param RCC_PLLSource: specifies the PLL entry clock source.
378 * This parameter can be one of the following values:
379 * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided
380 * by 2 selected as PLL clock entry
381 * @arg RCC_PLLSource_HSE_Div1: HSE oscillator clock selected
382 * as PLL clock entry
383 * @arg RCC_PLLSource_HSE_Div2: HSE oscillator clock divided
384 * by 2 selected as PLL clock entry
385 * @param RCC_PLLMul: specifies the PLL multiplication factor.
386 * This parameter can be RCC_PLLMul_x where x:[31:26][22:20]
387 * @retval : None
388 */
RCC_PLLConfig(uint32_t RCC_PLLSource,uint32_t RCC_PLLMul)389 void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul)
390 {
391 uint32_t tmpreg = 0;
392 /* Check the parameters */
393 assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
394 assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));
395 tmpreg = RCC->CFGR;
396 /* Clear PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
397 tmpreg &= CFGR_PLL_Mask;
398 /* Set the PLL configuration bits */
399 tmpreg |= RCC_PLLSource;
400 /* Store the new value */
401 RCC->CFGR = tmpreg;
402
403 if(RCC_PLLMul==RCC_PLLMul_2)
404 {
405 TK499_PLL_FACTOR = 2;
406 RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000001, 0x00000000,0x00000000); //Frclk*8/4
407 }
408 if(RCC_PLLMul==RCC_PLLMul_3)
409 {
410 TK499_PLL_FACTOR = 3;
411 RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000002, 0x00000000,0x00000000);//Frclk*6/2
412 }
413 if(RCC_PLLMul==RCC_PLLMul_4)
414 {
415 TK499_PLL_FACTOR = 4;
416 RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000003, 0x00000000,0x00000000);//Frclk*8/2
417 }
418 if(RCC_PLLMul==RCC_PLLMul_5)
419 {
420 TK499_PLL_FACTOR = 5;
421 RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000013, 0x00000001,0x00000001);//Frclk*10/2
422 }
423 if(RCC_PLLMul==RCC_PLLMul_6)
424 {
425 TK499_PLL_FACTOR = 6;
426 RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000005, 0x00000000,0x00000000);//Frclk*12/2
427 }
428 if(RCC_PLLMul==RCC_PLLMul_7)
429 {
430 TK499_PLL_FACTOR = 7;
431 RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000006, 0x00000000,0x00000000);//Frclk*14/2
432 }
433 if(RCC_PLLMul==RCC_PLLMul_8)
434 {
435 TK499_PLL_FACTOR = 8;
436 RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000007, 0x00000000,0x00000000);//Frclk*16/2
437 }
438 if(RCC_PLLMul==RCC_PLLMul_9)
439 {
440 TK499_PLL_FACTOR = 9;
441 RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000008, 0x00000000,0x00000000);//Frclk*18/2
442 }
443 if(RCC_PLLMul==RCC_PLLMul_10)
444 {
445 TK499_PLL_FACTOR = 10;
446 RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000009, 0x00000000,0x00000000);//Frclk*20/2
447 }
448 if(RCC_PLLMul==RCC_PLLMul_11)
449 {
450 TK499_PLL_FACTOR = 11;
451 RCC_PLLDMDNConfig(RCC_PLLSource, 0x0000000a, 0x00000000,0x00000000);//Frclk*22/2
452 }
453 if(RCC_PLLMul==RCC_PLLMul_12)
454 {
455 TK499_PLL_FACTOR = 12;
456 RCC_PLLDMDNConfig(RCC_PLLSource, 0x0000000b, 0x00000000,0x00000000);//Frclk*24/2
457 }
458 if(RCC_PLLMul==RCC_PLLMul_13)
459 {
460 TK499_PLL_FACTOR = 13;
461 RCC_PLLDMDNConfig(RCC_PLLSource, 0x0000000c, 0x00000000,0x00000000);//Frclk*26/2
462 }
463 if(RCC_PLLMul==RCC_PLLMul_14)
464 {
465 TK499_PLL_FACTOR = 14;
466 RCC_PLLDMDNConfig(RCC_PLLSource, 0x0000000d, 0x00000000,0x00000000);//Frclk*28/2
467 }
468 if(RCC_PLLMul==RCC_PLLMul_15)
469 {
470 TK499_PLL_FACTOR = 15;
471 RCC_PLLDMDNConfig(RCC_PLLSource, 0x0000000e, 0x00000000,0x00000000);//Frclk*30/2
472 }
473 if(RCC_PLLMul==RCC_PLLMul_16)
474 {
475 TK499_PLL_FACTOR = 16;
476 RCC_PLLDMDNConfig(RCC_PLLSource, 0x0000000f, 0x00000000,0x00000000);//Frclk*32/2
477 }
478 if(RCC_PLLMul==RCC_PLLMul_17)
479 {
480 TK499_PLL_FACTOR = 17;
481 RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000010, 0x00000000,0x00000000);//Frclk*32/2
482 }
483 if(RCC_PLLMul==RCC_PLLMul_18)
484 {
485 TK499_PLL_FACTOR = 18;
486 RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000011, 0x00000000,0x00000000);//Frclk*32/2
487 }
488 if(RCC_PLLMul==RCC_PLLMul_19)
489 {
490 TK499_PLL_FACTOR = 19;
491 RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000012, 0x00000000,0x00000000);//Frclk*32/2
492 }
493 if(RCC_PLLMul==RCC_PLLMul_20)
494 {
495 TK499_PLL_FACTOR = 20;
496 RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000013, 0x00000000,0x00000000);//Frclk*32/2
497 }
498 if(RCC_PLLMul==RCC_PLLMul_21)
499 {
500 TK499_PLL_FACTOR = 21;
501 RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000014, 0x00000000,0x00000000);//Frclk*32/2
502 }
503 if(RCC_PLLMul==RCC_PLLMul_22)
504 {
505 TK499_PLL_FACTOR = 22;
506 RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000015, 0x00000000,0x00000000);//Frclk*32/2
507 }
508 if(RCC_PLLMul==RCC_PLLMul_23)
509 {
510 TK499_PLL_FACTOR = 23;
511 RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000016, 0x00000000,0x00000000);//Frclk*32/2
512 }
513 if(RCC_PLLMul==RCC_PLLMul_24)
514 {
515 TK499_PLL_FACTOR = 24;
516 RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000017, 0x00000000,0x00000000);//Frclk*32/2
517 }
518 if(RCC_PLLMul==RCC_PLLMul_25)
519 {
520 TK499_PLL_FACTOR = 25;
521 RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000018, 0x00000000,0x00000000);//Frclk*32/2
522 }
523 if(RCC_PLLMul==RCC_PLLMul_26)
524 {
525 TK499_PLL_FACTOR = 26;
526 RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000019, 0x00000000,0x00000000);//Frclk*32/2
527 }
528 if(RCC_PLLMul==RCC_PLLMul_27)
529 {
530 TK499_PLL_FACTOR = 27;
531 RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000020, 0x00000000,0x00000000);//Frclk*32/2
532 }
533 if(RCC_PLLMul==RCC_PLLMul_28)
534 {
535 TK499_PLL_FACTOR = 28;
536 RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000021, 0x00000000,0x00000000);//Frclk*32/2
537 }
538 }
539
540
541 /**
542 * @brief Enables or disables the PLL.
543 * The PLL can not be disabled if it is used as system clock.
544 * @param NewState: new state of the PLL.
545 * This parameter can be: ENABLE or DISABLE.
546 * @retval : None
547 */
RCC_PLLCmd(FunctionalState NewState)548 void RCC_PLLCmd(FunctionalState NewState)
549 {
550 /* Check the parameters */
551 assert_param(IS_FUNCTIONAL_STATE(NewState));
552
553 if (NewState != DISABLE)
554 {
555 RCC->CR |= 0x01000000;
556 }
557 else
558 {
559 RCC->CR &= 0xfeffffff;
560 }
561 }
562
563 /**
564 * @brief Configures the system clock (SYSCLK).
565 * @param RCC_SYSCLKSource: specifies the clock source used as system
566 * clock. This parameter can be one of the following values:
567 * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock
568 * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock
569 * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock
570 * @retval : None
571 */
RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)572 void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
573 {
574 uint32_t tmpreg = 0;
575 /* Check the parameters */
576 assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
577 tmpreg = RCC->CFGR;
578 /* Clear SW[1:0] bits */
579 tmpreg &= CFGR_SW_Mask;
580 /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
581 tmpreg |= RCC_SYSCLKSource;
582 /* Store the new value */
583 RCC->CFGR = tmpreg;
584 if(RCC_SYSCLKSource == RCC_SYSCLKSource_PLLCLK)
585 {
586 if(TK499_PLL_FACTOR&0x10000)//hse as pll src
587 {
588 TK499_SYS_CLK = (TK499_PLL_FACTOR&0xff)*HSE_VALUE;
589 }
590 else
591 {
592 TK499_SYS_CLK = (TK499_PLL_FACTOR&0xff)*HSI_Value_Pll_ON;
593 }
594 }
595 else if(RCC_SYSCLKSource == RCC_SYSCLKSource_HSE)
596 {
597 TK499_SYS_CLK = HSE_VALUE;
598 }
599 else
600 {
601 TK499_SYS_CLK = HSI_Value_Pll_OFF;
602 }
603 }
604
605 /**
606 * @brief Returns the clock source used as system clock.
607 * @param None
608 * @retval : The clock source used as system clock. The returned value can
609 * be one of the following:
610 * - 0x00: HSI/6 used as system clock
611 * - 0x04: HSE used as system clock
612 * - 0x08: PLL used as system clock
613 */
RCC_GetSYSCLKSource(void)614 uint8_t RCC_GetSYSCLKSource(void)
615 {
616 return ((uint8_t)(RCC->CFGR & CFGR_SWS_Mask));
617 }
618
619 /**
620 * @brief Configures the AHB clock (HCLK).
621 * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from
622 * the system clock (SYSCLK).
623 * This parameter can be one of the following values:
624 * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK
625 * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
626 * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
627 * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
628 * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
629 * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
630 * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
631 * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
632 * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
633 * @retval : None
634 */
RCC_HCLKConfig(uint32_t RCC_SYSCLK)635 void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
636 {
637 uint32_t tmpreg = 0;
638 /* Check the parameters */
639 assert_param(IS_RCC_HCLK(RCC_SYSCLK));
640 tmpreg = RCC->CFGR;
641 /* Clear HPRE[3:0] bits */
642 tmpreg &= CFGR_HPRE_Reset_Mask;
643 /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
644 tmpreg |= RCC_SYSCLK;
645 /* Store the new value */
646 RCC->CFGR = tmpreg;
647 }
648
649 /**
650 * @brief Configures the Low Speed APB clock (PCLK1).
651 * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from
652 * the AHB clock (HCLK).
653 * This parameter can be one of the following values:
654 * @arg RCC_HCLK_Div1: APB1 clock = HCLK
655 * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2
656 * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4
657 * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8
658 * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16
659 * @retval : None
660 */
RCC_PCLK1Config(uint32_t RCC_HCLK)661 void RCC_PCLK1Config(uint32_t RCC_HCLK)
662 {
663 uint32_t tmpreg = 0;
664 /* Check the parameters */
665 assert_param(IS_RCC_PCLK(RCC_HCLK));
666 tmpreg = RCC->CFGR;
667 /* Clear PPRE1[2:0] bits */
668 tmpreg &= CFGR_PPRE1_Reset_Mask;
669 /* Set PPRE1[2:0] bits according to RCC_HCLK value */
670 tmpreg |= RCC_HCLK;
671 /* Store the new value */
672 RCC->CFGR = tmpreg;
673 }
674
675 /**
676 * @brief Configures the High Speed APB clock (PCLK2).
677 * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from
678 * the AHB clock (HCLK).
679 * This parameter can be one of the following values:
680 * @arg RCC_HCLK_Div1: APB2 clock = HCLK
681 * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2
682 * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4
683 * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8
684 * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16
685 * @retval : None
686 */
RCC_PCLK2Config(uint32_t RCC_HCLK)687 void RCC_PCLK2Config(uint32_t RCC_HCLK)
688 {
689 uint32_t tmpreg = 0;
690 /* Check the parameters */
691 assert_param(IS_RCC_PCLK(RCC_HCLK));
692 tmpreg = RCC->CFGR;
693 /* Clear PPRE2[2:0] bits */
694 tmpreg &= CFGR_PPRE2_Reset_Mask;
695 /* Set PPRE2[2:0] bits according to RCC_HCLK value */
696 tmpreg |= RCC_HCLK << 3;
697 /* Store the new value */
698 RCC->CFGR = tmpreg;
699 }
700
701 /**
702 * @brief Enables or disables the specified RCC interrupts.
703 * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.
704 * This parameter can be any combination of the following values:
705 * @arg RCC_IT_LSIRDY: LSI ready interrupt
706 * @arg RCC_IT_LSERDY: LSE ready interrupt
707 * @arg RCC_IT_HSIRDY: HSI ready interrupt
708 * @arg RCC_IT_HSERDY: HSE ready interrupt
709 * @arg RCC_IT_PLLRDY: PLL ready interrupt
710 * @param NewState: new state of the specified RCC interrupts.
711 * This parameter can be: ENABLE or DISABLE.
712 * @retval : None
713 */
RCC_ITConfig(uint8_t RCC_IT,FunctionalState NewState)714 void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
715 {
716 /* Check the parameters */
717 assert_param(IS_RCC_IT(RCC_IT));
718 assert_param(IS_FUNCTIONAL_STATE(NewState));
719 if (NewState != DISABLE)
720 {
721 /* Perform Byte access to RCC_CIR[12:8] bits to enable the selected interrupts */
722
723 RCC->CIR |= ((uint32_t)RCC_IT)<<8;
724 }
725 else
726 {
727 /* Perform Byte access to RCC_CIR[12:8] bits to disable the selected interrupts */
728
729 RCC->CIR &= ~((uint32_t)RCC_IT<<8);
730 }
731 }
732
733 /**
734 * @brief Configures the USB clock (USBCLK).
735 * @param RCC_USBCLKSource: specifies the USB clock source. This clock is
736 * derived from the PLL output.
737 * This parameter can be one of the following values:
738 * @arg RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5 selected as USB
739 * clock source
740 * @arg RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source
741 * @retval : None
742 */
RCC_USBCLKConfig(uint32_t RCC_USBCLKSource)743 void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource)
744 {
745 /* Check the parameters */
746 assert_param(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource));
747 RCC->CFGR |= RCC_USBCLKSource;
748 }
749
750 /**
751 * @brief Configures the ADC clock (ADCCLK).
752 * @param RCC_PCLK2: defines the ADC clock divider. This clock is derived from
753 * the APB2 clock (PCLK2).
754 * This parameter can be one of the following values:
755 * @arg RCC_PCLK2_Div2: ADC clock = PCLK2/2
756 * @arg RCC_PCLK2_Div4: ADC clock = PCLK2/4
757 * @arg RCC_PCLK2_Div6: ADC clock = PCLK2/6
758 * @arg RCC_PCLK2_Div8: ADC clock = PCLK2/8
759 * @retval : None
760 */
RCC_ADCCLKConfig(uint32_t RCC_PCLK2)761 void RCC_ADCCLKConfig(uint32_t RCC_PCLK2)
762 {
763 uint32_t tmpreg = 0;
764 /* Check the parameters */
765 assert_param(IS_RCC_ADCCLK(RCC_PCLK2));
766 tmpreg = RCC->CFGR;
767 /* Clear ADCPRE[1:0] bits */
768 tmpreg &= CFGR_ADCPRE_Reset_Mask;
769 /* Set ADCPRE[1:0] bits according to RCC_PCLK2 value */
770 tmpreg |= RCC_PCLK2;
771 /* Store the new value */
772 RCC->CFGR = tmpreg;
773 }
774
775 /**
776 * @brief Configures the External Low Speed oscillator (LSE).
777 * @param RCC_LSE: specifies the new state of the LSE.
778 * This parameter can be one of the following values:
779 * @arg RCC_LSE_OFF: LSE oscillator OFF
780 * @arg RCC_LSE_ON: LSE oscillator ON
781 * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external
782 * clock
783 * @retval : None
784 */
RCC_LSEConfig(uint8_t RCC_LSE)785 void RCC_LSEConfig(uint8_t RCC_LSE)
786 {
787 /* Check the parameters */
788 assert_param(IS_RCC_LSE(RCC_LSE));
789 /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
790 /* Reset LSEON bit */
791 RCC->BDCR &= ~((uint32_t)RCC_LSE_ON);
792 /* Reset LSEBYP bit */
793 RCC->BDCR &= ~((uint32_t)RCC_LSE_ON);
794 /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */
795 switch(RCC_LSE)
796 {
797 case RCC_LSE_ON:
798 /* Set LSEON bit */
799 RCC->BDCR |= RCC_LSE_ON;
800 break;
801
802 case RCC_LSE_Bypass:
803 /* Set LSEBYP and LSEON bits */
804 RCC->BDCR |= RCC_LSE_Bypass | RCC_LSE_ON;
805 break;
806
807 default:
808 break;
809 }
810 }
811
812 /**
813 * @brief Enables or disables the Internal Low Speed oscillator (LSI).
814 * LSI can not be disabled if the IWDG is running.
815 * @param NewState: new state of the LSI.
816 * This parameter can be: ENABLE or DISABLE.
817 * @retval : None
818 */
RCC_LSICmd(FunctionalState NewState)819 void RCC_LSICmd(FunctionalState NewState)
820 {
821 /* Check the parameters */
822 assert_param(IS_FUNCTIONAL_STATE(NewState));
823
824 if (NewState != DISABLE)
825 {
826 RCC->CSR |= 0x00000001;
827 }
828 else
829 {
830 RCC->CSR &= 0xfffffffe;
831 }
832 }
833
834 /**
835 * @brief Configures the RTC clock (RTCCLK).
836 * Once the RTC clock is selected it can't be changed unless the
837 * Backup domain is reset.
838 * @param RCC_RTCCLKSource: specifies the RTC clock source.
839 * This parameter can be one of the following values:
840 * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock
841 * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock
842 * @arg RCC_RTCCLKSource_HSE_Div128: HSE clock divided by 128
843 * selected as RTC clock
844 * @retval : None
845 */
RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)846 void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
847 {
848 /* Check the parameters */
849 assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
850 /* Select the RTC clock source */
851 RCC->BDCR |= RCC_RTCCLKSource;
852 }
853
854 /**
855 * @brief Enables or disables the RTC clock.
856 * This function must be used only after the RTC clock was
857 * selected using the RCC_RTCCLKConfig function.
858 * @param NewState: new state of the RTC clock.
859 * This parameter can be: ENABLE or DISABLE.
860 * @retval : None
861 */
RCC_RTCCLKCmd(FunctionalState NewState)862 void RCC_RTCCLKCmd(FunctionalState NewState)
863 {
864 /* Check the parameters */
865 assert_param(IS_FUNCTIONAL_STATE(NewState));
866
867 if (NewState != DISABLE)
868 {
869 RCC->BDCR |= 0x00008000;
870 }
871 else
872 {
873 RCC->BDCR &= 0xffff7fff;
874 }
875 }
getSystemClock(u32 * sysclk)876 void getSystemClock(u32 *sysclk)
877 {
878 u32 tempreg0 = RCC->CFGR;
879 u32 tempreg1;
880 u8 dn,dp,dm;
881 if((tempreg0 & 0xC) == 0x00)
882 {
883 *sysclk = 8000000;
884 }
885 else if((tempreg0 & 0xC) ==0x04)
886 {
887 *sysclk = 12000000;
888 }
889 else
890 {
891 tempreg1 = RCC->PLLCFGR;
892 dn = (tempreg1 >> 6) & 0x7F;
893 dn ++;
894 dp = (tempreg1 >> 4) & 0x3;
895 if(dp == 0)
896 dp = 1;
897 else if(dp == 1)
898 dp = 2;
899 else if(dp == 2)
900 dp = 4;
901 else if(dp == 3)
902 dp = 8;
903 dm = (tempreg1 >> 0) & 0xF;
904 dm++;
905 if(tempreg1 & (1 << 22))
906 {
907 if(tempreg0 & (1 << 16))
908 *sysclk = 6000000* dn/( dm * dp);
909 else
910 *sysclk = 12000000* dn/( dm * dp);
911 }
912 else
913 {
914 *sysclk = 12000000* dn/( dm * dp);
915 }
916 }
917 }
918
919 /**
920 * @brief Returns the frequencies of different on chip clocks.
921 * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which
922 * will hold the clocks frequencies.
923 * @retval : None
924 */
RCC_GetClocksFreq(RCC_ClocksTypeDef * RCC_Clocks)925 void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
926 {
927 uint32_t tmp = 0, presc = 0;
928 /* Get SYSCLK source -------------------------------------------------------*/
929 tmp = RCC->CFGR & CFGR_SWS_Mask;
930 switch (tmp)
931 {
932 case 0x00: /* HSI used as system clock */
933 RCC_Clocks->SYSCLK_Frequency = HSI_Value_Pll_OFF;
934 break;
935 case 0x04: /* HSE used as system clock */
936 RCC_Clocks->SYSCLK_Frequency = HSE_Value;
937 break;
938 case 0x08: /* PLL used as system clock */
939 /* Get PLL clock source and multiplication factor ----------------------*/
940
941 RCC_Clocks->SYSCLK_Frequency = TK499_SYS_CLK;
942 getSystemClock( & (RCC_Clocks->SYSCLK_Frequency ));
943 break;
944 default:
945 RCC_Clocks->SYSCLK_Frequency = HSI_Value_Pll_OFF;
946 break;
947 }
948 /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/
949 /* Get HCLK prescaler */
950 tmp = RCC->CFGR & CFGR_HPRE_Set_Mask;
951 tmp = tmp >> 4;
952 presc = APBAHBPrescTable[tmp];
953 /* HCLK clock frequency */
954 RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
955 /* Get PCLK1 prescaler */
956 tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask;
957 tmp = tmp >> 8;
958 presc = APBAHBPrescTable[tmp];
959 /* PCLK1 clock frequency */
960 RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
961 /* Get PCLK2 prescaler */
962 tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask;
963 tmp = tmp >> 11;
964 presc = APBAHBPrescTable[tmp];
965 /* PCLK2 clock frequency */
966 RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
967 /* Get ADCCLK prescaler */
968 tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask;
969 tmp = tmp >> 14;
970 presc = ADCPrescTable[tmp];
971 /* ADCCLK clock frequency */
972 RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc;
973 }
974
975 /**
976 * @brief Enables or disables the AHB peripheral clock.
977 * @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.
978 * This parameter can be any combination of the following values:
979 * @arg RCC_AHBPeriph_DMA1
980 * @arg RCC_AHBPeriph_DMA2
981 * @arg RCC_AHBPeriph_SRAM
982 * @arg RCC_AHBPeriph_FLITF
983 * @arg RCC_AHBPeriph_CRC
984 * @arg RCC_AHBPeriph_FSMC
985 * @arg RCC_AHBPeriph_SDIO
986 * SRAM and FLITF clock can be disabled only during sleep mode.
987 * @param NewState: new state of the specified peripheral clock.
988 * This parameter can be: ENABLE or DISABLE.
989 * @retval : None
990 */
RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph,FunctionalState NewState)991 void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
992 {
993 /* Check the parameters */
994 assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
995 assert_param(IS_FUNCTIONAL_STATE(NewState));
996 if (NewState != DISABLE)
997 {
998 RCC->AHB1ENR |= RCC_AHBPeriph;
999 }
1000 else
1001 {
1002 RCC->AHB1ENR &= ~RCC_AHBPeriph;
1003 }
1004 }
1005
1006 /**
1007 * @brief Enables or disables the High Speed APB (APB2) peripheral clock.
1008 * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its
1009 * clock.
1010 * This parameter can be any combination of the following values:
1011 * @arg RCC_APB2Periph_SYSCFG, RCC_AHBPeriph_GPIOA, RCC_AHBPeriph_GPIOB,
1012 * RCC_AHBPeriph_GPIOC, RCC_AHBPeriph_GPIOD, RCC_APB2Periph_ADC1,
1013 * RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1,
1014 * RCC_APB2Periph_TIM8, RCC_APB2Periph_UART1,
1015 * RCC_APB2Periph_ALL
1016 * @param NewState: new state of the specified peripheral clock.
1017 * This parameter can be: ENABLE or DISABLE.
1018 * @retval : None
1019 */
RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph,FunctionalState NewState)1020 void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
1021 {
1022 /* Check the parameters */
1023 assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
1024 assert_param(IS_FUNCTIONAL_STATE(NewState));
1025 if (NewState != DISABLE)
1026 {
1027 RCC->APB2ENR |= RCC_APB2Periph;
1028 }
1029 else
1030 {
1031 RCC->APB2ENR &= ~RCC_APB2Periph;
1032 }
1033 }
1034
1035
RCC_BackupResetCmd(FunctionalState NewState)1036 void RCC_BackupResetCmd(FunctionalState NewState)
1037 {
1038 /* Check the parameters */
1039 assert_param(IS_FUNCTIONAL_STATE(NewState));
1040 *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState;
1041 }
1042
1043 /**
1044 * @brief Enables or disables the Low Speed APB (APB1) peripheral clock.
1045 * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its
1046 * clock.
1047 * This parameter can be any combination of the following values:
1048 * @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4,
1049 * RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7,
1050 * RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3,
1051 * RCC_APB1Periph_UART2, RCC_APB1Periph_UART3, RCC_APB1Periph_UART4,
1052 * RCC_APB1Periph_UART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2,
1053 * RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP,
1054 * RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_ALL
1055 * @param NewState: new state of the specified peripheral clock.
1056 * This parameter can be: ENABLE or DISABLE.
1057 * @retval : None
1058 */
RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph,FunctionalState NewState)1059 void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
1060 {
1061 /* Check the parameters */
1062 assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
1063 assert_param(IS_FUNCTIONAL_STATE(NewState));
1064 if (NewState != DISABLE)
1065 {
1066 RCC->APB1ENR |= RCC_APB1Periph;
1067 }
1068 else
1069 {
1070 RCC->APB1ENR &= ~RCC_APB1Periph;
1071 }
1072 }
1073
1074 /**
1075 * @brief Forces or releases High Speed APB (APB2) peripheral reset.
1076 * @param RCC_APB2Periph: specifies the APB2 peripheral to reset.
1077 * This parameter can be any combination of the following values:
1078 * @arg RCC_APB2Periph_AFIO, RCC_AHBPeriph_GPIOA, RCC_AHBPeriph_GPIOB,
1079 * RCC_AHBPeriph_GPIOC, RCC_AHBPeriph_GPIOD, RCC_APB2Periph_ADC1,
1080 * RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1,
1081 * RCC_APB2Periph_TIM8, RCC_APB2Periph_UART1, RCC_APB2Periph_ADC3,
1082 * RCC_APB2Periph_ALL
1083 * @param NewState: new state of the specified peripheral reset.
1084 * This parameter can be: ENABLE or DISABLE.
1085 * @retval : None
1086 */
RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph,FunctionalState NewState)1087 void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
1088 {
1089 /* Check the parameters */
1090 assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
1091 assert_param(IS_FUNCTIONAL_STATE(NewState));
1092 if (NewState != DISABLE)
1093 {
1094 RCC->APB2RSTR |= RCC_APB2Periph;
1095 }
1096 else
1097 {
1098 RCC->APB2RSTR &= ~RCC_APB2Periph;
1099 }
1100 }
1101
1102 /**
1103 * @brief Forces or releases Low Speed APB (APB1) peripheral reset.
1104 * @param RCC_APB1Periph: specifies the APB1 peripheral to reset.
1105 * This parameter can be any combination of the following values:
1106 * @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4,
1107 * RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7,
1108 * RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3,
1109 * RCC_APB1Periph_UART2, RCC_APB1Periph_UART3, RCC_APB1Periph_UART4,
1110 * RCC_APB1Periph_UART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2,
1111 * RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP,
1112 * RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_ALL
1113 * @param NewState: new state of the specified peripheral clock.
1114 * This parameter can be: ENABLE or DISABLE.
1115 * @retval : None
1116 */
RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph,FunctionalState NewState)1117 void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
1118 {
1119 /* Check the parameters */
1120 assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
1121 assert_param(IS_FUNCTIONAL_STATE(NewState));
1122 if (NewState != DISABLE)
1123 {
1124 RCC->APB1RSTR |= RCC_APB1Periph;
1125 }
1126 else
1127 {
1128 RCC->APB1RSTR &= ~RCC_APB1Periph;
1129 }
1130 }
1131
1132
1133
1134 /**
1135 * @brief Enables or disables the Clock Security System.
1136 * @param NewState: new state of the Clock Security System..
1137 * This parameter can be: ENABLE or DISABLE.
1138 * @retval : None
1139 */
RCC_ClockSecuritySystemCmd(FunctionalState NewState)1140 void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
1141 {
1142 /* Check the parameters */
1143 assert_param(IS_FUNCTIONAL_STATE(NewState));
1144 // *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState;
1145 if(NewState==ENABLE)
1146 {
1147 RCC->CR |= (uint32_t)0x00080000;
1148 }
1149 else
1150 {
1151 RCC->CR &= (uint32_t)0xfff7ffff;
1152 }
1153 }
1154
1155 /**
1156 * @brief Selects the clock source to output on MCO pin.
1157 * @param RCC_MCO: specifies the clock source to output.
1158 * This parameter can be one of the following values:
1159 * @arg RCC_MCO_NoClock: No clock selected
1160 * @arg RCC_MCO_SYSCLK: System clock selected
1161 * @arg RCC_MCO_HSI: HSI oscillator clock selected
1162 * @arg RCC_MCO_HSE: HSE oscillator clock selected
1163 * @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected
1164 * @retval : None
1165 */
RCC_MCOConfig(uint8_t RCC_MCO)1166 void RCC_MCOConfig(uint8_t RCC_MCO)
1167 {
1168 /* Check the parameters */
1169 assert_param(IS_RCC_MCO(RCC_MCO));
1170 /* Perform Byte access to MCO[2:0] bits to select the MCO source */
1171
1172 RCC->CFGR |= (RCC_MCO<<24);
1173 }
1174
1175 /**
1176 * @brief Checks whether the specified RCC flag is set or not.
1177 * @param RCC_FLAG: specifies the flag to check.
1178 * This parameter can be one of the following values:
1179 * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
1180 * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
1181 * @arg RCC_FLAG_PLLRDY: PLL clock ready
1182 * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
1183 * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
1184 * @arg RCC_FLAG_PINRST: Pin reset
1185 * @arg RCC_FLAG_PORRST: POR/PDR reset
1186 * @arg RCC_FLAG_SFTRST: Software reset
1187 * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
1188 * @arg RCC_FLAG_WWDGRST: Window Watchdog reset
1189 * @arg RCC_FLAG_LPWRRST: Low Power reset
1190 * @retval : The new state of RCC_FLAG (SET or RESET).
1191 */
RCC_GetFlagStatus(uint8_t RCC_FLAG)1192 FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
1193 {
1194 uint32_t tmp = 0;
1195 uint32_t statusreg = 0;
1196 FlagStatus bitstatus = RESET;
1197 /* Check the parameters */
1198 assert_param(IS_RCC_FLAG(RCC_FLAG));
1199 /* Get the RCC register index */
1200 tmp = RCC_FLAG >> 5;
1201 if (tmp == 1) /* The flag to check is in CR register */
1202 {
1203 statusreg = RCC->CR;
1204 }
1205 else if (tmp == 2) /* The flag to check is in BDCR register */
1206 {
1207 statusreg = RCC->BDCR;
1208 }
1209 else /* The flag to check is in CSR register */
1210 {
1211 statusreg = RCC->CSR;
1212 }
1213 /* Get the flag position */
1214 tmp = RCC_FLAG & FLAG_Mask;
1215 if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
1216 {
1217 bitstatus = SET;
1218 }
1219 else
1220 {
1221 bitstatus = RESET;
1222 }
1223 /* Return the flag status */
1224 return bitstatus;
1225 }
1226
1227 /**
1228 * @brief Clears the RCC reset flags.
1229 * The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST,
1230 * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST,
1231 * RCC_FLAG_LPWRRST
1232 * @param None
1233 * @retval : None
1234 */
RCC_ClearFlag(void)1235 void RCC_ClearFlag(void)
1236 {
1237 /* Set RMVF bit to clear the reset flags */
1238 RCC->CSR |= CSR_RMVF_Set;
1239 }
1240
1241 /**
1242 * @brief Checks whether the specified RCC interrupt has occurred or not.
1243 * @param RCC_IT: specifies the RCC interrupt source to check.
1244 * This parameter can be one of the following values:
1245 * @arg RCC_IT_LSIRDY: LSI ready interrupt
1246 * @arg RCC_IT_LSERDY: LSE ready interrupt
1247 * @arg RCC_IT_HSIRDY: HSI ready interrupt
1248 * @arg RCC_IT_HSERDY: HSE ready interrupt
1249 * @arg RCC_IT_PLLRDY: PLL ready interrupt
1250 * @arg RCC_IT_CSS: Clock Security System interrupt
1251 * @retval : The new state of RCC_IT (SET or RESET).
1252 */
RCC_GetITStatus(uint8_t RCC_IT)1253 ITStatus RCC_GetITStatus(uint8_t RCC_IT)
1254 {
1255 ITStatus bitstatus = RESET;
1256 /* Check the parameters */
1257 assert_param(IS_RCC_GET_IT(RCC_IT));
1258 /* Check the status of the specified RCC interrupt */
1259 if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)
1260 {
1261 bitstatus = SET;
1262 }
1263 else
1264 {
1265 bitstatus = RESET;
1266 }
1267 /* Return the RCC_IT status */
1268 return bitstatus;
1269 }
1270
1271 /**
1272 * @brief Clears the RCC's interrupt pending bits.
1273 * @param RCC_IT: specifies the interrupt pending bit to clear.
1274 * This parameter can be any combination of the following values:
1275 * @arg RCC_IT_LSIRDY: LSI ready interrupt
1276 * @arg RCC_IT_LSERDY: LSE ready interrupt
1277 * @arg RCC_IT_HSIRDY: HSI ready interrupt
1278 * @arg RCC_IT_HSERDY: HSE ready interrupt
1279 * @arg RCC_IT_PLLRDY: PLL ready interrupt
1280 * @arg RCC_IT_CSS: Clock Security System interrupt
1281 * @retval : None
1282 */
RCC_ClearITPendingBit(uint8_t RCC_IT)1283 void RCC_ClearITPendingBit(uint8_t RCC_IT)
1284 {
1285 /* Check the parameters */
1286 assert_param(IS_RCC_CLEAR_IT(RCC_IT));
1287 /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt
1288 pending bits */
1289
1290 RCC->CIR |= (uint32_t)RCC_IT<<16;
1291 }
1292
1293 /**
1294 * @}
1295 */
1296
1297 /**
1298 * @}
1299 */
1300
1301 /**
1302 * @}
1303 */
1304
1305 /*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/
1306