1 /**************************************************************************** 2 * include/nuttx/usb/ohci.h 3 * 4 * Licensed to the Apache Software Foundation (ASF) under one or more 5 * contributor license agreements. See the NOTICE file distributed with 6 * this work for additional information regarding copyright ownership. The 7 * ASF licenses this file to you under the Apache License, Version 2.0 (the 8 * "License"); you may not use this file except in compliance with the 9 * License. You may obtain a copy of the License at 10 * 11 * http://www.apache.org/licenses/LICENSE-2.0 12 * 13 * Unless required by applicable law or agreed to in writing, software 14 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT 15 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the 16 * License for the specific language governing permissions and limitations 17 * under the License. 18 * 19 ****************************************************************************/ 20 21 #ifndef __INCLUDE_NUTTX_USB_OHCI_H 22 #define __INCLUDE_NUTTX_USB_OHCI_H 23 24 /**************************************************************************** 25 * Included Files 26 ****************************************************************************/ 27 28 #include <stdint.h> 29 30 /**************************************************************************** 31 * Pre-processor Definitions 32 ****************************************************************************/ 33 34 /* Register offsets *********************************************************/ 35 36 /* Control and status registers (section 7.1) */ 37 38 #define OHCI_HCIREV_OFFSET 0x0000 /* HcRevision: Version of HCI specification */ 39 #define OHCI_CTRL_OFFSET 0x0004 /* HcControl: HC control */ 40 #define OHCI_CMDST_OFFSET 0x0008 /* HcCommandStatus: HC command status */ 41 #define OHCI_INTST_OFFSET 0x000c /* HcInterruptStatus: HC interrupt status */ 42 #define OHCI_INTEN_OFFSET 0x0010 /* HcInterruptEnable: HC interrupt enable */ 43 #define OHCI_INTDIS_OFFSET 0x0014 /* HcInterruptDisable: HC interrupt disable */ 44 45 /* Memory pointer registers (section 7.2) */ 46 47 #define OHCI_HCCA_OFFSET 0x0018 /* HcHCCA: HC communication area */ 48 #define OHCI_PERED_OFFSET 0x001c /* HcPeriodCurrentED: Current isoc or int endpoint desc */ 49 #define OHCI_CTRLHEADED_OFFSET 0x0020 /* HcControlHeadED: First EP desc in the control list */ 50 #define OHCI_CTRLED_OFFSET 0x0024 /* HcControlCurrentED: Current EP desc in the control list */ 51 #define OHCI_BULKHEADED_OFFSET 0x0028 /* HcBulkHeadED: First EP desc in the bulk list */ 52 #define OHCI_BULKED_OFFSET 0x002c /* HcBulkCurrentED: Current EP desc in the bulk list */ 53 #define OHCI_DONEHEAD_OFFSET 0x0030 /* HcDoneHead: Last transfer desc added to DONE queue */ 54 55 /* Frame counter registers (section 7.3) */ 56 57 #define OHCI_FMINT_OFFSET 0x0034 /* HcFmInterval: Bit time interval that would not cause overrun */ 58 #define OHCI_FMREM_OFFSET 0x0038 /* HcFmRemaining: Bit time remaining in current frame */ 59 #define OHCI_FMNO_OFFSET 0x003c /* HcFmNumber: Frame number counter */ 60 #define OHCI_PERSTART_OFFSET 0x0040 /* HcPeriodicStart: Time to start processing periodic list */ 61 62 /* Root hub registers (section 7.4) */ 63 64 #define OHCI_LSTHRES_OFFSET 0x0044 /* HcLSThreshold: Commit to transfer threshold */ 65 #define OHCI_RHDESCA_OFFSET 0x0048 /* HcRhDescriptorA: Describes root hub (part A) */ 66 #define OHCI_RHDESCB_OFFSET 0x004c /* HcRhDescriptorB: Describes root hub (part B) */ 67 #define OHCI_RHSTATUS_OFFSET 0x0050 /* HcRhStatus: Root hub status */ 68 69 #define OHCI_MAX_RHPORT 15 /* Maximum number of OHCI root hub ports */ 70 71 #define OHCI_RHPORTST_OFFSET(n) (0x0054 + (((n) - 1) << 2)) 72 #define OHCI_RHPORTST1_OFFSET 0x0054 /* HcRhPort1Status: Root hub port status 1 */ 73 #define OHCI_RHPORTST2_OFFSET 0x0058 /* HcRhPort2Status: Root hub port status 2 */ 74 #define OHCI_RHPORTST3_OFFSET 0x005c /* HcRhPort3Status: Root hub port status 3 */ 75 #define OHCI_RHPORTST4_OFFSET 0x0060 /* HcRhPort4Status: Root hub port status 4 */ 76 #define OHCI_RHPORTST5_OFFSET 0x0064 /* HcRhPort5Status: Root hub port status 5 */ 77 #define OHCI_RHPORTST6_OFFSET 0x0068 /* HcRhPort6Status: Root hub port status 6 */ 78 #define OHCI_RHPORTST7_OFFSET 0x006c /* HcRhPort7Status: Root hub port status 7 */ 79 #define OHCI_RHPORTST8_OFFSET 0x0070 /* HcRhPort8Status: Root hub port status 8 */ 80 #define OHCI_RHPORTST9_OFFSET 0x0074 /* HcRhPort9Status: Root hub port status 9 */ 81 #define OHCI_RHPORTST10_OFFSET 0x0078 /* HcRhPort10Status: Root hub port status 10 */ 82 #define OHCI_RHPORTST11_OFFSET 0x007c /* HcRhPort11Status: Root hub port status 11 */ 83 #define OHCI_RHPORTST12_OFFSET 0x0080 /* HcRhPort12Status: Root hub port status 12 */ 84 #define OHCI_RHPORTST13_OFFSET 0x0084 /* HcRhPort13Status: Root hub port status 13 */ 85 #define OHCI_RHPORTST14_OFFSET 0x0088 /* HcRhPort14Status: Root hub port status 14 */ 86 #define OHCI_RHPORTST15_OFFSET 0x008c /* HcRhPort15Status: Root hub port status 15 */ 87 88 /* Register bit definitions *************************************************/ 89 90 /* HcRevision: Version of HCI specification (7.1.1) */ 91 92 #define OHCI_HCIREV_SHIFT (0) /* Bits 0-7: HCI spec version (BCD) */ 93 #define OHCI_HCIREV_MASK (0xff << OHCI_HCIREV_SHIFT) 94 95 /* HcControl: HC control (7.1.2) */ 96 97 #define OHCI_CTRL_CBSR (3 << 0) /* Bit 0: Control/bulk service ratio */ 98 #define OHCI_CTRL_PLE (1 << 2) /* Bit 2: Periodic list enable */ 99 #define OHCI_CTRL_IE (1 << 3) /* Bit 3: Isochronous enable */ 100 #define OHCI_CTRL_CLE (1 << 4) /* Bit 4: Control list enable */ 101 #define OHCI_CTRL_BLE (1 << 5) /* Bit 5: Bulk list enable */ 102 #define OHCI_CTRL_HCFS_SHIFT (6) /* Bits 6-7: Host controller functional state */ 103 #define OHCI_CTRL_HCFS_MASK (3 << OHCI_CTRL_HCFS_SHIFT) 104 # define OHCI_CTRL_HCFS_RESET (0 << OHCI_CTRL_HCFS_SHIFT) 105 # define OHCI_CTRL_HCFS_RESUME (1 << OHCI_CTRL_HCFS_SHIFT) 106 # define OHCI_CTRL_HCFS_OPER (2 << OHCI_CTRL_HCFS_SHIFT) 107 # define OHCI_CTRL_HCFS_SUSPEND (3 << OHCI_CTRL_HCFS_SHIFT) 108 #define OHCI_CTRL_IR (1 << 8) /* Bit 8: Interrupt routing */ 109 #define OHCI_CTRL_RWC (1 << 9) /* Bit 9: Remote wakeup connected */ 110 #define OHCI_CTRL_RWE (1 << 10) /* Bit 10: Remote wakeup enable */ 111 /* Bits 11-31: Reserved */ 112 113 /* HcCommandStatus: HC command status (7.1.3) */ 114 115 #define OHCI_CMDST_HCR (1 << 0) /* Bit 0: Host controller reset */ 116 #define OHCI_CMDST_CLF (1 << 1) /* Bit 1: Control list filled */ 117 #define OHCI_CMDST_BLF (1 << 2) /* Bit 2: Bulk list filled */ 118 #define OHCI_CMDST_OCR (1 << 3) /* Bit 3: Ownership change request */ 119 /* Bits 4-15: Reserved */ 120 #define OHCI_CMDST_SOC (3 << 16) /* Bit 16: Scheduling overrun count */ 121 /* Bits 17-31: Reserved */ 122 123 /* HcInterruptStatus: HC interrupt status (7.1.4), 124 * HcInterruptEnable: HC interrupt enable (7.1.5), and 125 * HcInterruptDisable: HC interrupt disable (7.1.6) 126 */ 127 128 #define OHCI_INT_SO (1 << 0) /* Bit 0: Scheduling overrun */ 129 #define OHCI_INT_WDH (1 << 1) /* Bit 1: Writeback done head */ 130 #define OHCI_INT_SF (1 << 2) /* Bit 2: Start of frame */ 131 #define OHCI_INT_RD (1 << 3) /* Bit 3: Resume detected */ 132 #define OHCI_INT_UE (1 << 4) /* Bit 4: Unrecoverable error */ 133 #define OHCI_INT_FNO (1 << 5) /* Bit 5: Frame number overflow */ 134 #define OHCI_INT_RHSC (1 << 6) /* Bit 6: Root hub status change */ 135 /* Bits 7-29: Reserved */ 136 #define OHCI_INT_OC (1 << 30) /* Bit 30: Ownership change */ 137 #define OHCI_INT_MIE (1 << 31) /* Bit 31: Master interrupt enable 138 * (Enable/disable only) */ 139 140 /* HcHCCA: HC communication area (7.2.1): 141 * 142 * 32-bits aligned to 256 byte boundary. 143 */ 144 145 /* HcPeriodCurrentED: Current isoc or int endpoint desc (7.2.2), 146 * HcControlHeadED: First EP desc in the control list (7.2.3), 147 * HcControlCurrentED: Current EP desc in the control list (7.2.4), 148 * HcBulkHeadED: First EP desc in the bulk list (7.2.5), 149 * HcBulkCurrentED: Current EP desc in the bulk list (7.2.6), and 150 * HcDoneHead: Last transfer desc added to DONE queue (7.2.7): 151 * 152 * All 32-bits aligned to an 8-byte boundary 153 */ 154 155 /* HcFmInterval: Bit time interval that would not cause overrun (7.3.1) */ 156 157 #define OHCI_FMINT_FI_SHIFT (0) /* Bits 0-13: Frame interval */ 158 #define OHCI_FMINT_FI_MASK (0x3fff << OHCI_FMINT_FI_SHIFT) 159 /* Bits 14-15: Reserved */ 160 #define OHCI_FMINT_FSMPS_SHIFT (16) /* Bits 16-30: FS largest packet data */ 161 #define OHCI_FMINT_FSMPS_MASK (0x7fff << OHCI_FMINT_FSMPS_SHIFT) 162 #define OHCI_FMINT_FIT (1 << 31) /* Bit 31: Frame interval toggle */ 163 164 /* HcFmRemaining: Bit time remaining in current frame (7.3.2) */ 165 166 #define OHCI_FMREM_FR_SHIFT (0) /* Bits 0-13: Frame remaining */ 167 #define OHCI_FMREM_FR_MASK (0x3fff << OHCI_FMREM_FR_SHIFT) 168 /* Bits 16-30: Reserved */ 169 #define OHCI_FMINT_FRT (1 << 31) /* Bit 31: Frame remaining toggle */ 170 171 /* HcFmNumber: Frame number counter (7.3.3) */ 172 173 #define OHCI_FMNO_FI_SHIFT (0) /* Bits 0-15: Frame number */ 174 #define OHCI_FMNO_FI_MASK (0xffff << OHCI_FMINT_FI_SHIFT) 175 /* Bits 16-31: Reserved */ 176 177 /* HcPeriodicStart: Time to start processing periodic list (7.3.4) */ 178 179 #define OHCI_PERSTART_SHIFT (0) /* Bits 0-13: Periodic start */ 180 #define OHCI_PERSTART_MASK (0x3fff << OHCI_PERSTART_SHIFT) 181 /* Bits 14-31: Reserved */ 182 183 /* HcLSThreshold: Commit to transfer threshold (7.3.5) */ 184 185 #define OHCI_LSTHRES_SHIFT (0) /* Bits 0-11: LS threshold */ 186 #define OHCI_LSTHRES_MASK (0x0fff << OHCI_PERSTART_SHIFT) 187 /* Bits 12-31: Reserved */ 188 189 /* HcRhDescriptorN: Describes root hub (part A) (7.4.1) */ 190 191 #define OHCI_RHDESCA_NDP_SHIFT (0) /* Bits 0-7: Number downstream ports */ 192 #define OHCI_RHDESCA_NDP_MASK (0xff << OHCI_RHDESCA_NDP_SHIFT) 193 #define OHCI_RHDESCA_PSM (1 << 8) /* Bit 8: Power switching mode */ 194 #define OHCI_RHDESCA_NPS (1 << 9) /* Bit 9: No power switching */ 195 #define OHCI_RHDESCA_DT (1 << 10) /* Bit 10: Device type */ 196 #define OHCI_RHDESCA_OCPM (1 << 11) /* Bit 11: Over current protection mode */ 197 #define OHCI_RHDESCA_NOCP (1 << 12) /* Bit 12: No over current protection */ 198 /* Bits 13-23: Reserved */ 199 #define OHCI_RHDESCA_POTPGT_SHIFT (24) /* Bits 24-31: Power on to power good time */ 200 #define OHCI_RHDESCA_POTPGT_MASK (0xff << OHCI_RHDESCA_POTPGT_SHIFT) 201 202 /* HcRhDescriptorB: Describes root hub (part B) (7.4.2) */ 203 204 #define OHCI_RHDESCB_DR_SHIFT (0) /* Bits 0-15: Device removable */ 205 #define OHCI_RHDESCB_DR_MASK (0xffff << OHCI_RHDESCB_DR_SHIFT) 206 # define OHCI_RHDESCB_ATTACHED(n) (1 << (OHCI_RHDESCB_DR_SHIFT+(n))) 207 #define OHCI_RHDESCB_PPCM_SHIFT (16) /* Bits 16-31: Port power control mask */ 208 #define OHCI_RHDESCB_PPCM_MASK (0xffff << OHCI_RHDESCB_PPCM_SHIFT) 209 # define OHCI_RHDESCB_POWERED(n) (1 << (OHCI_RHDESCB_DR_SHIFT+(n))) 210 211 /* HcRhStatus: Root hub status (7.4.3) */ 212 213 #define OHCI_RHSTATUS_LPS (1 << 0) /* Bit 0: Local power status (read)*/ 214 #define OHCI_RHSTATUS_CGP (1 << 0) /* Bit 0: Clear global power (write)*/ 215 #define OHCI_RHSTATUS_OCI (1 << 1) /* Bit 1: Over current indicator */ 216 /* Bits 2-14: Reserved */ 217 #define OHCI_RHSTATUS_DRWE (1 << 15) /* Bit 15: Device remote wakeup enable */ 218 #define OHCI_RHSTATUS_LPSC (1 << 16) /* Bit 16: Local power status change (read) */ 219 #define OHCI_RHSTATUS_SGP (1 << 16) /* Bit 16: Set global power (write) */ 220 #define OHCI_RHSTATUS_OCIC (1 << 17) /* Bit 17: Overcurrent indicator change */ 221 /* Bits 18-30: Reserved */ 222 #define OHCI_RHSTATUS_CRWE (1 << 31) /* Bit 31: Clear remote wakeup enable */ 223 224 /* HcRhPortStatus: Root hub port status (7.4.4) */ 225 226 #define OHCI_RHPORTST_CCS (1 << 0) /* Bit 0: Current connect status */ 227 #define OHCI_RHPORTST_PES (1 << 1) /* Bit 1: Port enable status */ 228 #define OHCI_RHPORTST_PSS (1 << 2) /* Bit 2: Port suspend status */ 229 #define OHCI_RHPORTST_POCI (1 << 3) /* Bit 3: Port over current indicator */ 230 #define OHCI_RHPORTST_PRS (1 << 4) /* Bit 4: Port reset status */ 231 /* Bits 5-7: Reserved */ 232 #define OHCI_RHPORTST_PPS (1 << 8) /* Bit 8: Port power status */ 233 #define OHCI_RHPORTST_LSDA (1 << 9) /* Bit 9: Low speed device attached */ 234 /* Bits 10-15: Reserved */ 235 #define OHCI_RHPORTST_CSC (1 << 16) /* Bit 16: Connect status change */ 236 #define OHCI_RHPORTST_PESC (1 << 17) /* Bit 17: Port enable status change */ 237 #define OHCI_RHPORTST_PSSC (1 << 18) /* Bit 18: Port suspend status change */ 238 #define OHCI_RHPORTST_OCIC (1 << 19) /* Bit 19: Port over current indicator change */ 239 #define OHCI_RHPORTST_PRSC (1 << 20) /* Bit 20: Port reset status change */ 240 /* Bits 21-31: Reserved */ 241 242 /* Transfer Descriptors *****************************************************/ 243 244 /* Endpoint Descriptor Offsets (4.2.1) */ 245 246 #define ED_CONTROL_OFFSET (0x00) /* ED status/control bits */ 247 #define ED_TAILP_OFFSET (0x04) /* TD Queue Tail Pointer (TailP) */ 248 #define ED_HEADP_OFFSET (0x08) /* TD Queue Head Pointer (HeadP) */ 249 #define ED_NEXTED_OFFSET (0x0c) /* Next Endpoint Descriptor (NextED) */ 250 251 /* Endpoint Descriptor Bit Definitions (4.2.2) */ 252 253 #define ED_CONTROL_FA_SHIFT (0) /* Bits 0-6: Function Address */ 254 #define ED_CONTROL_FA_MASK (0x7f << ED_CONTROL_FA_SHIFT) 255 #define ED_CONTROL_EN_SHIFT (7) /* Bits 7-10: Endpoint number */ 256 #define ED_CONTROL_EN_MASK (15 << ED_CONTROL_EN_SHIFT) 257 #define ED_CONTROL_D_SHIFT (11) /* Bits 11-12: Direction */ 258 #define ED_CONTROL_D_MASK (3 << ED_CONTROL_D_SHIFT) 259 # define ED_CONTROL_D_TD1 (0 << ED_CONTROL_D_SHIFT) /* Get direction from TD */ 260 # define ED_CONTROL_D_OUT (1 << ED_CONTROL_D_SHIFT) /* OUT */ 261 # define ED_CONTROL_D_IN (2 << ED_CONTROL_D_SHIFT) /* IN */ 262 # define ED_CONTROL_D_TD2 (3 << ED_CONTROL_D_SHIFT) /* Get direction from TD */ 263 264 #define ED_CONTROL_SPPED_LOW (1 << 13) /* Bit 13: Speed (low) */ 265 #define ED_CONTROL_SKIP (1 << 14) /* Bit 14: Skip */ 266 #define ED_CONTROL_FORMAT_ISO (1 << 15) /* Bit 15: Format (isochronous) */ 267 #define ED_CONTROL_MPS_SHIFT (16) /* Bits 16-26: Maximum packet size */ 268 #define ED_CONTROL_MPS_MASK (0x7ff << ED_CONTROL_MPS_SHIFT) 269 270 #define ED_HEADP_ADDR_SHIFT (0) 271 #define ED_HEADP_ADDR_MASK 0xfffffff0 272 #define ED_HEADP_H (1 << 0) /* Bit 0: Halted */ 273 #define ED_HEADP_C (1 << 1) /* Bit 1: Toggle carry */ 274 275 /* General Transfer Descriptor Offsets (4.3.1) */ 276 277 #define GTD_STATUS_OFFSET (0x00) /* TD status bits */ 278 #define GTD_CBP_OFFSET (0x04) /* Current Buffer Pointer (CBP) */ 279 #define GTD_NEXTTD_OFFSET (0x08) /* Next TD (NextTD) */ 280 #define GTD_BE_OFFSET (0x0c) /* Buffer End (BE) */ 281 282 /* General Transfer Descriptor Bit Definitions */ 283 284 /* Bits 0-17: Reserved */ 285 286 #define GTD_STATUS_R (1 << 18) /* Bit 18: Buffer rounding */ 287 #define GTD_STATUS_DP_SHIFT (19) /* Bits 19-20: Direction/PID */ 288 #define GTD_STATUS_DP_MASK (3 << GTD_STATUS_DP_SHIFT) 289 # define GTD_STATUS_DP_SETUP (0 << GTD_STATUS_DP_SHIFT) /* To endpoint */ 290 # define GTD_STATUS_DP_OUT (1 << GTD_STATUS_DP_SHIFT) /* To endpoint */ 291 # define GTD_STATUS_DP_IN (2 << GTD_STATUS_DP_SHIFT) /* From endpoint */ 292 293 #define GTD_STATUS_DI_SHIFT (21) /* Bits 21-23: Delay input */ 294 #define GTD_STATUS_DI_MASK (7 << GTD_STATUS_DI_SHIFT) 295 #define GTD_STATUS_T_SHIFT (24) /* Bits 24-25: Data Toggle */ 296 #define GTD_STATUS_T_MASK (3 << GTD_STATUS_T_SHIFT) 297 # define GTD_STATUS_T_TOGGLE (0 << GTD_STATUS_T_SHIFT) 298 # define GTD_STATUS_T_DATA0 (2 << GTD_STATUS_T_SHIFT) 299 # define GTD_STATUS_T_DATA1 (3 << GTD_STATUS_T_SHIFT) 300 #define GTD_STATUS_EC_SHIFT (26) /* Bits 26-27: Error count */ 301 #define GTD_STATUS_EC_MASK (3 << GTD_STATUS_EC_SHIFT) 302 #define GTD_STATUS_CC_SHIFT (28) /* Bits 28-31: Condition code */ 303 #define GTD_STATUS_CC_MASK (15 << GTD_STATUS_CC_SHIFT) 304 305 /* Isochronous Transfer Descriptor Offsets (4.3.2) */ 306 307 #define ITD_STATUS_OFFSET (0x00) /* TD status bits */ 308 #define ITD_BP0_OFFSET (0x04) /* Buffer page 0 (BP0) */ 309 #define ITD_NEXTTD_OFFSET (0x08) /* Next TD (NextTD) */ 310 #define ITD_BE_OFFSET (0x0c) /* Buffer End (BE) */ 311 312 #define ITD_NPSW (8) 313 #define ITD_PSW0_OFFSET (0x10) /* Offset0/PSW0 */ 314 #define ITD_PSW1_OFFSET (0x12) /* Offset1/PSW1 */ 315 #define ITD_PSW2_OFFSET (0x14) /* Offset2/PSW2 */ 316 #define ITD_PSW3_OFFSET (0x16) /* Offset3/PSW3 */ 317 #define ITD_PSW4_OFFSET (0x18) /* Offset4/PSW4 */ 318 #define ITD_PSW5_OFFSET (0x1a) /* Offset5/PSW5 */ 319 #define ITD_PSW6_OFFSET (0x1c) /* Offset6/PSW6 */ 320 #define ITD_PSW7_OFFSET (0x1e) /* Offset7/PSW7 */ 321 322 /* Condition codes (Table 4-7) */ 323 324 #define TD_CC_NOERROR 0x00 325 #define TD_CC_CRC 0x01 326 #define TD_CC_BITSTUFFING 0x02 327 #define TD_CC_DATATOGGLEMISMATCH 0x03 328 #define TD_CC_STALL 0x04 329 #define TD_CC_DEVNOTRESPONDING 0x05 330 #define TD_CC_PIDCHECKFAILURE 0x06 331 #define TD_CC_UNEXPECTEDPID 0x07 332 #define TD_CC_DATAOVERRUN 0x08 333 #define TD_CC_DATAUNDERRUN 0x09 334 #define TD_CC_BUFFEROVERRUN 0x0c 335 #define TD_CC_BUFFERUNDERRUN 0x0d 336 #define TD_CC_NOTACCESSED 0x0f 337 338 #define TD_CC_USER 0x10 /* For use by OHCI drivers */ 339 340 /* Host Controller Communications Area Format (4.4.1) ***********************/ 341 342 /* HccaInterruptTable: 32x32-bit pointers to interrupt EDs */ 343 344 #define HCCA_INTTBL_OFFSET (0x00) 345 #define HCCA_INTTBL_WSIZE (32) 346 #define HCCA_INTTBL_BSIZE (HCCA_INTTBL_WSIZE * 4) 347 348 /* HccaFrameNumber: Current frame number */ 349 350 #define HCCA_FMNO_OFFSET (0x80) 351 #define HCCA_FMNO_BSIZE (2) 352 353 /* HccaPad1: Zero when frame no. updated */ 354 355 #define HCCA_PAD1_OFFSET (0x82) 356 #define HCCA_PAD1_BSIZE (2) 357 358 /* HccaDoneHead: When the HC reaches the end of a frame and its deferred 359 * interrupt register is 0, it writes the current value of its HcDoneHead to 360 * this location and generates an interrupt. 361 * 362 * The LSB of HCCADoneHead may be set to 1 to indicate that an unmasked 363 * HcInterruptStatus was set when HccaDoneHead was written. 364 */ 365 366 #define HCCA_DONEHEAD_OFFSET (0x84) 367 #define HCCA_DONEHEAD_BSIZE (4) 368 369 #define HCCA_DONEHEAD_MASK 0xfffffffe 370 #define HCCA_DONEHEAD_INTSTA (1 << 0) 371 372 /* 0x88: 116 bytes reserved */ 373 374 #define HCCA_RESERVED_OFFSET (0x88) 375 #define HCCA_RESERVED_BSIZE (116) 376 377 /**************************************************************************** 378 * Public Types 379 ****************************************************************************/ 380 381 struct ohci_hcor 382 { 383 volatile uint32_t hcrevision; /* 0x00 */ 384 volatile uint32_t hccontrol; /* 0x04 */ 385 volatile uint32_t hccmdsts; /* 0x08 */ 386 volatile uint32_t hcintsts; /* 0x0c */ 387 volatile uint32_t hcinten; /* 0x10 */ 388 volatile uint32_t hcintdis; /* 0x14 */ 389 volatile uint32_t hchcca; /* 0x18 */ 390 volatile uint32_t hcperiodcurrented; /* 0x1c */ 391 volatile uint32_t hccontrolheaded; /* 0x20 */ 392 volatile uint32_t hccontrolcurrented; /* 0x24 */ 393 volatile uint32_t hcbulkheaded; /* 0x28 */ 394 volatile uint32_t hcbulkcurrented; /* 0x2c */ 395 volatile uint32_t hcdonehead; /* 0x30 */ 396 volatile uint32_t hcfminterval; /* 0x34 */ 397 volatile uint32_t hcfmremaining; /* 0x38 */ 398 volatile uint32_t hcfmnumber; /* 0x3c */ 399 volatile uint32_t hcperiodicstart; /* 0x40 */ 400 volatile uint32_t hclsthreshold; /* 0x44 */ 401 volatile uint32_t hcrhdescriptora; /* 0x48 */ 402 volatile uint32_t hcrhdescriptorb; /* 0x4c */ 403 volatile uint32_t hcrhsts; /* 0x50 */ 404 volatile uint32_t hcrhportsts[15]; /* 0x54 */ 405 }; 406 407 /* Endpoint Descriptor Offsets (4.2.1) */ 408 409 struct ohci_ed 410 { 411 volatile uint32_t ctrl; /* ED status/control bits */ 412 volatile uint32_t tailp; /* TD Queue Tail Pointer (TailP) */ 413 volatile uint32_t headp; /* TD Queue Head Pointer (HeadP) */ 414 volatile uint32_t nexted; /* Next Endpoint Descriptor (NextED) */ 415 }; 416 417 /* General Transfer Descriptor (4.3.1) */ 418 419 struct ohci_gtd 420 { 421 volatile uint32_t ctrl; /* TD status/control bits */ 422 volatile uint32_t cbp; /* Current Buffer Pointer (CBP) */ 423 volatile uint32_t nexttd; /* Next TD (NextTD) */ 424 volatile uint32_t be; /* Buffer End (BE) */ 425 }; 426 427 /* Isochronous Transfer Descriptor Offsets (4.3.2) */ 428 429 struct ohci_itd 430 { 431 volatile uint32_t ctrl; /* TD status/control bits */ 432 volatile uint32_t bp0; /* Buffer page 0 (BP0 */ 433 volatile uint32_t nexttd; /* Next TD (NextTD) */ 434 volatile uint32_t be; /* Buffer End (BE) */ 435 volatile uint16_t psw[ITD_NPSW]; /* Offset/PSW */ 436 }; 437 438 /* Host Controller Communications Area Format (4.4.1) */ 439 440 struct ohci_hcca 441 { 442 /* HccaInterruptTable: 32x32-bit pointers to interrupt EDs */ 443 444 volatile uint32_t inttbl[HCCA_INTTBL_WSIZE]; 445 446 /* HccaFrameNumber: Current frame number and 447 * HccaPad1: Zero when frame no. updated 448 */ 449 450 volatile uint16_t fmno; 451 volatile uint16_t pad1; 452 453 /* HccaDoneHead: When the HC reaches the end of a frame and its deferred 454 * interrupt register is 0, it writes the current value of its HcDoneHead 455 * to this location and generates an interrupt. 456 */ 457 458 volatile uint32_t donehead; 459 volatile uint8_t reserved[HCCA_RESERVED_BSIZE]; 460 volatile uint32_t extra; 461 } __attribute__((aligned(256))); 462 463 /**************************************************************************** 464 * Public Data 465 ****************************************************************************/ 466 467 #ifdef __cplusplus 468 #define EXTERN extern "C" 469 extern "C" 470 { 471 #else 472 #define EXTERN extern 473 #endif 474 475 /**************************************************************************** 476 * Public Function Prototypes 477 ****************************************************************************/ 478 479 #undef EXTERN 480 #ifdef __cplusplus 481 } 482 #endif 483 484 #endif /* __INCLUDE_NUTTX_USB_OHCI_H */ 485