1 /*
2 * Copyright (c) 2021 HPMicro
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 *
6 */
7
8 #ifndef HPM_I2C_DRV_H
9 #define HPM_I2C_DRV_H
10 #include "hpm_common.h"
11 #include "hpm_i2c_regs.h"
12 #include "hpm_soc_feature.h"
13
14 /**
15 * @brief I2C driver APIs
16 * @defgroup i2c_interface I2C driver APIs
17 * @ingroup io_interfaces
18 * @{
19 */
20
21 /**
22 * @brief I2C status
23 */
24 enum {
25 status_i2c_no_ack = MAKE_STATUS(status_group_i2c, 1),
26 status_i2c_invalid_data = MAKE_STATUS(status_group_i2c, 2),
27 status_i2c_no_addr_hit = MAKE_STATUS(status_group_i2c, 3),
28 status_i2c_transmit_not_completed = MAKE_STATUS(status_group_i2c, 4),
29 status_i2c_not_supported = MAKE_STATUS(status_group_i2c, 9),
30 };
31
32 /* convert data count value into register(CTRL[DATACNT] and CTRL[DATACNT_HIGH] if exist) */
33 /* x range from 1 to I2C_SOC_TRANSFER_COUNT_MAX */
34 /* 0 for I2C_SOC_TRANSFER_COUNT_MAX */
35 #define I2C_DATACNT_MAP(x) (((x) == I2C_SOC_TRANSFER_COUNT_MAX) ? 0 : x)
36
37 /**
38 * @brief I2C CMD
39 */
40 #define I2C_CMD_NO_ACTION (I2C_CMD_CMD_SET(0))
41 #define I2C_CMD_ISSUE_DATA_TRANSMISSION (I2C_CMD_CMD_SET(1))
42 #define I2C_CMD_ACK (I2C_CMD_CMD_SET(2))
43 #define I2C_CMD_NACK (I2C_CMD_CMD_SET(3))
44 #define I2C_CMD_CLEAR_FIFO (I2C_CMD_CMD_SET(4))
45 #define I2C_CMD_RESET (I2C_CMD_CMD_SET(5))
46
47 /**
48 * @brief I2C data direction
49 */
50 #define I2C_DIR_MASTER_WRITE (0U)
51 #define I2C_DIR_MASTER_READ (1U)
52 #define I2C_DIR_SLAVE_READ (0U)
53 #define I2C_DIR_SLAVE_WRITE (1U)
54
55 /**
56 * @brief I2C events for interrupt enable and status check
57 */
58 #define I2C_EVENT_TRANSACTION_COMPLETE I2C_INTEN_CMPL_MASK
59 #define I2C_EVENT_BYTE_RECEIVED I2C_INTEN_BYTERECV_MASK
60 #define I2C_EVENT_BYTE_TRANSMIT I2C_INTEN_BYTETRANS_MASK
61 #define I2C_EVENT_START_CONDITION I2C_INTEN_START_MASK
62 #define I2C_EVENT_STOP_CONDITION I2C_INTEN_STOP_MASK
63 #define I2C_EVENT_LOSS_ARBITRATION I2C_INTEN_ARBLOSE_MASK
64 #define I2C_EVENT_ADDRESS_HIT I2C_INTEN_ADDRHIT_MASK
65 #define I2C_EVENT_FIFO_HALF I2C_INTEN_FIFOHALF_MASK
66 #define I2C_EVENT_FIFO_FULL I2C_INTEN_FIFOFULL_MASK
67 #define I2C_EVENT_FIFO_EMPTY I2C_INTEN_FIFOEMPTY_MASK
68
69 #define I2C_EVENT_ALL_MASK (I2C_INTEN_CMPL_MASK \
70 | I2C_INTEN_BYTERECV_MASK \
71 | I2C_INTEN_BYTETRANS_MASK \
72 | I2C_INTEN_START_MASK \
73 | I2C_INTEN_STOP_MASK \
74 | I2C_INTEN_ARBLOSE_MASK \
75 | I2C_INTEN_ADDRHIT_MASK \
76 | I2C_INTEN_FIFOHALF_MASK \
77 | I2C_INTEN_FIFOFULL_MASK \
78 | I2C_INTEN_FIFOEMPTY_MASK)
79 /**
80 * @brief I2C status for status check only
81 */
82 #define I2C_STATUS_LINE_SDA I2C_STATUS_LINESDA_MASK
83 #define I2C_STATUS_LINE_SCL I2C_STATUS_LINESCL_MASK
84 #define I2C_STATUS_GENERAL_CALL I2C_STATUS_GENCALL_MASK
85 #define I2C_STATUS_BUS_BUSY I2C_STATUS_BUSBUSY_MASK
86 #define I2C_STATUS_ACK I2C_STATUS_ACK_MASK
87
88 #define I2C_WR 0x0000 /* not operable with read flags*/
89 #define I2C_RD (1u << 0) /* not operable with write flags*/
90 #define I2C_ADDR_10BIT (1u << 2) /* this is a ten bit chip address */
91 #define I2C_NO_START (1u << 4) /* no start */
92 #define I2C_NO_READ_ACK (1u << 6) /* when I2C reading, we do not ACK */
93 #define I2C_NO_STOP (1u << 7) /* no stop */
94
95 /**
96 * @brief I2C config
97 */
98 typedef struct {
99 bool is_10bit_addressing;
100 uint8_t i2c_mode;
101 } i2c_config_t;
102
103 /**
104 * @brief I2C mode
105 */
106 typedef enum i2c_mode {
107 i2c_mode_normal,
108 i2c_mode_fast,
109 i2c_mode_fast_plus,
110 } i2c_mode_t;
111
112 /**
113 * @brief I2c sequential transfer options
114 * @arg: i2c_frist_frame: has start signal
115 * @arg: i2c_next_frame: middle transfer
116 * @arg: i2c_last_frame: has stop signal
117 */
118 typedef enum i2c_seq_transfer_opt {
119 i2c_frist_frame = 0,
120 i2c_next_frame,
121 i2c_last_frame,
122 } i2c_seq_transfer_opt_t;
123
124 #ifdef __cplusplus
125 extern "C" {
126 #endif
127
128 /**
129 * @brief respond NACK
130 *
131 * @param [in] ptr I2C base address
132 */
i2c_respond_Nack(I2C_Type * ptr)133 static inline void i2c_respond_Nack(I2C_Type *ptr)
134 {
135 ptr->CMD = I2C_CMD_NACK;
136 }
137
138 /**
139 * @brief respond ACK
140 *
141 * @param [in] ptr I2C base address
142 */
i2c_respond_ack(I2C_Type * ptr)143 static inline void i2c_respond_ack(I2C_Type *ptr)
144 {
145 ptr->CMD = I2C_CMD_ACK;
146 }
147
148 /**
149 * @brief clear I2C fifo
150 *
151 * @param [in] ptr I2C base address
152 */
i2c_clear_fifo(I2C_Type * ptr)153 static inline void i2c_clear_fifo(I2C_Type *ptr)
154 {
155 ptr->CMD = I2C_CMD_CLEAR_FIFO;
156 }
157
158 /**
159 * @brief check data count
160 *
161 * @details It indicates number of bytes to transfer
162 *
163 * @param [in] ptr I2C base address
164 * @retval data count value in byte
165 */
i2c_get_data_count(I2C_Type * ptr)166 static inline uint16_t i2c_get_data_count(I2C_Type *ptr)
167 {
168 uint32_t i2c_ctrl = ptr->CTRL;
169 #ifdef I2C_CTRL_DATACNT_HIGH_MASK
170 return (I2C_CTRL_DATACNT_HIGH_GET(i2c_ctrl) << 8U) + I2C_CTRL_DATACNT_GET(i2c_ctrl);
171 #else
172 return I2C_CTRL_DATACNT_GET(i2c_ctrl);
173 #endif
174 }
175
176 /**
177 * @brief check if I2C FIFO is full
178 *
179 * @param [in] ptr I2C base address
180 * @retval true if FIFO is full
181 */
i2c_fifo_is_full(I2C_Type * ptr)182 static inline bool i2c_fifo_is_full(I2C_Type *ptr)
183 {
184 return ptr->STATUS & I2C_STATUS_FIFOFULL_MASK;
185 }
186
187 /**
188 * @brief check if I2C FIFO is half
189 *
190 * @note When I2C is transmitting data, it indicates if fifo is half-empty;
191 * @note When I2C is receiving data, it indicates if fifo is half full.
192 *
193 * @param [in] ptr I2C base address
194 * @retval true if FIFO is half empty or full
195 */
i2c_fifo_is_half(I2C_Type * ptr)196 static inline bool i2c_fifo_is_half(I2C_Type *ptr)
197 {
198 return ptr->STATUS & I2C_STATUS_FIFOHALF_MASK;
199 }
200
201 /**
202 * @brief check if I2C FIFO is empty
203 *
204 * @param [in] ptr I2C base address
205 * @retval true if FIFO is empty
206 */
i2c_fifo_is_empty(I2C_Type * ptr)207 static inline bool i2c_fifo_is_empty(I2C_Type *ptr)
208 {
209 return ptr->STATUS & I2C_STATUS_FIFOEMPTY_MASK;
210 }
211
212 /**
213 * @brief check if I2C is writing
214 *
215 * @param [in] ptr I2C base address
216 * @retval bool value
217 * @arg true: receive data if master mode, send data in slave mode
218 * @arg false: send data if master mode, reveive data in slave mode
219 *
220 */
i2c_is_writing(I2C_Type * ptr)221 static inline bool i2c_is_writing(I2C_Type *ptr)
222 {
223 return (ptr->CTRL & I2C_CTRL_DIR_MASK);
224 }
225
226 /**
227 * @brief check if I2C is reading
228 *
229 * @param [in] ptr I2C base address
230 * @retval bool value
231 * @arg true: send data if master mode, receive data in slave mode
232 * @arg false: receive data if master mode, send data in slave mode
233 *
234 */
i2c_is_reading(I2C_Type * ptr)235 static inline bool i2c_is_reading(I2C_Type *ptr)
236 {
237 return !i2c_is_writing(ptr);
238 }
239
240 /**
241 * @brief get i2c sda line status
242 *
243 * @param [in] ptr I2C base address
244 * @retval bool value
245 * @arg true: the sda line is high
246 * @arg false: the sda line is low
247 *
248 */
i2c_get_line_sda_status(I2C_Type * ptr)249 static inline bool i2c_get_line_sda_status(I2C_Type *ptr)
250 {
251 return I2C_STATUS_LINESDA_GET(ptr->STATUS);
252 }
253
254 /**
255 * @brief get i2c scl line status
256 *
257 * @param [in] ptr I2C base address
258 * @retval bool value
259 * @arg true: the scl line is high
260 * @arg false: the scl line is low
261 *
262 */
i2c_get_line_scl_status(I2C_Type * ptr)263 static inline bool i2c_get_line_scl_status(I2C_Type *ptr)
264 {
265 return I2C_STATUS_LINESCL_GET(ptr->STATUS);
266 }
267
268 /**
269 * @brief clear status
270 *
271 * @details Clear status based on mask
272 *
273 * @param [in] ptr I2C base address
274 * @param [in] mask mask to clear status
275 */
i2c_clear_status(I2C_Type * ptr,uint32_t mask)276 static inline void i2c_clear_status(I2C_Type *ptr, uint32_t mask)
277 {
278 ptr->STATUS = mask;
279 }
280
281 /**
282 * @brief get status
283 *
284 * @details Get current I2C status bits
285 *
286 * @param [in] ptr I2C base address
287 * @retval current I2C status
288 */
i2c_get_status(I2C_Type * ptr)289 static inline uint32_t i2c_get_status(I2C_Type *ptr)
290 {
291 return ptr->STATUS;
292 }
293
294 /**
295 * @brief i2c get interrupts setting
296 *
297 * @details Get interrupt setting register value
298 *
299 * @param [in] ptr I2C base address
300 * @retval [out] uint32_t interrupt setting register value
301 */
i2c_get_irq_setting(I2C_Type * ptr)302 static inline uint32_t i2c_get_irq_setting(I2C_Type *ptr)
303 {
304 return ptr->INTEN;
305 }
306
307 /**
308 * @brief disable interrupts
309 *
310 * @details Disable interrupts based on given mask
311 *
312 * @param [in] ptr I2C base address
313 * @param [in] mask interrupt mask to be disabled
314 */
i2c_disable_irq(I2C_Type * ptr,uint32_t mask)315 static inline void i2c_disable_irq(I2C_Type *ptr, uint32_t mask)
316 {
317 ptr->INTEN &= ~mask;
318 }
319
320 /**
321 * @brief enable interrupts
322 *
323 * @details Enable interrupts based on given mask
324 *
325 * @param [in] ptr I2C base address
326 * @param [in] mask interrupt mask to be enabled
327 */
i2c_enable_irq(I2C_Type * ptr,uint32_t mask)328 static inline void i2c_enable_irq(I2C_Type *ptr, uint32_t mask)
329 {
330 ptr->INTEN |= mask;
331 }
332
333 /**
334 * @brief disable auto ack
335 *
336 * @details Disable I2C auto generates proper acknowledgements for each byte received
337 *
338 * @param [in] ptr I2C base address
339 */
i2c_disable_auto_ack(I2C_Type * ptr)340 static inline void i2c_disable_auto_ack(I2C_Type *ptr)
341 {
342 ptr->INTEN &= ~I2C_EVENT_BYTE_RECEIVED;
343 }
344
345 /**
346 * @brief enable auto ack
347 *
348 * @details Enable I2C auto generates proper acknowledgements for each byte received
349 *
350 * @param [in] ptr I2C base address
351 */
i2c_enable_auto_ack(I2C_Type * ptr)352 static inline void i2c_enable_auto_ack(I2C_Type *ptr)
353 {
354 ptr->INTEN |= I2C_EVENT_BYTE_RECEIVED;
355 }
356
357 /**
358 * @brief enable 10 bit address mode
359 *
360 * @details enable 10 bit address mode, if not, address is 7 bit mode
361 *
362 * @param [in] ptr I2C base address
363 * @param [in] enable
364 * @arg true: enable 10 bit address mode
365 * @arg false: enable 7 bit address mode
366 */
i2c_enable_10bit_address_mode(I2C_Type * ptr,bool enable)367 static inline void i2c_enable_10bit_address_mode(I2C_Type *ptr, bool enable)
368 {
369 ptr->SETUP |= I2C_SETUP_ADDRESSING_SET(enable);
370 }
371
372 /**
373 * @brief I2C master initialization
374 *
375 * @details Initialized I2C controller working at master mode
376 *
377 * @param [in] ptr I2C base address
378 * @param [in] src_clk_in_hz I2C controller source clock source frequency in Hz
379 * @param [in] config i2c_config_t
380 * @retval hpm_stat_t: status_success if initialization is completed without any error
381 */
382 hpm_stat_t i2c_init_master(I2C_Type *ptr,
383 uint32_t src_clk_in_hz,
384 i2c_config_t *config);
385
386 /**
387 * @brief I2C master write data to specific address of certain slave device
388 *
389 * @details Write to certain I2C device at specific address within that device
390 * @note the sum of addr_size_in_byte and size_in_byte should not not greater than I2C_SOC_TRANSFER_COUNT_MAX
391 *
392 * @param [in] ptr I2C base address
393 * @param [in] device_address I2C slave address
394 * @param [in] addr address in that I2C device
395 * @param [in] addr_size_in_byte I2C address in byte
396 * @param [in] buf pointer of the data to be sent
397 * @param [in] size_in_byte size of data to be sent in bytes
398 * @retval hpm_stat_t: status_success if writing is completed without any error
399 */
400 hpm_stat_t i2c_master_address_write(I2C_Type *ptr,
401 const uint16_t device_address,
402 uint8_t *addr,
403 uint32_t addr_size_in_byte,
404 uint8_t *buf,
405 const uint32_t size_in_byte);
406
407 /**
408 * @brief I2C master read data from specific address of certain slave device
409 *
410 * @details Read fram certain I2C device at specific address within that device
411 * @note both addr_size_in_byte and size_in_byte should not not greater than I2C_SOC_TRANSFER_COUNT_MAX
412 *
413 * @param [in] ptr I2C base address
414 * @param [in] device_address I2C slave address
415 * @param [in] addr address in that I2C device
416 * @param [in] addr_size_in_byte I2C address in byte
417 * @param [out] buf pointer of the buffer to receive data read from the device
418 * @param [in] size_in_byte size of data to be read in bytes
419 * @retval hpm_stat_t: status_success if reading is completed without any error
420 */
421 hpm_stat_t i2c_master_address_read(I2C_Type *ptr,
422 const uint16_t device_address,
423 uint8_t *addr,
424 uint32_t addr_size_in_byte,
425 uint8_t *buf,
426 const uint32_t size_in_byte);
427
428 /**
429 * @brief I2C master write data to certain slave device
430 *
431 * @details Write data to I2C device
432 * @note size should not not greater than I2C_SOC_TRANSFER_COUNT_MAX
433 *
434 * @param [in] ptr I2C base address
435 * @param [in] device_address I2C slave address
436 * @param [in] buf pointer of the data to be sent
437 * @param [in] size size of data to be sent in bytes
438 * @retval hpm_stat_t: status_success if writing is completed without any error
439 */
440 hpm_stat_t i2c_master_write(I2C_Type *ptr,
441 const uint16_t device_address,
442 uint8_t *buf,
443 const uint32_t size);
444
445 /**
446 * @brief I2C master start write data by DMA
447 *
448 * @details Write data to I2C device by DMA
449 * @note size should not not greater than I2C_SOC_TRANSFER_COUNT_MAX
450 *
451 * @param [in] i2c_ptr I2C base address
452 * @param [in] device_address I2C slave address
453 * @param [in] size size of data to be sent in bytes
454 * @retval hpm_stat_t status_success if starting transmission without any error
455 */
456 hpm_stat_t i2c_master_start_dma_write(I2C_Type *i2c_ptr, const uint16_t device_address, uint32_t size);
457
458 /**
459 * @brief I2C master start read data by DMA
460 *
461 * @details Read data to I2C device by DMA
462 * @note size should not not greater than I2C_SOC_TRANSFER_COUNT_MAX
463 *
464 * @param [in] i2c_ptr I2C base address
465 * @param [in] device_address I2C slave address
466 * @param [in] size size of data to be read in bytes
467 * @retval hpm_stat_t status_success if starting transmission without any error
468 */
469 hpm_stat_t i2c_master_start_dma_read(I2C_Type *i2c_ptr, const uint16_t device_address, uint32_t size);
470
471 /**
472 * @brief I2C master read data from certain slave device
473 *
474 * @details Read data from I2C device
475 * @note size should not not greater than I2C_SOC_TRANSFER_COUNT_MAX
476 *
477 * @param [in] ptr I2C base address
478 * @param [in] device_address I2C slave address
479 * @param [out] buf pointer of the buffer to store data read from device
480 * @param [in] size size of data to be read in bytes
481 * @retval hpm_stat_t: status_success if reading is completed without any error
482 */
483 hpm_stat_t i2c_master_read(I2C_Type *ptr,
484 const uint16_t device_address,
485 uint8_t *buf,
486 const uint32_t size);
487 /**
488 * @brief I2C slave initialization
489 *
490 * @details Initialize I2C controller working at slave mode
491 *
492 * @param [in] ptr I2C base address
493 * @param [in] src_clk_in_hz I2C controller source clock source frequency in Hz
494 * @param [in] config I2C configuration structure
495 * @param [in] slave_address I2C address to be used at slave mode
496 * @retval hpm_stat_t: status_success if initialization is completed without any error
497 */
498 hpm_stat_t i2c_init_slave(I2C_Type *ptr, uint32_t src_clk_in_hz,
499 i2c_config_t *config, const uint16_t slave_address);
500
501 /**
502 * @brief I2C slave read data
503 *
504 * @details Read data at slave mode
505 * @note size should not not greater than I2C_SOC_TRANSFER_COUNT_MAX
506 *
507 * @param [in] ptr I2C base address
508 * @param [in] buf pointer of the buffer to store data read from device
509 * @param [in] size size of data to be read in bytes
510 * @retval hpm_stat_t: status_success if reading is completed without any error
511 */
512 hpm_stat_t i2c_slave_read(I2C_Type *ptr, uint8_t *buf, const uint32_t size);
513
514 /**
515 * @brief I2C slave write data
516 *
517 * @details Write data at slave mode.
518 * @note size should not not greater than I2C_SOC_TRANSFER_COUNT_MAX
519 *
520 * @param [in] ptr I2C base address
521 * @param [in] buf pointer of the buffer to store data sent from device
522 * @param [in] size size of data to be sent in bytes
523 * @retval hpm_stat_t status_success if writing is completed without any error
524 */
525 hpm_stat_t i2c_slave_write(I2C_Type *ptr, uint8_t *buf, const uint32_t size);
526
527 /**
528 * @brief reset I2C
529 *
530 * @param [in] ptr I2C base address
531 */
532 void i2c_reset(I2C_Type *ptr);
533
534 /**
535 * @brief Enable i2c DMA
536 *
537 * @param [in] ptr I2C base address
538 */
i2c_dma_enable(I2C_Type * ptr)539 static inline void i2c_dma_enable(I2C_Type *ptr)
540 {
541 ptr->SETUP |= I2C_SETUP_DMAEN_MASK;
542 }
543
544 /**
545 * @brief Disable i2c DMA
546 *
547 * @param [in] ptr I2C base address
548 */
i2c_dma_disable(I2C_Type * ptr)549 static inline void i2c_dma_disable(I2C_Type *ptr)
550 {
551 ptr->SETUP &= ~I2C_SETUP_DMAEN_MASK;
552 }
553
554 /**
555 * @brief I2C slave dma transfer data
556 *
557 * @note The direction of data transmission depends on Master setting
558 *
559 * @param [in] ptr I2C base address
560 * @param [in] size size of data in bytes
561 * @retval hpm_stat_t status_success if configuring transmission without any error
562 */
563 hpm_stat_t i2c_slave_dma_transfer(I2C_Type *ptr, const uint32_t size);
564
565 /**
566 * @brief I2C write byte into FIFO
567 *
568 * @param ptr [in] ptr I2C base address
569 * @param data [in] byte to ne sent
570 */
i2c_write_byte(I2C_Type * ptr,uint8_t data)571 static inline void i2c_write_byte(I2C_Type *ptr, uint8_t data)
572 {
573 ptr->DATA = I2C_DATA_DATA_SET(data);
574 }
575
576 /**
577 * @brief I2C read byte into FIFO
578 *
579 * @param ptr [in] ptr I2C base address
580 * @return uint8_t read byte
581 */
i2c_read_byte(I2C_Type * ptr)582 static inline uint8_t i2c_read_byte(I2C_Type *ptr)
583 {
584 return (uint8_t)I2C_DATA_DATA_GET(ptr->DATA);
585 }
586
587 /**
588 * @brief I2C get direction
589 *
590 * @note The same value has different meanings in master and slave modes
591 *
592 * @param ptr [in] ptr I2C base address
593 * @return uint8_t direction value
594 */
i2c_get_direction(I2C_Type * ptr)595 static inline uint8_t i2c_get_direction(I2C_Type *ptr)
596 {
597 return (uint8_t)I2C_CTRL_DIR_GET(ptr->CTRL);
598 }
599
600 /**
601 * @brief I2C master configure transfer setting
602 *
603 * @param i2c_ptr [in] ptr I2C base address
604 * @param device_address [in] I2C slave address
605 * @param size [in] size of data to be transferred in bytes
606 * @param read [in] true for receive, false for transmit
607 * @retval hpm_stat_t status_success if configuring transmission without any error
608 */
609 hpm_stat_t i2c_master_configure_transfer(I2C_Type *i2c_ptr, const uint16_t device_address, uint32_t size, bool read);
610
611 /**
612 * @brief sequential transmit in master I2C mode an amount of data in blocking
613 *
614 * @param [in] ptr ptr I2C base address
615 * @param [in] device_address I2C slave address
616 * @param [in] buf pointer of the buffer to store data sent from device
617 * @param [in] size size of data to be sent in bytes
618 * @param [in] opt I2c sequential transfer options
619 * @retval hpm_stat_t status_success if transmit is completed without any error
620 */
621 hpm_stat_t i2c_master_seq_transmit(I2C_Type *ptr, const uint16_t device_address,
622 uint8_t *buf, const uint32_t size, i2c_seq_transfer_opt_t opt);
623
624 /**
625 * @brief sequential receive in master I2C mode an amount of data in blocking
626 *
627 * @param [in] ptr ptr I2C base address
628 * @param [in] device_address I2C slave address
629 * @param [in] buf pointer of the buffer to store data sent from device
630 * @param [in] size size of data to be sent in bytes
631 * @param [in] opt I2c sequential transfer options
632 * @retval hpm_stat_t status_success if receive is completed without any error
633 */
634 hpm_stat_t i2c_master_seq_receive(I2C_Type *ptr, const uint16_t device_address,
635 uint8_t *buf, const uint32_t size, i2c_seq_transfer_opt_t opt);
636
637 #if defined(HPM_IP_FEATURE_I2C_SUPPORT_RESET) && (HPM_IP_FEATURE_I2C_SUPPORT_RESET == 1)
638 /**
639 * @brief generate SCL clock as reset signal
640 *
641 * @param ptr [in] ptr I2C base address
642 * @param [in] clk_len SCL clock length
643 */
i2s_gen_reset_signal(I2C_Type * ptr,uint8_t clk_len)644 static inline void i2s_gen_reset_signal(I2C_Type *ptr, uint8_t clk_len)
645 {
646 ptr->CTRL = (ptr->CTRL & ~I2C_CTRL_RESET_LEN_MASK) | I2C_CTRL_RESET_LEN_SET(clk_len) \
647 | I2C_CTRL_RESET_HOLD_SCKIN_MASK | I2C_CTRL_RESET_ON_MASK;
648 }
649 #endif
650
651 /**
652 * @brief data transfer on master I2C mode in blocking
653 *
654 * @param [in] ptr ptr I2C base address
655 * @param [in] device_address I2C slave address
656 * @param [in] buf pointer of the buffer to store data sent from device
657 * @param [in] size size of data to be sent in bytes
658 * @param [in] flags flag bit, which can be other flag bits except I2C_WR I2C_RD, and can perform "|" operation
659 * @retval hpm_stat_t status_success if receive is completed without any error
660 */
661 hpm_stat_t i2c_master_transfer(I2C_Type *ptr, const uint16_t device_address,
662 uint8_t *buf, const uint32_t size, uint16_t flags);
663 /**
664 * @}
665 */
666
667 #ifdef __cplusplus
668 }
669 #endif
670
671 #endif /* HPM_I2C_DRV_H */
672
673