1 /*
2 * This is a generated file
3 *
4 * Copyright 2021 QuickLogic
5 *
6 * Licensed under the Apache License, Version 2.0 (the "License");
7 * you may not use this file except in compliance with the License.
8 * You may obtain a copy of the License at
9 *
10 * http://www.apache.org/licenses/LICENSE-2.0
11 *
12 * Unless required by applicable law or agreed to in writing, software
13 * distributed under the License is distributed on an "AS IS" BASIS,
14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 * See the License for the specific language governing permissions and
16 * limitations under the License.
17 *
18 * SPDX-License-Identifier: Apache-2.0
19 */
20
21 #ifndef __APB_I2CS_H_
22 #define __APB_I2CS_H_
23
24 //---------------------------------//
25 //
26 // Module: APB_I2CS
27 //
28 //---------------------------------//
29
30 #ifndef __IO
31 #define __IO volatile
32 #endif
33
34 #ifndef __I
35 #define __I volatile
36 #endif
37
38 #ifndef __O
39 #define __O volatile
40 #endif
41
42 #include "stdint.h"
43
44 typedef struct {
45
46 // Offset = 0x0000
47 union {
48 __IO uint32_t i2cs_dev_address;
49 struct {
50 __IO uint32_t slave_addr : 7;
51 __IO uint32_t reserved : 1;
52 } i2cs_dev_address_b;
53 };
54
55 // Offset = 0x0004
56 union {
57 __IO uint32_t i2cs_enable;
58 struct {
59 __IO uint32_t ip_enable : 1;
60 __IO uint32_t reserved : 7;
61 } i2cs_enable_b;
62 };
63
64 // Offset = 0x0008
65 union {
66 __IO uint32_t i2cs_debounce_length;
67 struct {
68 __IO uint32_t deb_len : 8;
69 } i2cs_debounce_length_b;
70 };
71
72 // Offset = 0x000c
73 union {
74 __IO uint32_t i2cs_scl_delay_length;
75 struct {
76 __IO uint32_t scl_dly_len : 8;
77 } i2cs_scl_delay_length_b;
78 };
79
80 // Offset = 0x0010
81 union {
82 __IO uint32_t i2cs_sda_delay_length;
83 struct {
84 __IO uint32_t sda_dly_len : 8;
85 } i2cs_sda_delay_length_b;
86 };
87 __I uint32_t unused0[11];
88
89 // Offset = 0x0040
90 union {
91 __IO uint32_t i2cs_msg_i2c_apb;
92 struct {
93 __IO uint32_t i2c_to_apb : 8;
94 } i2cs_msg_i2c_apb_b;
95 };
96
97 // Offset = 0x0044
98 union {
99 __IO uint32_t i2cs_msg_i2c_apb_status;
100 struct {
101 __IO uint32_t i2c_to_apb_status : 1;
102 __IO uint32_t reserved : 7;
103 } i2cs_msg_i2c_apb_status_b;
104 };
105
106 // Offset = 0x0048
107 union {
108 __IO uint32_t i2cs_msg_apb_i2c;
109 struct {
110 __IO uint32_t apb_to_i2c : 8;
111 } i2cs_msg_apb_i2c_b;
112 };
113
114 // Offset = 0x004c
115 union {
116 __IO uint32_t i2cs_msg_apb_i2c_status;
117 struct {
118 __IO uint32_t apb_to_i2c_status : 1;
119 __IO uint32_t reserved : 7;
120 } i2cs_msg_apb_i2c_status_b;
121 };
122 __I uint32_t unused1[12];
123
124 // Offset = 0x0080
125 union {
126 __IO uint32_t i2cs_fifo_i2c_apb_write_data_port;
127 struct {
128 __IO uint32_t i2c_apb_write_data_port : 32;
129 } i2cs_fifo_i2c_apb_write_data_port_b;
130 };
131
132 // Offset = 0x0084
133 union {
134 __IO uint32_t i2cs_fifo_i2c_apb_read_data_port;
135 struct {
136 __IO uint32_t i2c_apb_read_data_port : 32;
137 } i2cs_fifo_i2c_apb_read_data_port_b;
138 };
139
140 // Offset = 0x0088
141 union {
142 __IO uint32_t i2cs_fifo_i2c_apb_flush;
143 struct {
144 __IO uint32_t enable : 1;
145 __IO uint32_t reserved : 7;
146 } i2cs_fifo_i2c_apb_flush_b;
147 };
148
149 // Offset = 0x008c
150 union {
151 __IO uint32_t i2cs_fifo_i2c_apb_write_flags;
152 struct {
153 __IO uint32_t flags : 3;
154 __IO uint32_t reserved : 5;
155 } i2cs_fifo_i2c_apb_write_flags_b;
156 };
157
158 // Offset = 0x0090
159 union {
160 __IO uint32_t i2cs_fifo_i2c_apb_read_flags;
161 struct {
162 __IO uint32_t flags : 3;
163 __IO uint32_t reserved : 5;
164 } i2cs_fifo_i2c_apb_read_flags_b;
165 };
166 __I uint32_t unused2[11];
167
168 // Offset = 0x00c0
169 union {
170 __IO uint32_t i2cs_fifo_apb_i2c_write_data_port;
171 struct {
172 __IO uint32_t i2c_apb_write_data_port : 32;
173 } i2cs_fifo_apb_i2c_write_data_port_b;
174 };
175
176 // Offset = 0x00c4
177 union {
178 __IO uint32_t i2cs_fifo_apb_i2c_read_data_port;
179 struct {
180 __IO uint32_t i2c_apb_read_data_port : 32;
181 } i2cs_fifo_apb_i2c_read_data_port_b;
182 };
183
184 // Offset = 0x00c8
185 union {
186 __IO uint32_t i2cs_fifo_apb_i2c_flush;
187 struct {
188 __IO uint32_t enable : 1;
189 __IO uint32_t reserved : 7;
190 } i2cs_fifo_apb_i2c_flush_b;
191 };
192
193 // Offset = 0x00cc
194 union {
195 __IO uint32_t i2cs_fifo_apb_i2c_write_flags;
196 struct {
197 __IO uint32_t flags : 3;
198 __IO uint32_t reserved : 5;
199 } i2cs_fifo_apb_i2c_write_flags_b;
200 };
201
202 // Offset = 0x00d0
203 union {
204 __IO uint32_t i2cs_fifo_apb_i2c_read_flags;
205 struct {
206 __IO uint32_t flags : 3;
207 __IO uint32_t reserved : 5;
208 } i2cs_fifo_apb_i2c_read_flags_b;
209 };
210 __I uint32_t unused3[11];
211
212 // Offset = 0x0100
213 union {
214 __IO uint32_t i2cs_interrupt_status;
215 struct {
216 __IO uint32_t apb_i2c_message_available : 1;
217 __IO uint32_t apb_i2c_fifo_read_status : 1;
218 __IO uint32_t i2c_apb_fifo_write_status : 1;
219 __IO uint32_t reserved : 5;
220 } i2cs_interrupt_status_b;
221 };
222
223 // Offset = 0x0104
224 union {
225 __IO uint32_t i2cs_interrupt_enable;
226 struct {
227 __IO uint32_t apb_i2c_message_available_int_enable : 1;
228 __IO uint32_t apb_i2c_fifo_read_status_int_enable : 1;
229 __IO uint32_t i2c_apb_fifo_write_status_int_enable : 1;
230 __IO uint32_t reserved : 5;
231 } i2cs_interrupt_enable_b;
232 };
233
234 // Offset = 0x0108
235 union {
236 __IO uint32_t i2cs_interrupt_i2c_apb_write_flags_select;
237 struct {
238 __IO uint32_t write_flag_128_space_avail : 1;
239 __IO uint32_t write_flag_64_127_space_avail : 1;
240 __IO uint32_t write_flag_32_63_space_avail : 1;
241 __IO uint32_t write_flag_8_31_space_avail : 1;
242 __IO uint32_t write_flag_4_7_space_avail : 1;
243 __IO uint32_t write_flag_2_3_space_avail : 1;
244 __IO uint32_t write_flag_1_space_avail : 1;
245 __IO uint32_t write_flag_full : 1;
246 } i2cs_interrupt_i2c_apb_write_flags_select_b;
247 };
248
249 // Offset = 0x010c
250 union {
251 __IO uint32_t i2cs_interrupt_apb_i2c_read_flags_select;
252 struct {
253 __IO uint32_t read_flag_empty : 1;
254 __IO uint32_t read_flag_1_space_avail : 1;
255 __IO uint32_t read_flag_2_3_space_avail : 1;
256 __IO uint32_t read_flag_4_7_space_avail : 1;
257 __IO uint32_t read_flag_8_31_space_avail : 1;
258 __IO uint32_t read_flag_32_63_space_avail : 1;
259 __IO uint32_t read_flag_64_127_space_avail : 1;
260 __IO uint32_t read_flag_128_space_avail : 1;
261 } i2cs_interrupt_apb_i2c_read_flags_select_b;
262 };
263 __I uint32_t unused4[12];
264
265 // Offset = 0x0140
266 union {
267 __IO uint32_t i2cs_interrupt_to_apb_status;
268 struct {
269 __IO uint32_t new_i2c_apb_msg_avail : 1;
270 __IO uint32_t i2c_apb_fifo_read_status : 1;
271 __IO uint32_t apb_i2c_fifo_write_status : 1;
272 __IO uint32_t reserved : 5;
273 } i2cs_interrupt_to_apb_status_b;
274 };
275
276 // Offset = 0x0144
277 union {
278 __IO uint32_t i2cs_interrupt_to_apb_enable;
279 struct {
280 __IO uint32_t new_i2c_apb_msg_avail_enable : 1;
281 __IO uint32_t i2c_apb_fifo_read_status_enable : 1;
282 __IO uint32_t apb_i2c_fifo_write_status_enable : 1;
283 __IO uint32_t reserved : 5;
284 } i2cs_interrupt_to_apb_enable_b;
285 };
286
287 // Offset = 0x0148
288 union {
289 __IO uint32_t i2cs_interrupt_apb_i2c_write_flags_select;
290 struct {
291 __IO uint32_t write_flag_128_space_avail : 1;
292 __IO uint32_t write_flag_64_127_space_avail : 1;
293 __IO uint32_t write_flag_32_63_space_avail : 1;
294 __IO uint32_t write_flag_8_31_space_avail : 1;
295 __IO uint32_t write_flag_4_7_space_avail : 1;
296 __IO uint32_t write_flag_2_3_space_avail : 1;
297 __IO uint32_t write_flag_1_space_avail : 1;
298 __IO uint32_t write_flag_full : 1;
299 } i2cs_interrupt_apb_i2c_write_flags_select_b;
300 };
301
302 // Offset = 0x014c
303 union {
304 __IO uint32_t i2cs_interrupt_i2c_apb_read_flags_select;
305 struct {
306 __IO uint32_t read_flag_empty : 1;
307 __IO uint32_t read_flag_1_space_avail : 1;
308 __IO uint32_t read_flag_2_3_space_avail : 1;
309 __IO uint32_t read_flag_4_7_space_avail : 1;
310 __IO uint32_t read_flag_8_31_space_avail : 1;
311 __IO uint32_t read_flag_32_63_space_avail : 1;
312 __IO uint32_t read_flag_64_127_space_avail : 1;
313 __IO uint32_t read_flag_128_space_avail : 1;
314 } i2cs_interrupt_i2c_apb_read_flags_select_b;
315 };
316 } ApbI2cs_t;
317
318
319 #define REG_I2CS_DEV_ADDRESS 0x000
320 #define REG_I2CS_DEV_ADDRESS_RESERVED_LSB 7
321 #define REG_I2CS_DEV_ADDRESS_RESERVED_MASK 0x1
322 #define REG_I2CS_DEV_ADDRESS_SLAVE_ADDR_LSB 0
323 #define REG_I2CS_DEV_ADDRESS_SLAVE_ADDR_MASK 0x7f
324 #define REG_I2CS_ENABLE 0x004
325 #define REG_I2CS_ENABLE_RESERVED_LSB 1
326 #define REG_I2CS_ENABLE_RESERVED_MASK 0x7f
327 #define REG_I2CS_ENABLE_IP_ENABLE_LSB 0
328 #define REG_I2CS_ENABLE_IP_ENABLE_MASK 0x1
329 #define REG_I2CS_DEBOUNCE_LENGTH 0x008
330 #define REG_I2CS_DEBOUNCE_LENGTH_DEB_LEN_LSB 0
331 #define REG_I2CS_DEBOUNCE_LENGTH_DEB_LEN_MASK 0xff
332 #define REG_I2CS_SCL_DELAY_LENGTH 0x00C
333 #define REG_I2CS_SCL_DELAY_LENGTH_SCL_DLY_LEN_LSB 0
334 #define REG_I2CS_SCL_DELAY_LENGTH_SCL_DLY_LEN_MASK 0xff
335 #define REG_I2CS_SDA_DELAY_LENGTH 0x010
336 #define REG_I2CS_SDA_DELAY_LENGTH_SDA_DLY_LEN_LSB 0
337 #define REG_I2CS_SDA_DELAY_LENGTH_SDA_DLY_LEN_MASK 0xff
338 #define REG_I2CS_MSG_I2C_APB 0x040
339 #define REG_I2CS_MSG_I2C_APB_I2C_TO_APB_LSB 0
340 #define REG_I2CS_MSG_I2C_APB_I2C_TO_APB_MASK 0xff
341 #define REG_I2CS_MSG_I2C_APB_STATUS 0x044
342 #define REG_I2CS_MSG_I2C_APB_STATUS_RESERVED_LSB 1
343 #define REG_I2CS_MSG_I2C_APB_STATUS_RESERVED_MASK 0x7f
344 #define REG_I2CS_MSG_I2C_APB_STATUS_I2C_TO_APB_STATUS_LSB 0
345 #define REG_I2CS_MSG_I2C_APB_STATUS_I2C_TO_APB_STATUS_MASK 0x1
346 #define REG_I2CS_MSG_APB_I2C 0x048
347 #define REG_I2CS_MSG_APB_I2C_APB_TO_I2C_LSB 0
348 #define REG_I2CS_MSG_APB_I2C_APB_TO_I2C_MASK 0xff
349 #define REG_I2CS_MSG_APB_I2C_STATUS 0x04C
350 #define REG_I2CS_MSG_APB_I2C_STATUS_RESERVED_LSB 1
351 #define REG_I2CS_MSG_APB_I2C_STATUS_RESERVED_MASK 0x7f
352 #define REG_I2CS_MSG_APB_I2C_STATUS_APB_TO_I2C_STATUS_LSB 0
353 #define REG_I2CS_MSG_APB_I2C_STATUS_APB_TO_I2C_STATUS_MASK 0x1
354 #define REG_I2CS_FIFO_I2C_APB_WRITE_DATA_PORT 0x080
355 #define REG_I2CS_FIFO_I2C_APB_WRITE_DATA_PORT_I2C_APB_WRITE_DATA_PORT_LSB 0
356 #define REG_I2CS_FIFO_I2C_APB_WRITE_DATA_PORT_I2C_APB_WRITE_DATA_PORT_MASK 0xffffffff
357 #define REG_I2CS_FIFO_I2C_APB_READ_DATA_PORT 0x084
358 #define REG_I2CS_FIFO_I2C_APB_READ_DATA_PORT_I2C_APB_READ_DATA_PORT_LSB 0
359 #define REG_I2CS_FIFO_I2C_APB_READ_DATA_PORT_I2C_APB_READ_DATA_PORT_MASK 0xffffffff
360 #define REG_I2CS_FIFO_I2C_APB_FLUSH 0x088
361 #define REG_I2CS_FIFO_I2C_APB_FLUSH_RESERVED_LSB 1
362 #define REG_I2CS_FIFO_I2C_APB_FLUSH_RESERVED_MASK 0x7f
363 #define REG_I2CS_FIFO_I2C_APB_FLUSH_ENABLE_LSB 0
364 #define REG_I2CS_FIFO_I2C_APB_FLUSH_ENABLE_MASK 0x1
365 #define REG_I2CS_FIFO_I2C_APB_WRITE_FLAGS 0x08C
366 #define REG_I2CS_FIFO_I2C_APB_WRITE_FLAGS_RESERVED_LSB 3
367 #define REG_I2CS_FIFO_I2C_APB_WRITE_FLAGS_RESERVED_MASK 0x1f
368 #define REG_I2CS_FIFO_I2C_APB_WRITE_FLAGS_FLAGS_LSB 0
369 #define REG_I2CS_FIFO_I2C_APB_WRITE_FLAGS_FLAGS_MASK 0x7
370 #define REG_I2CS_FIFO_I2C_APB_READ_FLAGS 0x090
371 #define REG_I2CS_FIFO_I2C_APB_READ_FLAGS_RESERVED_LSB 3
372 #define REG_I2CS_FIFO_I2C_APB_READ_FLAGS_RESERVED_MASK 0x1f
373 #define REG_I2CS_FIFO_I2C_APB_READ_FLAGS_FLAGS_LSB 0
374 #define REG_I2CS_FIFO_I2C_APB_READ_FLAGS_FLAGS_MASK 0x7
375 #define REG_I2CS_FIFO_APB_I2C_WRITE_DATA_PORT 0x0C0
376 #define REG_I2CS_FIFO_APB_I2C_WRITE_DATA_PORT_I2C_APB_WRITE_DATA_PORT_LSB 0
377 #define REG_I2CS_FIFO_APB_I2C_WRITE_DATA_PORT_I2C_APB_WRITE_DATA_PORT_MASK 0xffffffff
378 #define REG_I2CS_FIFO_APB_I2C_READ_DATA_PORT 0x0C4
379 #define REG_I2CS_FIFO_APB_I2C_READ_DATA_PORT_I2C_APB_READ_DATA_PORT_LSB 0
380 #define REG_I2CS_FIFO_APB_I2C_READ_DATA_PORT_I2C_APB_READ_DATA_PORT_MASK 0xffffffff
381 #define REG_I2CS_FIFO_APB_I2C_FLUSH 0x0C8
382 #define REG_I2CS_FIFO_APB_I2C_FLUSH_RESERVED_LSB 1
383 #define REG_I2CS_FIFO_APB_I2C_FLUSH_RESERVED_MASK 0x7f
384 #define REG_I2CS_FIFO_APB_I2C_FLUSH_ENABLE_LSB 0
385 #define REG_I2CS_FIFO_APB_I2C_FLUSH_ENABLE_MASK 0x1
386 #define REG_I2CS_FIFO_APB_I2C_WRITE_FLAGS 0x0CC
387 #define REG_I2CS_FIFO_APB_I2C_WRITE_FLAGS_RESERVED_LSB 3
388 #define REG_I2CS_FIFO_APB_I2C_WRITE_FLAGS_RESERVED_MASK 0x1f
389 #define REG_I2CS_FIFO_APB_I2C_WRITE_FLAGS_FLAGS_LSB 0
390 #define REG_I2CS_FIFO_APB_I2C_WRITE_FLAGS_FLAGS_MASK 0x7
391 #define REG_I2CS_FIFO_APB_I2C_READ_FLAGS 0x0D0
392 #define REG_I2CS_FIFO_APB_I2C_READ_FLAGS_RESERVED_LSB 3
393 #define REG_I2CS_FIFO_APB_I2C_READ_FLAGS_RESERVED_MASK 0x1f
394 #define REG_I2CS_FIFO_APB_I2C_READ_FLAGS_FLAGS_LSB 0
395 #define REG_I2CS_FIFO_APB_I2C_READ_FLAGS_FLAGS_MASK 0x7
396 #define REG_I2CS_INTERRUPT_STATUS 0x100
397 #define REG_I2CS_INTERRUPT_STATUS_RESERVED_LSB 3
398 #define REG_I2CS_INTERRUPT_STATUS_RESERVED_MASK 0x1f
399 #define REG_I2CS_INTERRUPT_STATUS_I2C_APB_FIFO_WRITE_STATUS_LSB 2
400 #define REG_I2CS_INTERRUPT_STATUS_I2C_APB_FIFO_WRITE_STATUS_MASK 0x1
401 #define REG_I2CS_INTERRUPT_STATUS_APB_I2C_FIFO_READ_STATUS_LSB 1
402 #define REG_I2CS_INTERRUPT_STATUS_APB_I2C_FIFO_READ_STATUS_MASK 0x1
403 #define REG_I2CS_INTERRUPT_STATUS_APB_I2C_MESSAGE_AVAILABLE_LSB 0
404 #define REG_I2CS_INTERRUPT_STATUS_APB_I2C_MESSAGE_AVAILABLE_MASK 0x1
405 #define REG_I2CS_INTERRUPT_ENABLE 0x104
406 #define REG_I2CS_INTERRUPT_ENABLE_RESERVED_LSB 3
407 #define REG_I2CS_INTERRUPT_ENABLE_RESERVED_MASK 0x1f
408 #define REG_I2CS_INTERRUPT_ENABLE_I2C_APB_FIFO_WRITE_STATUS_INT_ENABLE_LSB 2
409 #define REG_I2CS_INTERRUPT_ENABLE_I2C_APB_FIFO_WRITE_STATUS_INT_ENABLE_MASK 0x1
410 #define REG_I2CS_INTERRUPT_ENABLE_APB_I2C_FIFO_READ_STATUS_INT_ENABLE_LSB 1
411 #define REG_I2CS_INTERRUPT_ENABLE_APB_I2C_FIFO_READ_STATUS_INT_ENABLE_MASK 0x1
412 #define REG_I2CS_INTERRUPT_ENABLE_APB_I2C_MESSAGE_AVAILABLE_INT_ENABLE_LSB 0
413 #define REG_I2CS_INTERRUPT_ENABLE_APB_I2C_MESSAGE_AVAILABLE_INT_ENABLE_MASK 0x1
414 #define REG_I2CS_INTERRUPT_I2C_APB_WRITE_FLAGS_SELECT 0x108
415 #define REG_I2CS_INTERRUPT_I2C_APB_WRITE_FLAGS_SELECT_WRITE_FLAG_FULL_LSB 7
416 #define REG_I2CS_INTERRUPT_I2C_APB_WRITE_FLAGS_SELECT_WRITE_FLAG_FULL_MASK 0x1
417 #define REG_I2CS_INTERRUPT_I2C_APB_WRITE_FLAGS_SELECT_WRITE_FLAG_1_SPACE_AVAIL_LSB 6
418 #define REG_I2CS_INTERRUPT_I2C_APB_WRITE_FLAGS_SELECT_WRITE_FLAG_1_SPACE_AVAIL_MASK 0x1
419 #define REG_I2CS_INTERRUPT_I2C_APB_WRITE_FLAGS_SELECT_WRITE_FLAG_2_3_SPACE_AVAIL_LSB 5
420 #define REG_I2CS_INTERRUPT_I2C_APB_WRITE_FLAGS_SELECT_WRITE_FLAG_2_3_SPACE_AVAIL_MASK 0x1
421 #define REG_I2CS_INTERRUPT_I2C_APB_WRITE_FLAGS_SELECT_WRITE_FLAG_4_7_SPACE_AVAIL_LSB 4
422 #define REG_I2CS_INTERRUPT_I2C_APB_WRITE_FLAGS_SELECT_WRITE_FLAG_4_7_SPACE_AVAIL_MASK 0x1
423 #define REG_I2CS_INTERRUPT_I2C_APB_WRITE_FLAGS_SELECT_WRITE_FLAG_8_31_SPACE_AVAIL_LSB 3
424 #define REG_I2CS_INTERRUPT_I2C_APB_WRITE_FLAGS_SELECT_WRITE_FLAG_8_31_SPACE_AVAIL_MASK 0x1
425 #define REG_I2CS_INTERRUPT_I2C_APB_WRITE_FLAGS_SELECT_WRITE_FLAG_32_63_SPACE_AVAIL_LSB 2
426 #define REG_I2CS_INTERRUPT_I2C_APB_WRITE_FLAGS_SELECT_WRITE_FLAG_32_63_SPACE_AVAIL_MASK 0x1
427 #define REG_I2CS_INTERRUPT_I2C_APB_WRITE_FLAGS_SELECT_WRITE_FLAG_64_127_SPACE_AVAIL_LSB 1
428 #define REG_I2CS_INTERRUPT_I2C_APB_WRITE_FLAGS_SELECT_WRITE_FLAG_64_127_SPACE_AVAIL_MASK 0x1
429 #define REG_I2CS_INTERRUPT_I2C_APB_WRITE_FLAGS_SELECT_WRITE_FLAG_128_SPACE_AVAIL_LSB 0
430 #define REG_I2CS_INTERRUPT_I2C_APB_WRITE_FLAGS_SELECT_WRITE_FLAG_128_SPACE_AVAIL_MASK 0x1
431 #define REG_I2CS_INTERRUPT_APB_I2C_READ_FLAGS_SELECT 0x10C
432 #define REG_I2CS_INTERRUPT_APB_I2C_READ_FLAGS_SELECT_READ_FLAG_128_SPACE_AVAIL_LSB 7
433 #define REG_I2CS_INTERRUPT_APB_I2C_READ_FLAGS_SELECT_READ_FLAG_128_SPACE_AVAIL_MASK 0x1
434 #define REG_I2CS_INTERRUPT_APB_I2C_READ_FLAGS_SELECT_READ_FLAG_64_127_SPACE_AVAIL_LSB 6
435 #define REG_I2CS_INTERRUPT_APB_I2C_READ_FLAGS_SELECT_READ_FLAG_64_127_SPACE_AVAIL_MASK 0x1
436 #define REG_I2CS_INTERRUPT_APB_I2C_READ_FLAGS_SELECT_READ_FLAG_32_63_SPACE_AVAIL_LSB 5
437 #define REG_I2CS_INTERRUPT_APB_I2C_READ_FLAGS_SELECT_READ_FLAG_32_63_SPACE_AVAIL_MASK 0x1
438 #define REG_I2CS_INTERRUPT_APB_I2C_READ_FLAGS_SELECT_READ_FLAG_8_31_SPACE_AVAIL_LSB 4
439 #define REG_I2CS_INTERRUPT_APB_I2C_READ_FLAGS_SELECT_READ_FLAG_8_31_SPACE_AVAIL_MASK 0x1
440 #define REG_I2CS_INTERRUPT_APB_I2C_READ_FLAGS_SELECT_READ_FLAG_4_7_SPACE_AVAIL_LSB 3
441 #define REG_I2CS_INTERRUPT_APB_I2C_READ_FLAGS_SELECT_READ_FLAG_4_7_SPACE_AVAIL_MASK 0x1
442 #define REG_I2CS_INTERRUPT_APB_I2C_READ_FLAGS_SELECT_READ_FLAG_2_3_SPACE_AVAIL_LSB 2
443 #define REG_I2CS_INTERRUPT_APB_I2C_READ_FLAGS_SELECT_READ_FLAG_2_3_SPACE_AVAIL_MASK 0x1
444 #define REG_I2CS_INTERRUPT_APB_I2C_READ_FLAGS_SELECT_READ_FLAG_1_SPACE_AVAIL_LSB 1
445 #define REG_I2CS_INTERRUPT_APB_I2C_READ_FLAGS_SELECT_READ_FLAG_1_SPACE_AVAIL_MASK 0x1
446 #define REG_I2CS_INTERRUPT_APB_I2C_READ_FLAGS_SELECT_READ_FLAG_EMPTY_LSB 0
447 #define REG_I2CS_INTERRUPT_APB_I2C_READ_FLAGS_SELECT_READ_FLAG_EMPTY_MASK 0x1
448 #define REG_I2CS_INTERRUPT_TO_APB_STATUS 0x140
449 #define REG_I2CS_INTERRUPT_TO_APB_STATUS_RESERVED_LSB 3
450 #define REG_I2CS_INTERRUPT_TO_APB_STATUS_RESERVED_MASK 0x1f
451 #define REG_I2CS_INTERRUPT_TO_APB_STATUS_APB_I2C_FIFO_WRITE_STATUS_LSB 2
452 #define REG_I2CS_INTERRUPT_TO_APB_STATUS_APB_I2C_FIFO_WRITE_STATUS_MASK 0x1
453 #define REG_I2CS_INTERRUPT_TO_APB_STATUS_I2C_APB_FIFO_READ_STATUS_LSB 1
454 #define REG_I2CS_INTERRUPT_TO_APB_STATUS_I2C_APB_FIFO_READ_STATUS_MASK 0x1
455 #define REG_I2CS_INTERRUPT_TO_APB_STATUS_NEW_I2C_APB_MSG_AVAIL_LSB 0
456 #define REG_I2CS_INTERRUPT_TO_APB_STATUS_NEW_I2C_APB_MSG_AVAIL_MASK 0x1
457 #define REG_I2CS_INTERRUPT_TO_APB_ENABLE 0x144
458 #define REG_I2CS_INTERRUPT_TO_APB_ENABLE_RESERVED_LSB 3
459 #define REG_I2CS_INTERRUPT_TO_APB_ENABLE_RESERVED_MASK 0x1f
460 #define REG_I2CS_INTERRUPT_TO_APB_ENABLE_APB_I2C_FIFO_WRITE_STATUS_ENABLE_LSB 2
461 #define REG_I2CS_INTERRUPT_TO_APB_ENABLE_APB_I2C_FIFO_WRITE_STATUS_ENABLE_MASK 0x1
462 #define REG_I2CS_INTERRUPT_TO_APB_ENABLE_I2C_APB_FIFO_READ_STATUS_ENABLE_LSB 1
463 #define REG_I2CS_INTERRUPT_TO_APB_ENABLE_I2C_APB_FIFO_READ_STATUS_ENABLE_MASK 0x1
464 #define REG_I2CS_INTERRUPT_TO_APB_ENABLE_NEW_I2C_APB_MSG_AVAIL_ENABLE_LSB 0
465 #define REG_I2CS_INTERRUPT_TO_APB_ENABLE_NEW_I2C_APB_MSG_AVAIL_ENABLE_MASK 0x1
466 #define REG_I2CS_INTERRUPT_APB_I2C_WRITE_FLAGS_SELECT 0x148
467 #define REG_I2CS_INTERRUPT_APB_I2C_WRITE_FLAGS_SELECT_WRITE_FLAG_FULL_LSB 7
468 #define REG_I2CS_INTERRUPT_APB_I2C_WRITE_FLAGS_SELECT_WRITE_FLAG_FULL_MASK 0x1
469 #define REG_I2CS_INTERRUPT_APB_I2C_WRITE_FLAGS_SELECT_WRITE_FLAG_1_SPACE_AVAIL_LSB 6
470 #define REG_I2CS_INTERRUPT_APB_I2C_WRITE_FLAGS_SELECT_WRITE_FLAG_1_SPACE_AVAIL_MASK 0x1
471 #define REG_I2CS_INTERRUPT_APB_I2C_WRITE_FLAGS_SELECT_WRITE_FLAG_2_3_SPACE_AVAIL_LSB 5
472 #define REG_I2CS_INTERRUPT_APB_I2C_WRITE_FLAGS_SELECT_WRITE_FLAG_2_3_SPACE_AVAIL_MASK 0x1
473 #define REG_I2CS_INTERRUPT_APB_I2C_WRITE_FLAGS_SELECT_WRITE_FLAG_4_7_SPACE_AVAIL_LSB 4
474 #define REG_I2CS_INTERRUPT_APB_I2C_WRITE_FLAGS_SELECT_WRITE_FLAG_4_7_SPACE_AVAIL_MASK 0x1
475 #define REG_I2CS_INTERRUPT_APB_I2C_WRITE_FLAGS_SELECT_WRITE_FLAG_8_31_SPACE_AVAIL_LSB 3
476 #define REG_I2CS_INTERRUPT_APB_I2C_WRITE_FLAGS_SELECT_WRITE_FLAG_8_31_SPACE_AVAIL_MASK 0x1
477 #define REG_I2CS_INTERRUPT_APB_I2C_WRITE_FLAGS_SELECT_WRITE_FLAG_32_63_SPACE_AVAIL_LSB 2
478 #define REG_I2CS_INTERRUPT_APB_I2C_WRITE_FLAGS_SELECT_WRITE_FLAG_32_63_SPACE_AVAIL_MASK 0x1
479 #define REG_I2CS_INTERRUPT_APB_I2C_WRITE_FLAGS_SELECT_WRITE_FLAG_64_127_SPACE_AVAIL_LSB 1
480 #define REG_I2CS_INTERRUPT_APB_I2C_WRITE_FLAGS_SELECT_WRITE_FLAG_64_127_SPACE_AVAIL_MASK 0x1
481 #define REG_I2CS_INTERRUPT_APB_I2C_WRITE_FLAGS_SELECT_WRITE_FLAG_128_SPACE_AVAIL_LSB 0
482 #define REG_I2CS_INTERRUPT_APB_I2C_WRITE_FLAGS_SELECT_WRITE_FLAG_128_SPACE_AVAIL_MASK 0x1
483 #define REG_I2CS_INTERRUPT_I2C_APB_READ_FLAGS_SELECT 0x14C
484 #define REG_I2CS_INTERRUPT_I2C_APB_READ_FLAGS_SELECT_READ_FLAG_128_SPACE_AVAIL_LSB 7
485 #define REG_I2CS_INTERRUPT_I2C_APB_READ_FLAGS_SELECT_READ_FLAG_128_SPACE_AVAIL_MASK 0x1
486 #define REG_I2CS_INTERRUPT_I2C_APB_READ_FLAGS_SELECT_READ_FLAG_64_127_SPACE_AVAIL_LSB 6
487 #define REG_I2CS_INTERRUPT_I2C_APB_READ_FLAGS_SELECT_READ_FLAG_64_127_SPACE_AVAIL_MASK 0x1
488 #define REG_I2CS_INTERRUPT_I2C_APB_READ_FLAGS_SELECT_READ_FLAG_32_63_SPACE_AVAIL_LSB 5
489 #define REG_I2CS_INTERRUPT_I2C_APB_READ_FLAGS_SELECT_READ_FLAG_32_63_SPACE_AVAIL_MASK 0x1
490 #define REG_I2CS_INTERRUPT_I2C_APB_READ_FLAGS_SELECT_READ_FLAG_8_31_SPACE_AVAIL_LSB 4
491 #define REG_I2CS_INTERRUPT_I2C_APB_READ_FLAGS_SELECT_READ_FLAG_8_31_SPACE_AVAIL_MASK 0x1
492 #define REG_I2CS_INTERRUPT_I2C_APB_READ_FLAGS_SELECT_READ_FLAG_4_7_SPACE_AVAIL_LSB 3
493 #define REG_I2CS_INTERRUPT_I2C_APB_READ_FLAGS_SELECT_READ_FLAG_4_7_SPACE_AVAIL_MASK 0x1
494 #define REG_I2CS_INTERRUPT_I2C_APB_READ_FLAGS_SELECT_READ_FLAG_2_3_SPACE_AVAIL_LSB 2
495 #define REG_I2CS_INTERRUPT_I2C_APB_READ_FLAGS_SELECT_READ_FLAG_2_3_SPACE_AVAIL_MASK 0x1
496 #define REG_I2CS_INTERRUPT_I2C_APB_READ_FLAGS_SELECT_READ_FLAG_1_SPACE_AVAIL_LSB 1
497 #define REG_I2CS_INTERRUPT_I2C_APB_READ_FLAGS_SELECT_READ_FLAG_1_SPACE_AVAIL_MASK 0x1
498 #define REG_I2CS_INTERRUPT_I2C_APB_READ_FLAGS_SELECT_READ_FLAG_EMPTY_LSB 0
499 #define REG_I2CS_INTERRUPT_I2C_APB_READ_FLAGS_SELECT_READ_FLAG_EMPTY_MASK 0x1
500
501 #ifndef __REGFIELD_OPS_
502 #define __REGFIELD_OPS_
regfield_read(uint32_t reg,uint32_t mask,uint32_t lsb)503 static inline uint32_t regfield_read(uint32_t reg, uint32_t mask, uint32_t lsb) {
504 return (reg >> lsb) & mask;
505 }
regfield_write(uint32_t reg,uint32_t mask,uint32_t lsb,uint32_t value)506 static inline uint32_t regfield_write(uint32_t reg, uint32_t mask, uint32_t lsb, uint32_t value) {
507 reg &= ~(mask << lsb);
508 reg |= (value & mask) << lsb;
509 return reg;
510 }
511 #endif // __REGFIELD_OPS_
512
513 #endif // __APB_I2CS_H_
514