1 /*
2 * Copyright (c) 2023 hpmicro
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 *
6 */
7
8 /*
9 * Note:
10 * PY and PZ IOs: if any SOC pin function needs to be routed to these IOs,
11 * besides of IOC, PIOC/BIOC needs to be configured SOC_GPIO_X_xx, so that
12 * expected SoC function can be enabled on these IOs.
13 *
14 */
15 #include "board.h"
16
init_uart_pins(UART_Type * ptr)17 void init_uart_pins(UART_Type *ptr)
18 {
19 if (ptr == HPM_UART0) {
20 HPM_IOC->PAD[IOC_PAD_PA00].FUNC_CTL = IOC_PA00_FUNC_CTL_UART0_TXD;
21 HPM_IOC->PAD[IOC_PAD_PA01].FUNC_CTL = IOC_PA01_FUNC_CTL_UART0_RXD;
22 } else if (ptr == HPM_UART3) {
23 HPM_IOC->PAD[IOC_PAD_PE14].FUNC_CTL = IOC_PE14_FUNC_CTL_UART3_RXD;
24 HPM_IOC->PAD[IOC_PAD_PE15].FUNC_CTL = IOC_PE15_FUNC_CTL_UART3_TXD;
25 } else if (ptr == HPM_PUART) {
26 HPM_PIOC->PAD[IOC_PAD_PY00].FUNC_CTL = PIOC_PY00_FUNC_CTL_PURT_TXD;
27 HPM_PIOC->PAD[IOC_PAD_PY01].FUNC_CTL = PIOC_PY01_FUNC_CTL_PURT_RXD;
28 } else {
29 ;
30 }
31 }
32
33 /* for uart_lin case, need to configure pin as gpio to sent break signal */
init_uart_pin_as_gpio(UART_Type * ptr)34 void init_uart_pin_as_gpio(UART_Type *ptr)
35 {
36 /* pull-up */
37 uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
38
39 if (ptr == HPM_UART3) {
40 HPM_IOC->PAD[IOC_PAD_PE14].PAD_CTL = pad_ctl;
41 HPM_IOC->PAD[IOC_PAD_PE15].PAD_CTL = pad_ctl;
42 HPM_IOC->PAD[IOC_PAD_PE14].FUNC_CTL = IOC_PE14_FUNC_CTL_GPIO_E_14;
43 HPM_IOC->PAD[IOC_PAD_PE15].FUNC_CTL = IOC_PE15_FUNC_CTL_GPIO_E_15;
44 }
45 }
46
init_cap_pins(void)47 void init_cap_pins(void)
48 {
49 /* CAP_INT */
50 HPM_IOC->PAD[IOC_PAD_PY06].PAD_CTL = IOC_PAD_PAD_CTL_PE_MASK;
51 HPM_IOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY06_FUNC_CTL_GPIO_Y_06;
52 HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = PIOC_PY06_FUNC_CTL_SOC_PY_06;
53 /* CAP_RST */
54 HPM_IOC->PAD[IOC_PAD_PY07].PAD_CTL = IOC_PAD_PAD_CTL_PE_MASK;
55 HPM_IOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY07_FUNC_CTL_GPIO_Y_07;
56 HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = PIOC_PY07_FUNC_CTL_SOC_PY_07;
57 }
58
init_i2c_pins_as_gpio(I2C_Type * ptr)59 void init_i2c_pins_as_gpio(I2C_Type *ptr)
60 {
61 if (ptr == HPM_I2C3) {
62 HPM_IOC->PAD[IOC_PAD_PD28].FUNC_CTL = IOC_PD28_FUNC_CTL_GPIO_D_28;
63 HPM_IOC->PAD[IOC_PAD_PD29].FUNC_CTL = IOC_PD29_FUNC_CTL_GPIO_D_29;
64 } else if (ptr == HPM_I2C1) {
65 HPM_IOC->PAD[IOC_PAD_PE12].FUNC_CTL = IOC_PE12_FUNC_CTL_GPIO_E_12;
66 HPM_IOC->PAD[IOC_PAD_PE13].FUNC_CTL = IOC_PE13_FUNC_CTL_GPIO_E_13;
67 } else if (ptr == HPM_I2C0) {
68 HPM_IOC->PAD[IOC_PAD_PF09].FUNC_CTL = IOC_PF09_FUNC_CTL_GPIO_F_09;
69 HPM_IOC->PAD[IOC_PAD_PF08].FUNC_CTL = IOC_PF08_FUNC_CTL_GPIO_F_08;
70 } else {
71 ;
72 }
73 }
74
init_i2c_pins(I2C_Type * ptr)75 void init_i2c_pins(I2C_Type *ptr)
76 {
77 if (ptr == HPM_I2C3) { /* Audio */
78 HPM_IOC->PAD[IOC_PAD_PD28].FUNC_CTL = IOC_PD28_FUNC_CTL_I2C3_SDA
79 | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
80 HPM_IOC->PAD[IOC_PAD_PD29].FUNC_CTL = IOC_PD29_FUNC_CTL_I2C3_SCL
81 | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
82 HPM_IOC->PAD[IOC_PAD_PD28].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK;
83 HPM_IOC->PAD[IOC_PAD_PD29].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK;
84 } else if (ptr == HPM_I2C1) { /* Storage */
85 HPM_IOC->PAD[IOC_PAD_PE12].FUNC_CTL = IOC_PE12_FUNC_CTL_I2C1_SDA
86 | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
87 HPM_IOC->PAD[IOC_PAD_PE13].FUNC_CTL = IOC_PE13_FUNC_CTL_I2C1_SCL
88 | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
89 HPM_IOC->PAD[IOC_PAD_PE12].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK;
90 HPM_IOC->PAD[IOC_PAD_PE13].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK;
91 } else if (ptr == HPM_I2C0) { /* Touch Panel/ Camera */
92 HPM_IOC->PAD[IOC_PAD_PF09].FUNC_CTL = IOC_PF09_FUNC_CTL_I2C0_SDA
93 | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
94 HPM_IOC->PAD[IOC_PAD_PF08].FUNC_CTL = IOC_PF08_FUNC_CTL_I2C0_SCL
95 | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
96 HPM_IOC->PAD[IOC_PAD_PF09].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK;
97 HPM_IOC->PAD[IOC_PAD_PF08].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK;
98 } else {
99 ;
100 }
101 }
102
init_cam_pins(void)103 void init_cam_pins(void)
104 {
105 /* configure rst pin function */
106 HPM_IOC->PAD[IOC_PAD_PA22].FUNC_CTL = IOC_PA22_FUNC_CTL_GPIO_A_22;
107 /* configure pwdn pin function */
108 HPM_PIOC->PAD[IOC_PAD_PA21].FUNC_CTL = IOC_PA21_FUNC_CTL_GPIO_A_21;
109
110 HPM_IOC->PAD[IOC_PAD_PA29].FUNC_CTL = IOC_PA29_FUNC_CTL_CAM0_XCLK;
111 HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PA26_FUNC_CTL_CAM0_PIXCLK;
112 HPM_IOC->PAD[IOC_PAD_PB21].FUNC_CTL = IOC_PB21_FUNC_CTL_CAM0_VSYNC;
113 HPM_IOC->PAD[IOC_PAD_PB20].FUNC_CTL = IOC_PB20_FUNC_CTL_CAM0_HSYNC;
114 HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PA27_FUNC_CTL_CAM0_D_2;
115 HPM_IOC->PAD[IOC_PAD_PA25].FUNC_CTL = IOC_PA25_FUNC_CTL_CAM0_D_3;
116 HPM_IOC->PAD[IOC_PAD_PA23].FUNC_CTL = IOC_PA23_FUNC_CTL_CAM0_D_4;
117 HPM_IOC->PAD[IOC_PAD_PA24].FUNC_CTL = IOC_PA24_FUNC_CTL_CAM0_D_5;
118 HPM_IOC->PAD[IOC_PAD_PB16].FUNC_CTL = IOC_PB16_FUNC_CTL_CAM0_D_6;
119 HPM_IOC->PAD[IOC_PAD_PB17].FUNC_CTL = IOC_PB17_FUNC_CTL_CAM0_D_7;
120 HPM_IOC->PAD[IOC_PAD_PB19].FUNC_CTL = IOC_PB19_FUNC_CTL_CAM0_D_8;
121 HPM_IOC->PAD[IOC_PAD_PB18].FUNC_CTL = IOC_PB18_FUNC_CTL_CAM0_D_9;
122 }
123
init_cam_mipi_csi_pins(void)124 void init_cam_mipi_csi_pins(void)
125 {
126 /* configure rst pin function */
127 HPM_IOC->PAD[IOC_PAD_PB00].FUNC_CTL = IOC_PB00_FUNC_CTL_GPIO_B_00;
128 HPM_IOC->PAD[IOC_PAD_PB00].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK;
129 }
130
init_sdm_pins(void)131 void init_sdm_pins(void)
132 {
133
134 }
135
init_gpio_pins(void)136 void init_gpio_pins(void)
137 {
138 /* configure pad setting: pull enable and pull up, schmitt trigger enable */
139 /* enable schmitt trigger to eliminate jitter of pin used as button */
140 HPM_IOC->PAD[IOC_PAD_PF06].FUNC_CTL = IOC_PF06_FUNC_CTL_GPIO_F_06;
141 HPM_IOC->PAD[IOC_PAD_PF06].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_HYS_MASK | IOC_PAD_PAD_CTL_PRS_SET(11);
142
143 HPM_IOC->PAD[IOC_PAD_PF07].FUNC_CTL = IOC_PF07_FUNC_CTL_GPIO_F_07;
144 HPM_IOC->PAD[IOC_PAD_PF07].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_HYS_MASK | IOC_PAD_PAD_CTL_PRS_SET(11);
145 }
146
init_spi_pins(SPI_Type * ptr)147 void init_spi_pins(SPI_Type *ptr)
148 {
149 if (ptr == HPM_SPI3) {
150 HPM_IOC->PAD[IOC_PAD_PE05].FUNC_CTL = IOC_PE05_FUNC_CTL_SPI3_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1);
151 HPM_IOC->PAD[IOC_PAD_PE06].FUNC_CTL = IOC_PE06_FUNC_CTL_SPI3_MISO;
152 HPM_IOC->PAD[IOC_PAD_PE07].FUNC_CTL = IOC_PE07_FUNC_CTL_SPI3_MOSI;
153 HPM_IOC->PAD[IOC_PAD_PE04].FUNC_CTL = IOC_PE04_FUNC_CTL_SPI3_CS_0;
154 }
155 }
156
init_spi_pins_with_gpio_as_cs(SPI_Type * ptr)157 void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr)
158 {
159 if (ptr == HPM_SPI3) {
160 HPM_IOC->PAD[IOC_PAD_PE05].FUNC_CTL = IOC_PE05_FUNC_CTL_SPI3_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1);
161 HPM_IOC->PAD[IOC_PAD_PE06].FUNC_CTL = IOC_PE06_FUNC_CTL_SPI3_MISO;
162 HPM_IOC->PAD[IOC_PAD_PE07].FUNC_CTL = IOC_PE07_FUNC_CTL_SPI3_MOSI;
163 HPM_IOC->PAD[IOC_PAD_PE04].FUNC_CTL = IOC_PE04_FUNC_CTL_GPIO_E_04;
164 }
165 }
166
init_pins(void)167 void init_pins(void)
168 {
169 #ifdef BOARD_CONSOLE_UART_BASE
170 init_uart_pins(BOARD_CONSOLE_UART_BASE);
171 #endif
172 }
173
init_gptmr_pins(GPTMR_Type * ptr)174 void init_gptmr_pins(GPTMR_Type *ptr)
175 {
176 if (ptr == HPM_GPTMR2) {
177 HPM_IOC->PAD[IOC_PAD_PE22].FUNC_CTL = IOC_PE22_FUNC_CTL_GPTMR2_CAPT_0;
178 HPM_IOC->PAD[IOC_PAD_PE23].FUNC_CTL = IOC_PE23_FUNC_CTL_GPTMR2_COMP_0;
179 HPM_IOC->PAD[IOC_PAD_PE24].FUNC_CTL = IOC_PE24_FUNC_CTL_GPTMR2_COMP_1;
180 }
181 }
182
init_butn_pins(void)183 void init_butn_pins(void)
184 {
185
186 }
187
init_acmp_pins(void)188 void init_acmp_pins(void)
189 {
190
191 }
192
init_sdxc_cmd_pin(SDXC_Type * ptr,bool open_drain,bool is_1v8)193 void init_sdxc_cmd_pin(SDXC_Type *ptr, bool open_drain, bool is_1v8)
194 {
195 (void) is_1v8;
196 /* Pull-up */
197 uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PRS_SET(2) | \
198 IOC_PAD_PAD_CTL_SR_SET(1) | IOC_PAD_PAD_CTL_SPD_SET(3) | IOC_PAD_PAD_CTL_DS_SET(6);
199 if (ptr == HPM_SDXC0) {
200 if (open_drain) {
201 pad_ctl |= IOC_PAD_PAD_CTL_OD_MASK;
202 }
203 HPM_IOC->PAD[IOC_PAD_PC01].FUNC_CTL = IOC_PC01_FUNC_CTL_SDC0_CMD | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1);
204 HPM_IOC->PAD[IOC_PAD_PC01].PAD_CTL = pad_ctl;
205 }
206 if (ptr == HPM_SDXC1) {
207 HPM_IOC->PAD[IOC_PAD_PC13].FUNC_CTL = IOC_PC13_FUNC_CTL_SDC1_CMD | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1);
208 HPM_IOC->PAD[IOC_PAD_PC13].PAD_CTL = pad_ctl;
209 }
210 }
211
212
init_sdxc_ds_pin(SDXC_Type * ptr)213 void init_sdxc_ds_pin(SDXC_Type *ptr)
214 {
215 #define SDXC_DS_PIN_SETTING (IOC_PAD_PAD_CTL_PE_SET(1) \
216 | IOC_PAD_PAD_CTL_SPD_SET(3) \
217 | IOC_PAD_PAD_CTL_SR_SET(1))
218 if (ptr == HPM_SDXC0) {
219 HPM_IOC->PAD[IOC_PAD_PC00].FUNC_CTL = IOC_PC00_FUNC_CTL_SDC0_DS;
220 HPM_IOC->PAD[IOC_PAD_PC00].PAD_CTL = SDXC_DS_PIN_SETTING;
221 }
222 }
223
init_sdxc_pwr_pin(SDXC_Type * ptr,bool as_gpio)224 void init_sdxc_pwr_pin(SDXC_Type *ptr, bool as_gpio)
225 {
226 if (ptr == HPM_SDXC1) {
227 if (as_gpio) {
228 /* SD_PWR */
229 HPM_IOC->PAD[IOC_PAD_PD07].FUNC_CTL = IOC_PD07_FUNC_CTL_GPIO_D_07;
230 HPM_IOC->PAD[IOC_PAD_PD07].PAD_CTL =
231 IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_DS_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
232 HPM_GPIO0->OE[GPIO_OE_GPIOD].SET = 1UL << 7;
233 }
234 }
235 }
236
init_sdxc_vsel_pin(SDXC_Type * ptr,bool as_gpio)237 void init_sdxc_vsel_pin(SDXC_Type *ptr, bool as_gpio)
238 {
239 if (ptr == HPM_SDXC1) {
240 if (as_gpio) {
241 /* VSEL */
242 HPM_IOC->PAD[IOC_PAD_PD12].FUNC_CTL = IOC_PD12_FUNC_CTL_GPIO_D_12;
243 HPM_IOC->PAD[IOC_PAD_PD12].PAD_CTL =
244 IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_DS_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
245 HPM_GPIO0->OE[GPIO_OE_GPIOD].SET = 1UL << 12;
246 }
247 }
248 }
249
init_sdxc_cd_pin(SDXC_Type * ptr,bool as_gpio)250 void init_sdxc_cd_pin(SDXC_Type *ptr, bool as_gpio)
251 {
252 if (ptr == HPM_SDXC1) {
253 if (as_gpio) {
254 /* CDN */
255 HPM_IOC->PAD[IOC_PAD_PD05].FUNC_CTL = IOC_PD05_FUNC_CTL_GPIO_D_05;
256 HPM_IOC->PAD[IOC_PAD_PD05].PAD_CTL =
257 IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_DS_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
258 HPM_GPIO0->OE[GPIO_OE_GPIOD].CLEAR = 1UL << 5;
259 }
260 }
261 }
262
init_sdxc_clk_data_pins(SDXC_Type * ptr,uint32_t width,bool is_1v8)263 void init_sdxc_clk_data_pins(SDXC_Type *ptr, uint32_t width, bool is_1v8)
264 {
265 (void) is_1v8;
266 #define SDXC_PIN_SETTING_COMMON (IOC_PAD_PAD_CTL_PE_SET(1) \
267 | IOC_PAD_PAD_CTL_SPD_SET(3) \
268 | IOC_PAD_PAD_CTL_SR_SET(1))
269 #define SDXC_PIN_SETTING (IOC_PAD_PAD_CTL_DS_SET(7) \
270 | SDXC_PIN_SETTING_COMMON \
271 | IOC_PAD_PAD_CTL_PS_SET(1) \
272 | IOC_PAD_PAD_CTL_PRS_SET(3))
273
274 uint32_t pad_ctl = SDXC_PIN_SETTING;
275 if (ptr == HPM_SDXC0) {
276 /*CLK*/
277 HPM_IOC->PAD[IOC_PAD_PC02].FUNC_CTL = IOC_PC02_FUNC_CTL_SDC0_CLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1);
278 HPM_IOC->PAD[IOC_PAD_PC02].PAD_CTL = pad_ctl;
279
280 /* DAT0-DATA7 */
281 HPM_IOC->PAD[IOC_PAD_PC06].FUNC_CTL = IOC_PC06_FUNC_CTL_SDC0_DATA_0;
282 HPM_IOC->PAD[IOC_PAD_PC06].PAD_CTL = pad_ctl;
283 if ((width == 4) || (width == 8)) {
284 HPM_IOC->PAD[IOC_PAD_PC03].FUNC_CTL = IOC_PC03_FUNC_CTL_SDC0_DATA_1;
285 HPM_IOC->PAD[IOC_PAD_PC03].PAD_CTL = pad_ctl;
286 HPM_IOC->PAD[IOC_PAD_PC04].FUNC_CTL = IOC_PC04_FUNC_CTL_SDC0_DATA_2;
287 HPM_IOC->PAD[IOC_PAD_PC04].PAD_CTL = pad_ctl;
288 HPM_IOC->PAD[IOC_PAD_PC05].FUNC_CTL = IOC_PC05_FUNC_CTL_SDC0_DATA_3;
289 HPM_IOC->PAD[IOC_PAD_PC05].PAD_CTL = pad_ctl;
290 }
291 if (width == 8) {
292 HPM_IOC->PAD[IOC_PAD_PC08].FUNC_CTL = IOC_PC08_FUNC_CTL_SDC0_DATA_4;
293 HPM_IOC->PAD[IOC_PAD_PC08].PAD_CTL = pad_ctl;
294 HPM_IOC->PAD[IOC_PAD_PC09].FUNC_CTL = IOC_PC09_FUNC_CTL_SDC0_DATA_5;
295 HPM_IOC->PAD[IOC_PAD_PC09].PAD_CTL = pad_ctl;
296 HPM_IOC->PAD[IOC_PAD_PC10].FUNC_CTL = IOC_PC10_FUNC_CTL_SDC0_DATA_6;
297 HPM_IOC->PAD[IOC_PAD_PC10].PAD_CTL = pad_ctl;
298 HPM_IOC->PAD[IOC_PAD_PC11].FUNC_CTL = IOC_PC11_FUNC_CTL_SDC0_DATA_7;
299 HPM_IOC->PAD[IOC_PAD_PC11].PAD_CTL = pad_ctl;
300 }
301 }
302 if (ptr == HPM_SDXC1) {
303 /*CLK*/
304 HPM_IOC->PAD[IOC_PAD_PC16].FUNC_CTL = IOC_PC16_FUNC_CTL_SDC1_CLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1);
305 HPM_IOC->PAD[IOC_PAD_PC16].PAD_CTL = pad_ctl;
306
307 /* DAT0 -DATA3 */
308 HPM_IOC->PAD[IOC_PAD_PC17].FUNC_CTL = IOC_PC17_FUNC_CTL_SDC1_DATA_0;
309 HPM_IOC->PAD[IOC_PAD_PC17].PAD_CTL = pad_ctl;
310 HPM_IOC->PAD[IOC_PAD_PC15].FUNC_CTL = IOC_PC15_FUNC_CTL_SDC1_DATA_1;
311 HPM_IOC->PAD[IOC_PAD_PC15].PAD_CTL = pad_ctl;
312 HPM_IOC->PAD[IOC_PAD_PC14].FUNC_CTL = IOC_PC14_FUNC_CTL_SDC1_DATA_2;
313 HPM_IOC->PAD[IOC_PAD_PC14].PAD_CTL = pad_ctl;
314 HPM_IOC->PAD[IOC_PAD_PC12].FUNC_CTL = IOC_PC12_FUNC_CTL_SDC1_DATA_3;
315 HPM_IOC->PAD[IOC_PAD_PC12].PAD_CTL = pad_ctl;
316 }
317 }
318
319
320
init_usb_pins(void)321 void init_usb_pins(void)
322 {
323 /* USB0_ID */
324 HPM_IOC->PAD[IOC_PAD_PF04].FUNC_CTL = IOC_PF04_FUNC_CTL_USB0_ID;
325 /* USB0_OC */
326 HPM_IOC->PAD[IOC_PAD_PF03].FUNC_CTL = IOC_PF03_FUNC_CTL_USB0_OC;
327 /* USB0_PWR */
328 HPM_IOC->PAD[IOC_PAD_PF00].FUNC_CTL = IOC_PF00_FUNC_CTL_USB0_PWR;
329 }
330
init_can_pins(MCAN_Type * ptr)331 void init_can_pins(MCAN_Type *ptr)
332 {
333 if (ptr == HPM_MCAN3) {
334 HPM_IOC->PAD[IOC_PAD_PD15].FUNC_CTL = IOC_PD15_FUNC_CTL_MCAN3_TXD;
335 HPM_IOC->PAD[IOC_PAD_PD14].FUNC_CTL = IOC_PD14_FUNC_CTL_MCAN3_RXD;
336 HPM_IOC->PAD[IOC_PAD_PD13].FUNC_CTL = IOC_PD13_FUNC_CTL_MCAN3_STBY;
337 }
338 }
339
init_clk_obs_pins(void)340 void init_clk_obs_pins(void)
341 {
342 /* HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PB02_FUNC_CTL_SYSCTL_CLK_OBS_0; */
343 }
344
init_led_pins_as_gpio(void)345 void init_led_pins_as_gpio(void)
346 {
347 HPM_IOC->PAD[IOC_PAD_PF01].FUNC_CTL = IOC_PF01_FUNC_CTL_GPIO_F_01;
348 HPM_IOC->PAD[IOC_PAD_PF02].FUNC_CTL = IOC_PF02_FUNC_CTL_GPIO_F_02;
349 HPM_IOC->PAD[IOC_PAD_PF05].FUNC_CTL = IOC_PF05_FUNC_CTL_GPIO_F_05;
350 }
351
init_mipi_lvds_tx_phy0_pin(void)352 void init_mipi_lvds_tx_phy0_pin(void)
353 {
354 HPM_IOC->PAD[IOC_PAD_PB04].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
355 HPM_IOC->PAD[IOC_PAD_PB05].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
356 HPM_IOC->PAD[IOC_PAD_PB06].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
357 HPM_IOC->PAD[IOC_PAD_PB07].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
358 HPM_IOC->PAD[IOC_PAD_PB08].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
359 HPM_IOC->PAD[IOC_PAD_PB09].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
360 HPM_IOC->PAD[IOC_PAD_PB10].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
361 HPM_IOC->PAD[IOC_PAD_PB11].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
362 HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
363 HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
364 HPM_IOC->PAD[IOC_PAD_PB14].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /*REXT*/
365 }
366
init_mipi_lvds_tx_phy1_pin(void)367 void init_mipi_lvds_tx_phy1_pin(void)
368 {
369 HPM_IOC->PAD[IOC_PAD_PB22].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
370 HPM_IOC->PAD[IOC_PAD_PB23].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
371 HPM_IOC->PAD[IOC_PAD_PB24].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
372 HPM_IOC->PAD[IOC_PAD_PB25].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
373 HPM_IOC->PAD[IOC_PAD_PB26].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
374 HPM_IOC->PAD[IOC_PAD_PB27].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
375 HPM_IOC->PAD[IOC_PAD_PB28].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
376 HPM_IOC->PAD[IOC_PAD_PB29].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
377 HPM_IOC->PAD[IOC_PAD_PB30].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
378 HPM_IOC->PAD[IOC_PAD_PB31].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
379 HPM_IOC->PAD[IOC_PAD_PB15].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /*REXT*/
380 }
381
init_mipi_lvds_rx_phy0_pin(void)382 void init_mipi_lvds_rx_phy0_pin(void)
383 {
384 HPM_IOC->PAD[IOC_PAD_PA30].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
385 HPM_IOC->PAD[IOC_PAD_PA31].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
386 HPM_IOC->PAD[IOC_PAD_PB00].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
387 HPM_IOC->PAD[IOC_PAD_PB01].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
388 HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
389 HPM_IOC->PAD[IOC_PAD_PB03].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
390 HPM_IOC->PAD[IOC_PAD_PA28].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /*REXT*/
391 }
392
init_mipi_lvds_rx_phy1_pin(void)393 void init_mipi_lvds_rx_phy1_pin(void)
394 {
395 HPM_IOC->PAD[IOC_PAD_PB16].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
396 HPM_IOC->PAD[IOC_PAD_PB17].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
397 HPM_IOC->PAD[IOC_PAD_PB18].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
398 HPM_IOC->PAD[IOC_PAD_PB19].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
399 HPM_IOC->PAD[IOC_PAD_PB20].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
400 HPM_IOC->PAD[IOC_PAD_PB21].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
401 HPM_IOC->PAD[IOC_PAD_PA29].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /*REXT*/
402 }
403
init_lcd_mipi_ctl_pins(void)404 void init_lcd_mipi_ctl_pins(void)
405 {
406 /* RESET */
407 HPM_IOC->PAD[IOC_PAD_PB01].FUNC_CTL = IOC_PB01_FUNC_CTL_GPIO_B_01;
408 }
409
init_lcd_lvds_double_ctl_pins(void)410 void init_lcd_lvds_double_ctl_pins(void)
411 {
412 /* RESET */
413 HPM_IOC->PAD[IOC_PAD_PA31].FUNC_CTL = IOC_PA31_FUNC_CTL_GPIO_A_31;
414 }
415
init_lcd_lvds_single_ctl_pins(void)416 void init_lcd_lvds_single_ctl_pins(void)
417 {
418 /* LED-EN */
419 HPM_IOC->PAD[IOC_PAD_PA30].FUNC_CTL = IOC_PA30_FUNC_CTL_GPIO_A_30;
420
421 /* PWM */
422 HPM_IOC->PAD[IOC_PAD_PA31].FUNC_CTL = IOC_PA31_FUNC_CTL_GPIO_A_31;
423 }
424
init_lcd_rgb_ctl_pins(void)425 void init_lcd_rgb_ctl_pins(void)
426 {
427 /* PWM */
428 HPM_IOC->PAD[IOC_PAD_PA09].FUNC_CTL = IOC_PA09_FUNC_CTL_GPIO_A_09;
429 /* RST */
430 HPM_IOC->PAD[IOC_PAD_PA14].FUNC_CTL = IOC_PA14_FUNC_CTL_GPIO_A_14;
431
432 HPM_IOC->PAD[IOC_PAD_PY05].PAD_CTL = IOC_PAD_PAD_CTL_PE_MASK;
433 HPM_IOC->PAD[IOC_PAD_PY05].FUNC_CTL = IOC_PY05_FUNC_CTL_GPIO_Y_05;
434 HPM_PIOC->PAD[IOC_PAD_PY05].FUNC_CTL = PIOC_PY05_FUNC_CTL_SOC_PY_05;
435 }
436
init_lcd_rgb_pins(void)437 void init_lcd_rgb_pins(void)
438 {
439 HPM_IOC->PAD[IOC_PAD_PA10].FUNC_CTL = IOC_PA10_FUNC_CTL_DIS0_G_4;
440 HPM_IOC->PAD[IOC_PAD_PA11].FUNC_CTL = IOC_PA11_FUNC_CTL_DIS0_G_3;
441 HPM_IOC->PAD[IOC_PAD_PA12].FUNC_CTL = IOC_PA12_FUNC_CTL_DIS0_G_6;
442 HPM_IOC->PAD[IOC_PAD_PA13].FUNC_CTL = IOC_PA13_FUNC_CTL_DIS0_G_5;
443 HPM_IOC->PAD[IOC_PAD_PA15].FUNC_CTL = IOC_PA15_FUNC_CTL_DIS0_R_3;
444 HPM_IOC->PAD[IOC_PAD_PA16].FUNC_CTL = IOC_PA16_FUNC_CTL_DIS0_R_5;
445 HPM_IOC->PAD[IOC_PAD_PA17].FUNC_CTL = IOC_PA17_FUNC_CTL_DIS0_R_4;
446 HPM_IOC->PAD[IOC_PAD_PA18].FUNC_CTL = IOC_PA18_FUNC_CTL_DIS0_R_7;
447 HPM_IOC->PAD[IOC_PAD_PA19].FUNC_CTL = IOC_PA19_FUNC_CTL_DIS0_R_6;
448 HPM_IOC->PAD[IOC_PAD_PA20].FUNC_CTL = IOC_PA20_FUNC_CTL_DIS0_G_2;
449 HPM_IOC->PAD[IOC_PAD_PA28].FUNC_CTL = IOC_PA28_FUNC_CTL_DIS0_R_0;
450 HPM_IOC->PAD[IOC_PAD_PA30].FUNC_CTL = IOC_PA30_FUNC_CTL_DIS0_R_2;
451 HPM_IOC->PAD[IOC_PAD_PA31].FUNC_CTL = IOC_PA31_FUNC_CTL_DIS0_R_1;
452
453 HPM_IOC->PAD[IOC_PAD_PB00].FUNC_CTL = IOC_PB00_FUNC_CTL_DIS0_G_1;
454 HPM_IOC->PAD[IOC_PAD_PB01].FUNC_CTL = IOC_PB01_FUNC_CTL_DIS0_G_0;
455 HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PB02_FUNC_CTL_DIS0_B_1;
456 HPM_IOC->PAD[IOC_PAD_PB03].FUNC_CTL = IOC_PB03_FUNC_CTL_DIS0_B_0;
457 HPM_IOC->PAD[IOC_PAD_PB04].FUNC_CTL = IOC_PB04_FUNC_CTL_DIS0_B_2;
458 HPM_IOC->PAD[IOC_PAD_PB05].FUNC_CTL = IOC_PB05_FUNC_CTL_DIS0_G_7;
459 HPM_IOC->PAD[IOC_PAD_PB06].FUNC_CTL = IOC_PB06_FUNC_CTL_DIS0_B_3;
460 HPM_IOC->PAD[IOC_PAD_PB07].FUNC_CTL = IOC_PB07_FUNC_CTL_DIS0_B_4;
461 HPM_IOC->PAD[IOC_PAD_PB08].FUNC_CTL = IOC_PB08_FUNC_CTL_DIS0_B_6;
462 HPM_IOC->PAD[IOC_PAD_PB09].FUNC_CTL = IOC_PB09_FUNC_CTL_DIS0_B_5;
463 HPM_IOC->PAD[IOC_PAD_PB10].FUNC_CTL = IOC_PB10_FUNC_CTL_DIS0_EN;
464 HPM_IOC->PAD[IOC_PAD_PB11].FUNC_CTL = IOC_PB11_FUNC_CTL_DIS0_B_7;
465 HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PB12_FUNC_CTL_DIS0_HSYNC;
466 HPM_IOC->PAD[IOC_PAD_PB14].FUNC_CTL = IOC_PB14_FUNC_CTL_DIS0_VSYNC;
467
468 HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PB13_FUNC_CTL_DIS0_CLK; /*A.CLK*/
469 }
470
init_i2s_pins(I2S_Type * ptr)471 void init_i2s_pins(I2S_Type *ptr)
472 {
473 if (ptr == HPM_I2S3) {
474 HPM_IOC->PAD[IOC_PAD_PD30].FUNC_CTL = IOC_PD30_FUNC_CTL_I2S3_MCLK;
475 HPM_IOC->PAD[IOC_PAD_PD24].FUNC_CTL = IOC_PD24_FUNC_CTL_I2S3_BCLK;
476 HPM_IOC->PAD[IOC_PAD_PD25].FUNC_CTL = IOC_PD25_FUNC_CTL_I2S3_FCLK;
477 HPM_IOC->PAD[IOC_PAD_PD27].FUNC_CTL = IOC_PD27_FUNC_CTL_I2S3_TXD_2;
478 HPM_IOC->PAD[IOC_PAD_PD23].FUNC_CTL = IOC_PD23_FUNC_CTL_I2S3_RXD_2;
479 }
480 }
481
init_dao_pins(void)482 void init_dao_pins(void)
483 {
484 HPM_IOC->PAD[IOC_PAD_PC31].FUNC_CTL = IOC_PC31_FUNC_CTL_DAO_LP;
485 HPM_IOC->PAD[IOC_PAD_PC30].FUNC_CTL = IOC_PC30_FUNC_CTL_DAO_LN;
486 HPM_IOC->PAD[IOC_PAD_PD01].FUNC_CTL = IOC_PD01_FUNC_CTL_DAO_RP;
487 HPM_IOC->PAD[IOC_PAD_PD00].FUNC_CTL = IOC_PD00_FUNC_CTL_DAO_RN;
488 }
489
init_pdm_pins(void)490 void init_pdm_pins(void)
491 {
492 HPM_IOC->PAD[IOC_PAD_PE00].FUNC_CTL = IOC_PE00_FUNC_CTL_PDM0_CLK;
493 HPM_IOC->PAD[IOC_PAD_PE01].FUNC_CTL = IOC_PE01_FUNC_CTL_PDM0_D_1;
494 }
495
init_enet_pins(ENET_Type * ptr)496 void init_enet_pins(ENET_Type *ptr)
497 {
498 if (ptr == HPM_ENET0) {
499 HPM_IOC->PAD[IOC_PAD_PD18].FUNC_CTL = IOC_PD18_FUNC_CTL_GPIO_D_18;
500
501 HPM_IOC->PAD[IOC_PAD_PD02].FUNC_CTL = IOC_PD02_FUNC_CTL_ETH0_MDC;
502 HPM_IOC->PAD[IOC_PAD_PD03].FUNC_CTL = IOC_PD03_FUNC_CTL_ETH0_MDIO;
503
504 HPM_IOC->PAD[IOC_PAD_PC29].FUNC_CTL = IOC_PC29_FUNC_CTL_ETH0_RXD_0;
505 HPM_IOC->PAD[IOC_PAD_PC28].FUNC_CTL = IOC_PC28_FUNC_CTL_ETH0_RXD_1;
506 HPM_IOC->PAD[IOC_PAD_PC24].FUNC_CTL = IOC_PC24_FUNC_CTL_ETH0_RXD_2;
507 HPM_IOC->PAD[IOC_PAD_PC25].FUNC_CTL = IOC_PC25_FUNC_CTL_ETH0_RXD_3;
508 HPM_IOC->PAD[IOC_PAD_PC26].FUNC_CTL = IOC_PC26_FUNC_CTL_ETH0_RXCK;
509 HPM_IOC->PAD[IOC_PAD_PC27].FUNC_CTL = IOC_PC27_FUNC_CTL_ETH0_RXDV;
510
511 HPM_IOC->PAD[IOC_PAD_PC22].FUNC_CTL = IOC_PC22_FUNC_CTL_ETH0_TXD_0;
512 HPM_IOC->PAD[IOC_PAD_PC23].FUNC_CTL = IOC_PC23_FUNC_CTL_ETH0_TXD_1;
513 HPM_IOC->PAD[IOC_PAD_PC19].FUNC_CTL = IOC_PC19_FUNC_CTL_ETH0_TXD_2;
514 HPM_IOC->PAD[IOC_PAD_PC18].FUNC_CTL = IOC_PC18_FUNC_CTL_ETH0_TXD_3;
515 HPM_IOC->PAD[IOC_PAD_PC20].FUNC_CTL = IOC_PC20_FUNC_CTL_ETH0_TXCK;
516 HPM_IOC->PAD[IOC_PAD_PC21].FUNC_CTL = IOC_PC21_FUNC_CTL_ETH0_TXEN;
517 }
518 }
519
init_enet_pps_pins(void)520 void init_enet_pps_pins(void)
521 {
522 HPM_IOC->PAD[IOC_PAD_PD31].FUNC_CTL = IOC_PD31_FUNC_CTL_ETH0_EVTO_0;
523 }
524
init_adc_pins(void)525 void init_adc_pins(void)
526 {
527 HPM_IOC->PAD[IOC_PAD_PE16].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
528 HPM_IOC->PAD[IOC_PAD_PE17].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
529 HPM_IOC->PAD[IOC_PAD_PE18].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
530 HPM_IOC->PAD[IOC_PAD_PE19].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
531 HPM_IOC->PAD[IOC_PAD_PE21].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
532 HPM_IOC->PAD[IOC_PAD_PE22].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
533 HPM_IOC->PAD[IOC_PAD_PE23].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
534 HPM_IOC->PAD[IOC_PAD_PE24].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
535 HPM_IOC->PAD[IOC_PAD_PE25].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
536 HPM_IOC->PAD[IOC_PAD_PE26].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
537 HPM_IOC->PAD[IOC_PAD_PE27].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
538 HPM_IOC->PAD[IOC_PAD_PE28].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
539 HPM_IOC->PAD[IOC_PAD_PE29].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
540 HPM_IOC->PAD[IOC_PAD_PE30].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
541 HPM_IOC->PAD[IOC_PAD_PE31].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
542 }
543
init_tamper_pins(void)544 void init_tamper_pins(void)
545 {
546 HPM_BIOC->PAD[IOC_PAD_PZ04].FUNC_CTL = BIOC_PZ04_FUNC_CTL_TAMP_PZ_04 | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
547 HPM_BIOC->PAD[IOC_PAD_PZ05].FUNC_CTL = BIOC_PZ05_FUNC_CTL_TAMP_PZ_05;
548 HPM_BIOC->PAD[IOC_PAD_PZ06].FUNC_CTL = BIOC_PZ06_FUNC_CTL_TAMP_PZ_06;
549 }
550