1 /* 2 * Copyright (c) 2006-2021, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2018-05-25 RT-Thread the first version 9 */ 10 11 #ifndef __DRV_PL041_H__ 12 #define __DRV_PL041_H__ 13 14 #define PL041_BASE_ADDR (0x10004000) 15 16 /* offsets in CTRL_CH */ 17 #define AACI_RXCR 0x00 /* 29 bits Control Rx FIFO */ 18 #define AACI_TXCR 0x04 /* 17 bits Control Tx FIFO */ 19 #define AACI_SR 0x08 /* 12 bits Status */ 20 #define AACI_ISR 0x0C /* 7 bits Int Status */ 21 #define AACI_IE 0x10 /* 7 bits Int Enable */ 22 23 /* both for AACI_RXCR and AACI_TXCR */ 24 #define AACI_CR_FEN (1 << 16) /* fifo enable */ 25 #define AACI_CR_COMPACT (1 << 15) /* compact mode */ 26 #define AACI_CR_SZ16 (0 << 13) /* 16 bits */ 27 #define AACI_CR_SZ18 (1 << 13) /* 18 bits */ 28 #define AACI_CR_SZ20 (2 << 13) /* 20 bits */ 29 #define AACI_CR_SZ12 (3 << 13) /* 12 bits */ 30 #define AACI_CR_SL12 (1 << 12) 31 #define AACI_CR_SL11 (1 << 11) 32 #define AACI_CR_SL10 (1 << 10) 33 #define AACI_CR_SL9 (1 << 9) 34 #define AACI_CR_SL8 (1 << 8) 35 #define AACI_CR_SL7 (1 << 7) 36 #define AACI_CR_SL6 (1 << 6) 37 #define AACI_CR_SL5 (1 << 5) 38 #define AACI_CR_SL4 (1 << 4) 39 #define AACI_CR_SL3 (1 << 3) 40 #define AACI_CR_SL2 (1 << 2) 41 #define AACI_CR_SL1 (1 << 1) 42 #define AACI_CR_EN (1 << 0) /* receive enable */ 43 44 /* status register bits */ 45 #define AACI_SR_RXTOFE (1 << 11) /* rx timeout fifo empty */ 46 #define AACI_SR_TXTO (1 << 10) /* rx timeout fifo nonempty */ 47 #define AACI_SR_TXU (1 << 9) /* tx underrun */ 48 #define AACI_SR_RXO (1 << 8) /* rx overrun */ 49 #define AACI_SR_TXB (1 << 7) /* tx busy */ 50 #define AACI_SR_RXB (1 << 6) /* rx busy */ 51 #define AACI_SR_TXFF (1 << 5) /* tx fifo full */ 52 #define AACI_SR_RXFF (1 << 4) /* rx fifo full */ 53 #define AACI_SR_TXHE (1 << 3) /* tx fifo half empty */ 54 #define AACI_SR_RXHF (1 << 2) /* rx fifo half full */ 55 #define AACI_SR_TXFE (1 << 1) /* tx fifo empty */ 56 #define AACI_SR_RXFE (1 << 0) /* rx fifo empty */ 57 58 #define AACI_ISR_RXTOFEINTR (1 << 6) /* rx fifo empty */ 59 #define AACI_ISR_URINTR (1 << 5) /* tx underflow */ 60 #define AACI_ISR_ORINTR (1 << 4) /* rx overflow */ 61 #define AACI_ISR_RXINTR (1 << 3) /* rx fifo */ 62 #define AACI_ISR_TXINTR (1 << 2) /* tx fifo intr */ 63 #define AACI_ISR_RXTOINTR (1 << 1) /* rx timeout */ 64 #define AACI_ISR_TXCINTR (1 << 0) /* tx complete */ 65 66 /* interrupt enable */ 67 #define AACI_IE_RXTOIE (1 << 6) /*rx timeout interrupt enable*/ 68 #define AACI_IE_URIE (1 << 5) /*Transmit underrun interrupt enable*/ 69 #define AACI_IE_ORIE (1 << 4) /*Overrun receive interrupt enable*/ 70 #define AACI_IE_RXIE (1 << 3) /*Receive interrupt enable*/ 71 #define AACI_IE_TXIE (1 << 2) /*Transmit interrupt enable*/ 72 #define AACI_IE_RXTIE (1 << 1) /*Receive timeout interrupt enable*/ 73 #define AACI_IE_TXCIE (1 << 0) /*Transmit complete interrupt enable*/ 74 75 /* interrupt status */ 76 #define AACI_ISR_RXTOFE (1 << 6) /* rx timeout fifo empty */ 77 #define AACI_ISR_UR (1 << 5) /* tx fifo underrun */ 78 #define AACI_ISR_OR (1 << 4) /* rx fifo overrun */ 79 #define AACI_ISR_RX (1 << 3) /* rx interrupt status */ 80 #define AACI_ISR_TX (1 << 2) /* tx interrupt status */ 81 #define AACI_ISR_RXTO (1 << 1) /* rx timeout */ 82 #define AACI_ISR_TXC (1 << 0) /* tx complete */ 83 84 /* interrupt enable */ 85 #define AACI_IE_RXTOFE (1 << 6) /* rx timeout fifo empty */ 86 #define AACI_IE_UR (1 << 5) /* tx fifo underrun */ 87 #define AACI_IE_OR (1 << 4) /* rx fifo overrun */ 88 #define AACI_IE_RX (1 << 3) /* rx interrupt status */ 89 #define AACI_IE_TX (1 << 2) /* tx interrupt status */ 90 #define AACI_IE_RXTO (1 << 1) /* rx timeout */ 91 #define AACI_IE_TXC (1 << 0) /* tx complete */ 92 93 /* slot flag register bits */ 94 #define AACI_SLFR_RWIS (1 << 13) /* raw wake-up interrupt status */ 95 #define AACI_SLFR_RGPIOINTR (1 << 12) /* raw gpio interrupt */ 96 #define AACI_SLFR_12TXE (1 << 11) /* slot 12 tx empty */ 97 #define AACI_SLFR_12RXV (1 << 10) /* slot 12 rx valid */ 98 #define AACI_SLFR_2TXE (1 << 9) /* slot 2 tx empty */ 99 #define AACI_SLFR_2RXV (1 << 8) /* slot 2 rx valid */ 100 #define AACI_SLFR_1TXE (1 << 7) /* slot 1 tx empty */ 101 #define AACI_SLFR_1RXV (1 << 6) /* slot 1 rx valid */ 102 #define AACI_SLFR_12TXB (1 << 5) /* slot 12 tx busy */ 103 #define AACI_SLFR_12RXB (1 << 4) /* slot 12 rx busy */ 104 #define AACI_SLFR_2TXB (1 << 3) /* slot 2 tx busy */ 105 #define AACI_SLFR_2RXB (1 << 2) /* slot 2 rx busy */ 106 #define AACI_SLFR_1TXB (1 << 1) /* slot 1 tx busy */ 107 #define AACI_SLFR_1RXB (1 << 0) /* slot 1 rx busy */ 108 109 /* Interrupt clear register */ 110 #define AACI_ICLR_RXTOFEC4 (1 << 12) /* Receive timeout FIFO empty clear */ 111 #define AACI_ICLR_RXTOFEC3 (1 << 11) /* Receive timeout FIFO empty clear */ 112 #define AACI_ICLR_RXTOFEC2 (1 << 10) /* Receive timeout FIFO empty clear */ 113 #define AACI_ICLR_RXTOFEC1 (1 << 9) /* Receive timeout FIFO empty clear */ 114 #define AACI_ICLR_TXUEC4 (1 << 8) /* Transmit underrun error clear */ 115 #define AACI_ICLR_TXUEC3 (1 << 7) /* Transmit underrun error clear */ 116 #define AACI_ICLR_TXUEC2 (1 << 6) /* Transmit underrun error clear*/ 117 #define AACI_ICLR_TXUEC1 (1 << 5) /* Transmit underrun error clear */ 118 #define AACI_ICLR_RXOEC4 (1 << 4) /* Receive overrun error clear */ 119 #define AACI_ICLR_RXOEC3 (1 << 3) /* Receive overrun error clear */ 120 #define AACI_ICLR_RXOEC2 (1 << 2) /* Receive overrun error clear */ 121 #define AACI_ICLR_RXOEC1 (1 << 1) /* Receive overrun error clear */ 122 #define AACI_ICLR_WISC (1 << 0) /* Wake-up interrupt status clear */ 123 124 /* Main control register bits AACI_MAINCR */ 125 #define AACI_MAINCR_SCRA(x) ((x) << 10) /* secondary codec reg access */ 126 #define AACI_MAINCR_DMAEN (1 << 9) /* dma enable */ 127 #define AACI_MAINCR_SL12TXEN (1 << 8) /* slot 12 transmit enable */ 128 #define AACI_MAINCR_SL12RXEN (1 << 7) /* slot 12 receive enable */ 129 #define AACI_MAINCR_SL2TXEN (1 << 6) /* slot 2 transmit enable */ 130 #define AACI_MAINCR_SL2RXEN (1 << 5) /* slot 2 receive enable */ 131 #define AACI_MAINCR_SL1TXEN (1 << 4) /* slot 1 transmit enable */ 132 #define AACI_MAINCR_SL1RXEN (1 << 3) /* slot 1 receive enable */ 133 #define AACI_MAINCR_LPM (1 << 2) /* low power mode */ 134 #define AACI_MAINCR_LOOPBK (1 << 1) /* loopback */ 135 #define AACI_MAINCR_IE (1 << 0) /* aaci interface enable */ 136 137 /* Reset register bits. P65 */ 138 #define RESET_NRST (1 << 0) 139 140 /* Sync register bits. P65 */ 141 #define SYNC_FORCE (1 << 0) 142 143 /* Main flag register bits. P66 */ 144 #define MAINFR_TXB (1 << 1) /* transmit busy */ 145 #define MAINFR_RXB (1 << 0) /* receive busy */ 146 147 #define PL041_CHANNEL_LEFT_DAC (0x1 << 3) 148 #define PL041_CHANNEL_RIGHT_DAC (0x1 << 3) 149 #define PL041_CHANNEL_LEFT_ADC (0x1 << 3) 150 #define PL041_CHANNEL_RIGHT_ADC (0x1 << 3) 151 152 struct reg_pl041 153 { 154 volatile rt_uint32_t rxcr1; /* 0x000 */ 155 volatile rt_uint32_t txcr1; /* 0x004 */ 156 volatile rt_uint32_t sr1; /* 0x008 */ 157 volatile rt_uint32_t isr1; /* 0x00c */ 158 volatile rt_uint32_t iie1; /* 0x010 */ 159 volatile rt_uint32_t rxcr2; /* 0x014 */ 160 volatile rt_uint32_t txcr2; /* 0x018 */ 161 volatile rt_uint32_t sr2; /* 0x01c */ 162 volatile rt_uint32_t isr2; /* 0x020 */ 163 volatile rt_uint32_t iie2; /* 0x024 */ 164 volatile rt_uint32_t rxcr3; /* 0x028 */ 165 volatile rt_uint32_t txcr3; /* 0x02c */ 166 volatile rt_uint32_t sr3; /* 0x030 */ 167 volatile rt_uint32_t isr3; /* 0x034 */ 168 volatile rt_uint32_t iie3; /* 0x038 */ 169 volatile rt_uint32_t rxcr4; /* 0x03c */ 170 volatile rt_uint32_t txcr4; /* 0x040 */ 171 volatile rt_uint32_t sr4; /* 0x044 */ 172 volatile rt_uint32_t isr4; /* 0x048 */ 173 volatile rt_uint32_t iie4; /* 0x04c */ 174 volatile rt_uint32_t sl1rx; /* 0x050 */ 175 volatile rt_uint32_t sl1tx; /* 0x054 */ 176 volatile rt_uint32_t sl2rx; /* 0x058 */ 177 volatile rt_uint32_t sl2tx; /* 0x05c */ 178 volatile rt_uint32_t sl12rx; /* 0x060 */ 179 volatile rt_uint32_t sl12tx; /* 0x064 */ 180 volatile rt_uint32_t slfr; /* 0x068 */ 181 volatile rt_uint32_t slistat; /* 0x06c */ 182 volatile rt_uint32_t slien; /* 0x070 */ 183 volatile rt_uint32_t intclr; /* 0x074 */ 184 volatile rt_uint32_t maincr; /* 0x078 */ 185 volatile rt_uint32_t reset; /* 0x07c */ 186 volatile rt_uint32_t sync; /* 0x080 */ 187 volatile rt_uint32_t allints; /* 0x084 */ 188 volatile rt_uint32_t mainfr; /* 0x088 */ 189 volatile rt_uint32_t res08c; 190 volatile rt_uint32_t dr1[8]; /* 0x090 */ 191 volatile rt_uint32_t dr2[8]; /* 0x0b0 */ 192 volatile rt_uint32_t dr3[8]; /* 0x0d0 */ 193 volatile rt_uint32_t dr4[8]; /* 0x0f0 */ 194 }; 195 196 typedef struct reg_pl041 *reg_pl041_t; 197 198 #define PL041 ((reg_pl041_t)PL041_BASE_ADDR) 199 200 struct pl041_cfg 201 { 202 rt_uint32_t itype; 203 rt_uint32_t otype; 204 int vol; 205 int rate; 206 }; 207 typedef struct pl041_cfg *pl041_cfg_t; 208 209 typedef void (*pl041_irq_fun_t)(rt_uint32_t status, void * user_data); 210 211 rt_err_t aaci_pl041_init(void); 212 void aaci_ac97_write(rt_uint16_t reg, rt_uint16_t val); 213 rt_uint16_t aaci_ac97_read(rt_uint16_t reg); 214 int aaci_pl041_channel_cfg(int channel, pl041_cfg_t cfg); 215 int aaci_pl041_channel_write(int channel, rt_uint16_t *buff, int count); 216 int aaci_pl041_channel_read(int channel, rt_uint16_t *buff, int count); 217 int aaci_pl041_channel_enable(int channel); 218 int aaci_pl041_channel_disable(int channel); 219 rt_err_t aaci_pl041_irq_register(int channel, pl041_irq_fun_t fun, void *user_data); 220 rt_err_t aaci_pl041_irq_unregister(int channel); 221 void aaci_pl041_irq_disable(int channel, rt_uint32_t vector); 222 void aaci_pl041_irq_enable(int channel, rt_uint32_t vector); 223 #endif 224