1 /*
2 * Copyright (c) 2006-2021, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include "drv_spi.h"
8
9 #include "fsl_common.h"
10 #include "fsl_iocon.h"
11 #include "fsl_spi.h"
12
13 struct lpc_spi
14 {
15 SPI_Type *base;
16 struct rt_spi_configuration *cfg;
17 };
18
get_spi_freq(SPI_Type * base)19 static uint32_t get_spi_freq(SPI_Type *base)
20 {
21 uint32_t freq = 0;
22
23 #if defined(BSP_USING_SPI2)
24 if(base == SPI2)
25 {
26 freq = CLOCK_GetFreq(kCLOCK_Flexcomm2);
27 }
28 #endif
29
30 return freq;
31 }
32
spi_init(SPI_Type * base,struct rt_spi_configuration * cfg)33 static rt_err_t spi_init(SPI_Type *base, struct rt_spi_configuration *cfg)
34 {
35 spi_master_config_t masterConfig = {0};
36
37 RT_ASSERT(cfg != RT_NULL);
38
39 if(cfg->data_width != 8 && cfg->data_width != 16)
40 {
41 return (-RT_EINVAL);
42 }
43
44 SPI_MasterGetDefaultConfig(&masterConfig);
45
46 if(cfg->max_hz > 12*1000*1000)
47 {
48 cfg->max_hz = 12*1000*1000;
49 }
50 masterConfig.baudRate_Bps = cfg->max_hz;
51
52 if(cfg->data_width == 8)
53 {
54 masterConfig.dataWidth = kSPI_Data8Bits;
55 }
56 else if(cfg->data_width == 16)
57 {
58 masterConfig.dataWidth = kSPI_Data16Bits;
59 }
60
61 if(cfg->mode & RT_SPI_MSB)
62 {
63 masterConfig.direction = kSPI_MsbFirst;
64 }
65 else
66 {
67 masterConfig.direction = kSPI_LsbFirst;
68 }
69
70 if(cfg->mode & RT_SPI_CPHA)
71 {
72 masterConfig.phase = kSPI_ClockPhaseSecondEdge;
73 }
74 else
75 {
76 masterConfig.phase = kSPI_ClockPhaseFirstEdge;
77 }
78
79 if(cfg->mode & RT_SPI_CPOL)
80 {
81 masterConfig.polarity = kSPI_ClockPolarityActiveLow;
82 }
83 else
84 {
85 masterConfig.polarity = kSPI_ClockPolarityActiveHigh;
86 }
87
88 masterConfig.txWatermark = kSPI_TxFifo0,
89 masterConfig.rxWatermark = kSPI_RxFifo1,
90
91 // masterConfig.sselNum = kSPI_Ssel3;
92 SPI_MasterInit(base, &masterConfig, get_spi_freq(base));
93
94 return RT_EOK;
95 }
96
lpc_spi_bus_attach_device(const char * bus_name,const char * device_name,rt_uint32_t pin)97 rt_err_t lpc_spi_bus_attach_device(const char *bus_name, const char *device_name, rt_uint32_t pin)
98 {
99 rt_err_t ret = RT_EOK;
100
101 struct rt_spi_device *spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device));
102 RT_ASSERT(spi_device != RT_NULL);
103
104 struct lpc_sw_spi_cs *cs_pin = (struct lpc_sw_spi_cs *)rt_malloc(sizeof(struct lpc_sw_spi_cs));
105 RT_ASSERT(cs_pin != RT_NULL);
106
107 cs_pin->pin = pin;
108 rt_pin_mode(pin, PIN_MODE_OUTPUT);
109 rt_pin_write(pin, PIN_HIGH);
110
111 ret = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin);
112
113 return ret;
114 }
115
configure(struct rt_spi_device * device,struct rt_spi_configuration * cfg)116 static rt_err_t configure(struct rt_spi_device *device, struct rt_spi_configuration *cfg)
117 {
118 rt_err_t ret = RT_EOK;
119 struct lpc_spi *spi = RT_NULL;
120
121 RT_ASSERT(cfg != RT_NULL);
122 RT_ASSERT(device != RT_NULL);
123
124 spi = (struct lpc_spi *)(device->bus->parent.user_data);
125 spi->cfg = cfg;
126 ret = spi_init(spi->base, cfg);
127
128 return ret;
129 }
130
spixfer(struct rt_spi_device * device,struct rt_spi_message * message)131 static rt_ssize_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message)
132 {
133 spi_transfer_t transfer = {0};
134
135 RT_ASSERT(device != RT_NULL);
136 RT_ASSERT(device->bus != RT_NULL);
137 RT_ASSERT(device->bus->parent.user_data != RT_NULL);
138
139 struct lpc_spi *spi = (struct lpc_spi *)(device->bus->parent.user_data);
140 struct lpc_sw_spi_cs *cs = device->parent.user_data;
141
142 if(message->cs_take)
143 {
144 rt_pin_write(cs->pin, PIN_LOW);
145 }
146
147 transfer.dataSize = message->length;
148 transfer.rxData = (uint8_t *)(message->recv_buf);
149 transfer.txData = (uint8_t *)(message->send_buf);
150 transfer.configFlags |= kSPI_FrameAssert;
151
152 SPI_MasterTransferBlocking(spi->base, &transfer);
153
154 if(message->cs_release)
155 {
156 rt_pin_write(cs->pin, PIN_HIGH);
157 }
158
159 return message->length;
160 }
161
162 #if defined(BSP_USING_SPI2)
163 static struct lpc_spi spi2 = {0};
164 static struct rt_spi_bus spi2_bus = {0};
165 #endif
166
167 static struct rt_spi_ops lpc_spi_ops =
168 {
169 configure,
170 spixfer
171 };
172
rt_hw_spi_init(void)173 int rt_hw_spi_init(void)
174 {
175 CLOCK_EnableClock(kCLOCK_Iocon);
176
177 #if defined(BSP_USING_SPI2)
178 CLOCK_AttachClk(kFRO12M_to_FLEXCOMM2);
179 RESET_PeripheralReset(kFC2_RST_SHIFT_RSTn);
180
181 spi2.base = SPI2;
182 spi2.cfg = RT_NULL;
183 spi2_bus.parent.user_data = &spi2;
184
185 IOCON_PinMuxSet(IOCON, 0, 8, (IOCON_FUNC1 | IOCON_MODE_PULLUP | IOCON_GPIO_MODE | IOCON_DIGITAL_EN)); /* SPI2_MOSI */
186 IOCON_PinMuxSet(IOCON, 0, 9, (IOCON_FUNC1 | IOCON_MODE_PULLUP | IOCON_GPIO_MODE | IOCON_DIGITAL_EN)); /* SPI2_MISO */
187 IOCON_PinMuxSet(IOCON, 0, 10, (IOCON_FUNC1 | IOCON_MODE_PULLUP | IOCON_GPIO_MODE | IOCON_DIGITAL_EN)); /* SPI2_SCK */
188
189 rt_spi_bus_register(&spi2_bus, "spi2", &lpc_spi_ops);
190 #endif
191
192 return RT_EOK;
193 }
194 INIT_BOARD_EXPORT(rt_hw_spi_init);
195