1 #ifndef __ASM_PPC_PROCESSOR_H
2 #define __ASM_PPC_PROCESSOR_H
3
4 /*
5 * Default implementation of macro that returns current
6 * instruction pointer ("program counter").
7 */
8 #define current_text_addr() ({ __label__ _l; _l: &&_l;})
9
10 #include <config.h>
11
12 #include <asm/ptrace.h>
13 #include <asm/types.h>
14
15 /* Machine State Register (MSR) Fields */
16
17 #ifdef CONFIG_PPC64BRIDGE
18 #define MSR_SF (1<<63)
19 #define MSR_ISF (1<<61)
20 #endif /* CONFIG_PPC64BRIDGE */
21 #define MSR_UCLE (1<<26) /* User-mode cache lock enable (e500) */
22 #define MSR_VEC (1<<25) /* Enable AltiVec(74xx) */
23 #define MSR_SPE (1<<25) /* Enable SPE(e500) */
24 #define MSR_POW (1<<18) /* Enable Power Management */
25 #define MSR_WE (1<<18) /* Wait State Enable */
26 #define MSR_TGPR (1<<17) /* TLB Update registers in use */
27 #define MSR_CE (1<<17) /* Critical Interrupt Enable */
28 #define MSR_ILE (1<<16) /* Interrupt Little Endian */
29 #define MSR_EE (1<<15) /* External Interrupt Enable */
30 #define MSR_PR (1<<14) /* Problem State / Privilege Level */
31 #define MSR_FP (1<<13) /* Floating Point enable */
32 #define MSR_ME (1<<12) /* Machine Check Enable */
33 #define MSR_FE0 (1<<11) /* Floating Exception mode 0 */
34 #define MSR_SE (1<<10) /* Single Step */
35 #define MSR_DWE (1<<10) /* Debug Wait Enable (4xx) */
36 #define MSR_UBLE (1<<10) /* BTB lock enable (e500) */
37 #define MSR_BE (1<<9) /* Branch Trace */
38 #define MSR_DE (1<<9) /* Debug Exception Enable */
39 #define MSR_FE1 (1<<8) /* Floating Exception mode 1 */
40 #define MSR_IP (1<<6) /* Exception prefix 0x000/0xFFF */
41 #define MSR_IR (1<<5) /* Instruction Relocate */
42 #define MSR_IS (1<<5) /* Book E Instruction space */
43 #define MSR_DR (1<<4) /* Data Relocate */
44 #define MSR_DS (1<<4) /* Book E Data space */
45 #define MSR_PE (1<<3) /* Protection Enable */
46 #define MSR_PX (1<<2) /* Protection Exclusive Mode */
47 #define MSR_PMM (1<<2) /* Performance monitor mark bit (e500) */
48 #define MSR_RI (1<<1) /* Recoverable Exception */
49 #define MSR_LE (1<<0) /* Little Endian */
50
51 #ifdef CONFIG_APUS_FAST_EXCEPT
52 #define MSR_ MSR_ME|MSR_IP|MSR_RI
53 #else
54 #define MSR_ MSR_ME|MSR_RI
55 #endif
56
57 #ifndef CONFIG_E500
58 #define MSR_KERNEL MSR_|MSR_IR|MSR_DR
59 #else
60 #define MSR_KERNEL MSR_ME
61 #endif
62
63 /* Floating Point Status and Control Register (FPSCR) Fields */
64
65 #define FPSCR_FX 0x80000000 /* FPU exception summary */
66 #define FPSCR_FEX 0x40000000 /* FPU enabled exception summary */
67 #define FPSCR_VX 0x20000000 /* Invalid operation summary */
68 #define FPSCR_OX 0x10000000 /* Overflow exception summary */
69 #define FPSCR_UX 0x08000000 /* Underflow exception summary */
70 #define FPSCR_ZX 0x04000000 /* Zero-devide exception summary */
71 #define FPSCR_XX 0x02000000 /* Inexact exception summary */
72 #define FPSCR_VXSNAN 0x01000000 /* Invalid op for SNaN */
73 #define FPSCR_VXISI 0x00800000 /* Invalid op for Inv - Inv */
74 #define FPSCR_VXIDI 0x00400000 /* Invalid op for Inv / Inv */
75 #define FPSCR_VXZDZ 0x00200000 /* Invalid op for Zero / Zero */
76 #define FPSCR_VXIMZ 0x00100000 /* Invalid op for Inv * Zero */
77 #define FPSCR_VXVC 0x00080000 /* Invalid op for Compare */
78 #define FPSCR_FR 0x00040000 /* Fraction rounded */
79 #define FPSCR_FI 0x00020000 /* Fraction inexact */
80 #define FPSCR_FPRF 0x0001f000 /* FPU Result Flags */
81 #define FPSCR_FPCC 0x0000f000 /* FPU Condition Codes */
82 #define FPSCR_VXSOFT 0x00000400 /* Invalid op for software request */
83 #define FPSCR_VXSQRT 0x00000200 /* Invalid op for square root */
84 #define FPSCR_VXCVI 0x00000100 /* Invalid op for integer convert */
85 #define FPSCR_VE 0x00000080 /* Invalid op exception enable */
86 #define FPSCR_OE 0x00000040 /* IEEE overflow exception enable */
87 #define FPSCR_UE 0x00000020 /* IEEE underflow exception enable */
88 #define FPSCR_ZE 0x00000010 /* IEEE zero divide exception enable */
89 #define FPSCR_XE 0x00000008 /* FP inexact exception enable */
90 #define FPSCR_NI 0x00000004 /* FPU non IEEE-Mode */
91 #define FPSCR_RN 0x00000003 /* FPU rounding control */
92
93 /* Special Purpose Registers (SPRNs)*/
94
95 /* PPC440 Architecture is BOOK-E */
96 #ifdef CONFIG_440
97 #define CONFIG_BOOKE
98 #endif
99
100 #define SPRN_CCR0 0x3B3 /* Core Configuration Register 0 */
101 #ifdef CONFIG_BOOKE
102 #define SPRN_CCR1 0x378 /* Core Configuration Register for 440 only */
103 #endif
104 #define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */
105 #define SPRN_CTR 0x009 /* Count Register */
106 #define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */
107 #ifndef CONFIG_BOOKE
108 #define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */
109 #define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */
110 #else
111 #define SPRN_DAC1 0x13C /* Book E Data Address Compare 1 */
112 #define SPRN_DAC2 0x13D /* Book E Data Address Compare 2 */
113 #endif /* CONFIG_BOOKE */
114 #define SPRN_DAR 0x013 /* Data Address Register */
115 #define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */
116 #define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */
117 #define SPRN_DBAT1L 0x21B /* Data BAT 1 Lower Register */
118 #define SPRN_DBAT1U 0x21A /* Data BAT 1 Upper Register */
119 #define SPRN_DBAT2L 0x21D /* Data BAT 2 Lower Register */
120 #define SPRN_DBAT2U 0x21C /* Data BAT 2 Upper Register */
121 #define SPRN_DBAT3L 0x21F /* Data BAT 3 Lower Register */
122 #define SPRN_DBAT3U 0x21E /* Data BAT 3 Upper Register */
123 #define SPRN_DBAT4L 0x239 /* Data BAT 4 Lower Register */
124 #define SPRN_DBAT4U 0x238 /* Data BAT 4 Upper Register */
125 #define SPRN_DBAT5L 0x23B /* Data BAT 5 Lower Register */
126 #define SPRN_DBAT5U 0x23A /* Data BAT 5 Upper Register */
127 #define SPRN_DBAT6L 0x23D /* Data BAT 6 Lower Register */
128 #define SPRN_DBAT6U 0x23C /* Data BAT 6 Upper Register */
129 #define SPRN_DBAT7L 0x23F /* Data BAT 7 Lower Register */
130 #define SPRN_DBAT7U 0x23E /* Data BAT 7 Lower Register */
131 #define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */
132 #define DBCR_EDM 0x80000000
133 #define DBCR_IDM 0x40000000
134 #define DBCR_RST(x) (((x) & 0x3) << 28)
135 #define DBCR_RST_NONE 0
136 #define DBCR_RST_CORE 1
137 #define DBCR_RST_CHIP 2
138 #define DBCR_RST_SYSTEM 3
139 #define DBCR_IC 0x08000000 /* Instruction Completion Debug Evnt */
140 #define DBCR_BT 0x04000000 /* Branch Taken Debug Event */
141 #define DBCR_EDE 0x02000000 /* Exception Debug Event */
142 #define DBCR_TDE 0x01000000 /* TRAP Debug Event */
143 #define DBCR_FER 0x00F80000 /* First Events Remaining Mask */
144 #define DBCR_FT 0x00040000 /* Freeze Timers on Debug Event */
145 #define DBCR_IA1 0x00020000 /* Instr. Addr. Compare 1 Enable */
146 #define DBCR_IA2 0x00010000 /* Instr. Addr. Compare 2 Enable */
147 #define DBCR_D1R 0x00008000 /* Data Addr. Compare 1 Read Enable */
148 #define DBCR_D1W 0x00004000 /* Data Addr. Compare 1 Write Enable */
149 #define DBCR_D1S(x) (((x) & 0x3) << 12) /* Data Adrr. Compare 1 Size */
150 #define DAC_BYTE 0
151 #define DAC_HALF 1
152 #define DAC_WORD 2
153 #define DAC_QUAD 3
154 #define DBCR_D2R 0x00000800 /* Data Addr. Compare 2 Read Enable */
155 #define DBCR_D2W 0x00000400 /* Data Addr. Compare 2 Write Enable */
156 #define DBCR_D2S(x) (((x) & 0x3) << 8) /* Data Addr. Compare 2 Size */
157 #define DBCR_SBT 0x00000040 /* Second Branch Taken Debug Event */
158 #define DBCR_SED 0x00000020 /* Second Exception Debug Event */
159 #define DBCR_STD 0x00000010 /* Second Trap Debug Event */
160 #define DBCR_SIA 0x00000008 /* Second IAC Enable */
161 #define DBCR_SDA 0x00000004 /* Second DAC Enable */
162 #define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */
163 #define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */
164 #ifndef CONFIG_BOOKE
165 #define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */
166 #else
167 #define SPRN_DBCR0 0x134 /* Book E Debug Control Register 0 */
168 #endif /* CONFIG_BOOKE */
169 #ifndef CONFIG_BOOKE
170 #define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */
171 #define SPRN_DBSR 0x3F0 /* Debug Status Register */
172 #else
173 #define SPRN_DBCR1 0x135 /* Book E Debug Control Register 1 */
174 #ifdef CONFIG_BOOKE
175 #define SPRN_DBDR 0x3f3 /* Debug Data Register */
176 #endif
177 #define SPRN_DBSR 0x130 /* Book E Debug Status Register */
178 #define DBSR_IC 0x08000000 /* Book E Instruction Completion */
179 #define DBSR_TIE 0x01000000 /* Book E Trap Instruction Event */
180 #endif /* CONFIG_BOOKE */
181 #define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */
182 #define DCCR_NOCACHE 0 /* Noncacheable */
183 #define DCCR_CACHE 1 /* Cacheable */
184 #ifndef CONFIG_BOOKE
185 #define SPRN_DCDBTRL 0x39c /* Data Cache Debug Tag Register Low */
186 #define SPRN_DCDBTRH 0x39d /* Data Cache Debug Tag Register High */
187 #endif
188 #define SPRN_DCMP 0x3D1 /* Data TLB Compare Register */
189 #define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */
190 #define DCWR_COPY 0 /* Copy-back */
191 #define DCWR_WRITE 1 /* Write-through */
192 #ifndef CONFIG_BOOKE
193 #define SPRN_DEAR 0x3D5 /* Data Error Address Register */
194 #else
195 #define SPRN_DEAR 0x03D /* Book E Data Error Address Register */
196 #endif /* CONFIG_BOOKE */
197 #define SPRN_DEC 0x016 /* Decrement Register */
198 #define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */
199 #ifdef CONFIG_BOOKE
200 #define SPRN_DNV0 0x390 /* Data Cache Normal Victim 0 */
201 #define SPRN_DNV1 0x391 /* Data Cache Normal Victim 1 */
202 #define SPRN_DNV2 0x392 /* Data Cache Normal Victim 2 */
203 #define SPRN_DNV3 0x393 /* Data Cache Normal Victim 3 */
204 #endif
205 #define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */
206 #ifdef CONFIG_BOOKE
207 #define SPRN_DTV0 0x394 /* Data Cache Transient Victim 0 */
208 #define SPRN_DTV1 0x395 /* Data Cache Transient Victim 1 */
209 #define SPRN_DTV2 0x396 /* Data Cache Transient Victim 2 */
210 #define SPRN_DTV3 0x397 /* Data Cache Transient Victim 3 */
211 #define SPRN_DVLIM 0x398 /* Data Cache Victim Limit */
212 #endif
213 #define SPRN_EAR 0x11A /* External Address Register */
214 #ifndef CONFIG_BOOKE
215 #define SPRN_ESR 0x3D4 /* Exception Syndrome Register */
216 #else
217 #define SPRN_ESR 0x03E /* Book E Exception Syndrome Register */
218 #endif /* CONFIG_BOOKE */
219 #define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */
220 #define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */
221 #define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */
222 #define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */
223 #define ESR_PIL 0x08000000 /* Program Exception - Illegal */
224 #define ESR_PPR 0x04000000 /* Program Exception - Priveleged */
225 #define ESR_PTR 0x02000000 /* Program Exception - Trap */
226 #define ESR_DST 0x00800000 /* Storage Exception - Data miss */
227 #define ESR_DIZ 0x00400000 /* Storage Exception - Zone fault */
228 #define SPRN_EVPR 0x3D6 /* Exception Vector Prefix Register */
229 #define SPRN_HASH1 0x3D2 /* Primary Hash Address Register */
230 #define SPRN_HASH2 0x3D3 /* Secondary Hash Address Resgister */
231 #define SPRN_HID0 0x3F0 /* Hardware Implementation Register 0 */
232
233 #define HID0_ICE_SHIFT 15
234 #define HID0_DCE_SHIFT 14
235 #define HID0_DLOCK_SHIFT 12
236
237 #define HID0_EMCP (1<<31) /* Enable Machine Check pin */
238 #define HID0_EBA (1<<29) /* Enable Bus Address Parity */
239 #define HID0_EBD (1<<28) /* Enable Bus Data Parity */
240 #define HID0_SBCLK (1<<27)
241 #define HID0_EICE (1<<26)
242 #define HID0_ECLK (1<<25)
243 #define HID0_PAR (1<<24)
244 #define HID0_DOZE (1<<23)
245 #define HID0_NAP (1<<22)
246 #define HID0_SLEEP (1<<21)
247 #define HID0_DPM (1<<20)
248 #define HID0_ICE (1<<HID0_ICE_SHIFT) /* Instruction Cache Enable */
249 #define HID0_DCE (1<<HID0_DCE_SHIFT) /* Data Cache Enable */
250 #define HID0_TBEN (1<<14) /* Time Base Enable */
251 #define HID0_ILOCK (1<<13) /* Instruction Cache Lock */
252 #define HID0_DLOCK (1<<HID0_DLOCK_SHIFT) /* Data Cache Lock */
253 #define HID0_ICFI (1<<11) /* Instr. Cache Flash Invalidate */
254 #define HID0_DCFI (1<<10) /* Data Cache Flash Invalidate */
255 #define HID0_DCI HID0_DCFI
256 #define HID0_SPD (1<<9) /* Speculative disable */
257 #define HID0_ENMAS7 (1<<7) /* Enable MAS7 Update for 36-bit phys */
258 #define HID0_SGE (1<<7) /* Store Gathering Enable */
259 #define HID0_SIED HID_SGE /* Serial Instr. Execution [Disable] */
260 #define HID0_DCFA (1<<6) /* Data Cache Flush Assist */
261 #define HID0_BTIC (1<<5) /* Branch Target Instruction Cache Enable */
262 #define HID0_ABE (1<<3) /* Address Broadcast Enable */
263 #define HID0_BHTE (1<<2) /* Branch History Table Enable */
264 #define HID0_BTCD (1<<1) /* Branch target cache disable */
265 #define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */
266 #define HID1_RFXE (1<<17) /* Read Fault Exception Enable */
267 #define HID1_ASTME (1<<13) /* Address bus streaming mode */
268 #define HID1_ABE (1<<12) /* Address broadcast enable */
269 #define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */
270 #ifndef CONFIG_BOOKE
271 #define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */
272 #define SPRN_IAC2 0x3F5 /* Instruction Address Compare 2 */
273 #else
274 #define SPRN_IAC1 0x138 /* Book E Instruction Address Compare 1 */
275 #define SPRN_IAC2 0x139 /* Book E Instruction Address Compare 2 */
276 #endif /* CONFIG_BOOKE */
277 #define SPRN_IBAT0L 0x211 /* Instruction BAT 0 Lower Register */
278 #define SPRN_IBAT0U 0x210 /* Instruction BAT 0 Upper Register */
279 #define SPRN_IBAT1L 0x213 /* Instruction BAT 1 Lower Register */
280 #define SPRN_IBAT1U 0x212 /* Instruction BAT 1 Upper Register */
281 #define SPRN_IBAT2L 0x215 /* Instruction BAT 2 Lower Register */
282 #define SPRN_IBAT2U 0x214 /* Instruction BAT 2 Upper Register */
283 #define SPRN_IBAT3L 0x217 /* Instruction BAT 3 Lower Register */
284 #define SPRN_IBAT3U 0x216 /* Instruction BAT 3 Upper Register */
285 #define SPRN_IBAT4L 0x231 /* Instruction BAT 4 Lower Register */
286 #define SPRN_IBAT4U 0x230 /* Instruction BAT 4 Upper Register */
287 #define SPRN_IBAT5L 0x233 /* Instruction BAT 5 Lower Register */
288 #define SPRN_IBAT5U 0x232 /* Instruction BAT 5 Upper Register */
289 #define SPRN_IBAT6L 0x235 /* Instruction BAT 6 Lower Register */
290 #define SPRN_IBAT6U 0x234 /* Instruction BAT 6 Upper Register */
291 #define SPRN_IBAT7L 0x237 /* Instruction BAT 7 Lower Register */
292 #define SPRN_IBAT7U 0x236 /* Instruction BAT 7 Upper Register */
293 #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */
294 #define ICCR_NOCACHE 0 /* Noncacheable */
295 #define ICCR_CACHE 1 /* Cacheable */
296 #define SPRN_ICDBDR 0x3D3 /* Instruction Cache Debug Data Register */
297 #ifdef CONFIG_BOOKE
298 #define SPRN_ICDBTRL 0x39e /* instruction cache debug tag register low */
299 #define SPRN_ICDBTRH 0x39f /* instruction cache debug tag register high */
300 #endif
301 #define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */
302 #define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */
303 #define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */
304 #define SPRN_IMMR 0x27E /* Internal Memory Map Register */
305 #ifdef CONFIG_BOOKE
306 #define SPRN_INV0 0x370 /* Instruction Cache Normal Victim 0 */
307 #define SPRN_INV1 0x371 /* Instruction Cache Normal Victim 1 */
308 #define SPRN_INV2 0x372 /* Instruction Cache Normal Victim 2 */
309 #define SPRN_INV3 0x373 /* Instruction Cache Normal Victim 3 */
310 #define SPRN_ITV0 0x374 /* Instruction Cache Transient Victim 0 */
311 #define SPRN_ITV1 0x375 /* Instruction Cache Transient Victim 1 */
312 #define SPRN_ITV2 0x376 /* Instruction Cache Transient Victim 2 */
313 #define SPRN_ITV3 0x377 /* Instruction Cache Transient Victim 3 */
314 #define SPRN_IVLIM 0x399 /* Instruction Cache Victim Limit */
315 #endif
316 #define SPRN_LDSTCR 0x3F8 /* Load/Store Control Register */
317 #define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */
318 #define SPRN_LR 0x008 /* Link Register */
319 #define SPRN_MBAR 0x137 /* System memory base address */
320 #define SPRN_MMCR0 0x3B8 /* Monitor Mode Control Register 0 */
321 #define SPRN_MMCR1 0x3BC /* Monitor Mode Control Register 1 */
322 #ifdef CONFIG_BOOKE
323 #define SPRN_MMUCR 0x3b2 /* MMU Control Register */
324 #endif
325 #define SPRN_PBL1 0x3FC /* Protection Bound Lower 1 */
326 #define SPRN_PBL2 0x3FE /* Protection Bound Lower 2 */
327 #define SPRN_PBU1 0x3FD /* Protection Bound Upper 1 */
328 #define SPRN_PBU2 0x3FF /* Protection Bound Upper 2 */
329 #ifndef CONFIG_BOOKE
330 #define SPRN_PID 0x3B1 /* Process ID */
331 #define SPRN_PIR 0x3FF /* Processor Identification Register */
332 #else
333 #define SPRN_PID 0x030 /* Book E Process ID */
334 #define SPRN_PIR 0x11E /* Book E Processor Identification Register */
335 #endif /* CONFIG_BOOKE */
336 #define SPRN_PIT 0x3DB /* Programmable Interval Timer */
337 #define SPRN_PMC1 0x3B9 /* Performance Counter Register 1 */
338 #define SPRN_PMC2 0x3BA /* Performance Counter Register 2 */
339 #define SPRN_PMC3 0x3BD /* Performance Counter Register 3 */
340 #define SPRN_PMC4 0x3BE /* Performance Counter Register 4 */
341 #define SPRN_PVR 0x11F /* Processor Version Register */
342 #define SPRN_RPA 0x3D6 /* Required Physical Address Register */
343 #ifdef CONFIG_BOOKE
344 #define SPRN_RSTCFG 0x39b /* Reset Configuration */
345 #endif
346 #define SPRN_SDA 0x3BF /* Sampled Data Address Register */
347 #define SPRN_SDR1 0x019 /* MMU Hash Base Register */
348 #define SPRN_SGR 0x3B9 /* Storage Guarded Register */
349 #define SGR_NORMAL 0
350 #define SGR_GUARDED 1
351 #define SPRN_SIA 0x3BB /* Sampled Instruction Address Register */
352 #define SPRN_SPRG0 0x110 /* Special Purpose Register General 0 */
353 #define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */
354 #define SPRN_SPRG2 0x112 /* Special Purpose Register General 2 */
355 #define SPRN_SPRG3 0x113 /* Special Purpose Register General 3 */
356 #define SPRN_SPRG4 0x114 /* Special Purpose Register General 4 */
357 #define SPRN_SPRG5 0x115 /* Special Purpose Register General 5 */
358 #define SPRN_SPRG6 0x116 /* Special Purpose Register General 6 */
359 #define SPRN_SPRG7 0x117 /* Special Purpose Register General 7 */
360 #define SPRN_SRR0 0x01A /* Save/Restore Register 0 */
361 #define SPRN_SRR1 0x01B /* Save/Restore Register 1 */
362 #define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */
363 #define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */
364
365 #ifdef CONFIG_BOOKE
366 #define SPRN_SVR 0x3FF /* System Version Register */
367 #else
368 #define SPRN_SVR 0x11E /* System Version Register */
369 #endif
370 #define SPRN_TBHI 0x3DC /* Time Base High */
371 #define SPRN_TBHU 0x3CC /* Time Base High User-mode */
372 #define SPRN_TBLO 0x3DD /* Time Base Low */
373 #define SPRN_TBLU 0x3CD /* Time Base Low User-mode */
374 #define SPRN_TBRL 0x10C /* Time Base Read Lower Register */
375 #define SPRN_TBRU 0x10D /* Time Base Read Upper Register */
376 #define SPRN_TBWL 0x11C /* Time Base Write Lower Register */
377 #define SPRN_TBWU 0x11D /* Time Base Write Upper Register */
378 #ifndef CONFIG_BOOKE
379 #define SPRN_TCR 0x3DA /* Timer Control Register */
380 #else
381 #define SPRN_TCR 0x154 /* Book E Timer Control Register */
382 #endif /* CONFIG_BOOKE */
383 #define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */
384 #define WP_2_17 0 /* 2^17 clocks */
385 #define WP_2_21 1 /* 2^21 clocks */
386 #define WP_2_25 2 /* 2^25 clocks */
387 #define WP_2_29 3 /* 2^29 clocks */
388 #define TCR_WRC(x) (((x)&0x3)<<28) /* WDT Reset Control */
389 #define WRC_NONE 0 /* No reset will occur */
390 #define WRC_CORE 1 /* Core reset will occur */
391 #define WRC_CHIP 2 /* Chip reset will occur */
392 #define WRC_SYSTEM 3 /* System reset will occur */
393 #define TCR_WIE 0x08000000 /* WDT Interrupt Enable */
394 #define TCR_PIE 0x04000000 /* PIT Interrupt Enable */
395 #define TCR_FP(x) (((x)&0x3)<<24) /* FIT Period */
396 #define FP_2_9 0 /* 2^9 clocks */
397 #define FP_2_13 1 /* 2^13 clocks */
398 #define FP_2_17 2 /* 2^17 clocks */
399 #define FP_2_21 3 /* 2^21 clocks */
400 #define TCR_FIE 0x00800000 /* FIT Interrupt Enable */
401 #define TCR_ARE 0x00400000 /* Auto Reload Enable */
402 #define SPRN_THRM1 0x3FC /* Thermal Management Register 1 */
403 #define THRM1_TIN (1<<0)
404 #define THRM1_TIV (1<<1)
405 #define THRM1_THRES (0x7f<<2)
406 #define THRM1_TID (1<<29)
407 #define THRM1_TIE (1<<30)
408 #define THRM1_V (1<<31)
409 #define SPRN_THRM2 0x3FD /* Thermal Management Register 2 */
410 #define SPRN_THRM3 0x3FE /* Thermal Management Register 3 */
411 #define THRM3_E (1<<31)
412 #define SPRN_TLBMISS 0x3D4 /* 980 7450 TLB Miss Register */
413 #ifndef CONFIG_BOOKE
414 #define SPRN_TSR 0x3D8 /* Timer Status Register */
415 #else
416 #define SPRN_TSR 0x150 /* Book E Timer Status Register */
417 #endif /* CONFIG_BOOKE */
418 #define TSR_ENW 0x80000000 /* Enable Next Watchdog */
419 #define TSR_WIS 0x40000000 /* WDT Interrupt Status */
420 #define TSR_WRS(x) (((x)&0x3)<<28) /* WDT Reset Status */
421 #define WRS_NONE 0 /* No WDT reset occurred */
422 #define WRS_CORE 1 /* WDT forced core reset */
423 #define WRS_CHIP 2 /* WDT forced chip reset */
424 #define WRS_SYSTEM 3 /* WDT forced system reset */
425 #define TSR_PIS 0x08000000 /* PIT Interrupt Status */
426 #define TSR_FIS 0x04000000 /* FIT Interrupt Status */
427 #define SPRN_UMMCR0 0x3A8 /* User Monitor Mode Control Register 0 */
428 #define SPRN_UMMCR1 0x3AC /* User Monitor Mode Control Register 0 */
429 #define SPRN_UPMC1 0x3A9 /* User Performance Counter Register 1 */
430 #define SPRN_UPMC2 0x3AA /* User Performance Counter Register 2 */
431 #define SPRN_UPMC3 0x3AD /* User Performance Counter Register 3 */
432 #define SPRN_UPMC4 0x3AE /* User Performance Counter Register 4 */
433 #define SPRN_USIA 0x3AB /* User Sampled Instruction Address Register */
434 #define SPRN_XER 0x001 /* Fixed Point Exception Register */
435 #define SPRN_ZPR 0x3B0 /* Zone Protection Register */
436
437 /* Book E definitions */
438 #define SPRN_DECAR 0x036 /* Decrementer Auto Reload Register */
439 #define SPRN_CSRR0 0x03A /* Critical SRR0 */
440 #define SPRN_CSRR1 0x03B /* Critical SRR0 */
441 #define SPRN_IVPR 0x03F /* Interrupt Vector Prefix Register */
442 #define SPRN_USPRG0 0x100 /* User Special Purpose Register General 0 */
443 #define SPRN_SPRG4R 0x104 /* Special Purpose Register General 4 Read */
444 #define SPRN_SPRG5R 0x105 /* Special Purpose Register General 5 Read */
445 #define SPRN_SPRG6R 0x106 /* Special Purpose Register General 6 Read */
446 #define SPRN_SPRG7R 0x107 /* Special Purpose Register General 7 Read */
447 #define SPRN_SPRG4W 0x114 /* Special Purpose Register General 4 Write */
448 #define SPRN_SPRG5W 0x115 /* Special Purpose Register General 5 Write */
449 #define SPRN_SPRG6W 0x116 /* Special Purpose Register General 6 Write */
450 #define SPRN_SPRG7W 0x117 /* Special Purpose Register General 7 Write */
451 #define SPRN_DBCR2 0x136 /* Debug Control Register 2 */
452 #define SPRN_IAC3 0x13A /* Instruction Address Compare 3 */
453 #define SPRN_IAC4 0x13B /* Instruction Address Compare 4 */
454 #define SPRN_DVC1 0x13E /* Data Value Compare Register 1 */
455 #define SPRN_DVC2 0x13F /* Data Value Compare Register 2 */
456 #define SPRN_IVOR0 0x190 /* Interrupt Vector Offset Register 0 */
457 #define SPRN_IVOR1 0x191 /* Interrupt Vector Offset Register 1 */
458 #define SPRN_IVOR2 0x192 /* Interrupt Vector Offset Register 2 */
459 #define SPRN_IVOR3 0x193 /* Interrupt Vector Offset Register 3 */
460 #define SPRN_IVOR4 0x194 /* Interrupt Vector Offset Register 4 */
461 #define SPRN_IVOR5 0x195 /* Interrupt Vector Offset Register 5 */
462 #define SPRN_IVOR6 0x196 /* Interrupt Vector Offset Register 6 */
463 #define SPRN_IVOR7 0x197 /* Interrupt Vector Offset Register 7 */
464 #define SPRN_IVOR8 0x198 /* Interrupt Vector Offset Register 8 */
465 #define SPRN_IVOR9 0x199 /* Interrupt Vector Offset Register 9 */
466 #define SPRN_IVOR10 0x19a /* Interrupt Vector Offset Register 10 */
467 #define SPRN_IVOR11 0x19b /* Interrupt Vector Offset Register 11 */
468 #define SPRN_IVOR12 0x19c /* Interrupt Vector Offset Register 12 */
469 #define SPRN_IVOR13 0x19d /* Interrupt Vector Offset Register 13 */
470 #define SPRN_IVOR14 0x19e /* Interrupt Vector Offset Register 14 */
471 #define SPRN_IVOR15 0x19f /* Interrupt Vector Offset Register 15 */
472
473 /* e500 definitions */
474 #define SPRN_L1CFG0 0x203 /* L1 Cache Configuration Register 0 */
475 #define SPRN_L1CFG1 0x204 /* L1 Cache Configuration Register 1 */
476 #define SPRN_L2CFG0 0x207 /* L2 Cache Configuration Register 0 */
477 #define SPRN_L1CSR0 0x3f2 /* L1 Data Cache Control and Status Register 0 */
478 #define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */
479 #define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */
480 #define L1CSR0_DCE 0x00000001 /* Data Cache Enable */
481 #define SPRN_L1CSR1 0x3f3 /* L1 Instruction Cache Control and Status Register 1 */
482 #define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */
483 #define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */
484 #define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */
485 #define SPRN_L1CSR2 0x25e /* L1 Data Cache Control and Status Register 2 */
486 #define SPRN_L2CSR0 0x3f9 /* L2 Data Cache Control and Status Register 0 */
487 #define L2CSR0_L2E 0x80000000 /* L2 Cache Enable */
488 #define L2CSR0_L2PE 0x40000000 /* L2 Cache Parity/ECC Enable */
489 #define L2CSR0_L2WP 0x1c000000 /* L2 I/D Way Partioning */
490 #define L2CSR0_L2CM 0x03000000 /* L2 Cache Coherency Mode */
491 #define L2CSR0_L2FI 0x00200000 /* L2 Cache Flash Invalidate */
492 #define L2CSR0_L2IO 0x00100000 /* L2 Cache Instruction Only */
493 #define L2CSR0_L2DO 0x00010000 /* L2 Cache Data Only */
494 #define L2CSR0_L2REP 0x00003000 /* L2 Line Replacement Algo */
495 #define L2CSR0_L2FL 0x00000800 /* L2 Cache Flush */
496 #define L2CSR0_L2LFC 0x00000400 /* L2 Cache Lock Flash Clear */
497 #define L2CSR0_L2LOA 0x00000080 /* L2 Cache Lock Overflow Allocate */
498 #define L2CSR0_L2LO 0x00000020 /* L2 Cache Lock Overflow */
499 #define SPRN_L2CSR1 0x3fa /* L2 Data Cache Control and Status Register 1 */
500
501 #define SPRN_TLB0CFG 0x2B0 /* TLB 0 Config Register */
502 #define SPRN_TLB1CFG 0x2B1 /* TLB 1 Config Register */
503 #define SPRN_MMUCSR0 0x3f4 /* MMU control and status register 0 */
504 #define SPRN_MAS0 0x270 /* MMU Assist Register 0 */
505 #define SPRN_MAS1 0x271 /* MMU Assist Register 1 */
506 #define SPRN_MAS2 0x272 /* MMU Assist Register 2 */
507 #define SPRN_MAS3 0x273 /* MMU Assist Register 3 */
508 #define SPRN_MAS4 0x274 /* MMU Assist Register 4 */
509 #define SPRN_MAS5 0x275 /* MMU Assist Register 5 */
510 #define SPRN_MAS6 0x276 /* MMU Assist Register 6 */
511 #define SPRN_MAS7 0x3B0 /* MMU Assist Register 7 */
512
513 #define SPRN_IVOR32 0x210 /* Interrupt Vector Offset Register 32 */
514 #define SPRN_IVOR33 0x211 /* Interrupt Vector Offset Register 33 */
515 #define SPRN_IVOR34 0x212 /* Interrupt Vector Offset Register 34 */
516 #define SPRN_IVOR35 0x213 /* Interrupt Vector Offset Register 35 */
517 #define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */
518
519 #define SPRN_MCSRR0 0x23a /* Machine Check Save and Restore Register 0 */
520 #define SPRN_MCSRR1 0x23b /* Machine Check Save and Restore Register 1 */
521 #define SPRN_BUCSR 0x3f5 /* Branch Control and Status Register */
522 #define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */
523 #define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */
524 #define SPRN_PID1 0x279 /* Process ID Register 1 */
525 #define SPRN_PID2 0x27a /* Process ID Register 2 */
526 #define SPRN_MCSR 0x23c /* Machine Check Syndrome register */
527 #define SPRN_MCAR 0x23d /* Machine Check Address register */
528 #define MCSR_MCS 0x80000000 /* Machine Check Summary */
529 #define MCSR_IB 0x40000000 /* Instruction PLB Error */
530 #if defined(CONFIG_440)
531 #define MCSR_DRB 0x20000000 /* Data Read PLB Error */
532 #define MCSR_DWB 0x10000000 /* Data Write PLB Error */
533 #else
534 #define MCSR_DB 0x20000000 /* Data PLB Error */
535 #endif /* defined(CONFIG_440) */
536 #define MCSR_TLBP 0x08000000 /* TLB Parity Error */
537 #define MCSR_ICP 0x04000000 /* I-Cache Parity Error */
538 #define MCSR_DCSP 0x02000000 /* D-Cache Search Parity Error */
539 #define MCSR_DCFP 0x01000000 /* D-Cache Flush Parity Error */
540 #define MCSR_IMPE 0x00800000 /* Imprecise Machine Check Exception */
541 #define ESR_ST 0x00800000 /* Store Operation */
542
543 #if defined(CONFIG_MPC86xx)
544 #define SPRN_MSSCR0 0x3f6
545 #define SPRN_MSSSR0 0x3f7
546 #endif
547
548 /* Short-hand versions for a number of the above SPRNs */
549
550 #define CTR SPRN_CTR /* Counter Register */
551 #define DAR SPRN_DAR /* Data Address Register */
552 #define DABR SPRN_DABR /* Data Address Breakpoint Register */
553 #define DAC1 SPRN_DAC1 /* Data Address Register 1 */
554 #define DAC2 SPRN_DAC2 /* Data Address Register 2 */
555 #define DBAT0L SPRN_DBAT0L /* Data BAT 0 Lower Register */
556 #define DBAT0U SPRN_DBAT0U /* Data BAT 0 Upper Register */
557 #define DBAT1L SPRN_DBAT1L /* Data BAT 1 Lower Register */
558 #define DBAT1U SPRN_DBAT1U /* Data BAT 1 Upper Register */
559 #define DBAT2L SPRN_DBAT2L /* Data BAT 2 Lower Register */
560 #define DBAT2U SPRN_DBAT2U /* Data BAT 2 Upper Register */
561 #define DBAT3L SPRN_DBAT3L /* Data BAT 3 Lower Register */
562 #define DBAT3U SPRN_DBAT3U /* Data BAT 3 Upper Register */
563 #define DBAT4L SPRN_DBAT4L /* Data BAT 4 Lower Register */
564 #define DBAT4U SPRN_DBAT4U /* Data BAT 4 Upper Register */
565 #define DBAT5L SPRN_DBAT5L /* Data BAT 5 Lower Register */
566 #define DBAT5U SPRN_DBAT5U /* Data BAT 5 Upper Register */
567 #define DBAT6L SPRN_DBAT6L /* Data BAT 6 Lower Register */
568 #define DBAT6U SPRN_DBAT6U /* Data BAT 6 Upper Register */
569 #define DBAT7L SPRN_DBAT7L /* Data BAT 7 Lower Register */
570 #define DBAT7U SPRN_DBAT7U /* Data BAT 7 Upper Register */
571 #define DBCR0 SPRN_DBCR0 /* Debug Control Register 0 */
572 #define DBCR1 SPRN_DBCR1 /* Debug Control Register 1 */
573 #define DBSR SPRN_DBSR /* Debug Status Register */
574 #define DCMP SPRN_DCMP /* Data TLB Compare Register */
575 #define DEC SPRN_DEC /* Decrement Register */
576 #define DMISS SPRN_DMISS /* Data TLB Miss Register */
577 #define DSISR SPRN_DSISR /* Data Storage Interrupt Status Register */
578 #define EAR SPRN_EAR /* External Address Register */
579 #define ESR SPRN_ESR /* Exception Syndrome Register */
580 #define HASH1 SPRN_HASH1 /* Primary Hash Address Register */
581 #define HASH2 SPRN_HASH2 /* Secondary Hash Address Register */
582 #define HID0 SPRN_HID0 /* Hardware Implementation Register 0 */
583 #define HID1 SPRN_HID1 /* Hardware Implementation Register 1 */
584 #define IABR SPRN_IABR /* Instruction Address Breakpoint Register */
585 #define IAC1 SPRN_IAC1 /* Instruction Address Register 1 */
586 #define IAC2 SPRN_IAC2 /* Instruction Address Register 2 */
587 #define IBAT0L SPRN_IBAT0L /* Instruction BAT 0 Lower Register */
588 #define IBAT0U SPRN_IBAT0U /* Instruction BAT 0 Upper Register */
589 #define IBAT1L SPRN_IBAT1L /* Instruction BAT 1 Lower Register */
590 #define IBAT1U SPRN_IBAT1U /* Instruction BAT 1 Upper Register */
591 #define IBAT2L SPRN_IBAT2L /* Instruction BAT 2 Lower Register */
592 #define IBAT2U SPRN_IBAT2U /* Instruction BAT 2 Upper Register */
593 #define IBAT3L SPRN_IBAT3L /* Instruction BAT 3 Lower Register */
594 #define IBAT3U SPRN_IBAT3U /* Instruction BAT 3 Upper Register */
595 #define IBAT4L SPRN_IBAT4L /* Instruction BAT 4 Lower Register */
596 #define IBAT4U SPRN_IBAT4U /* Instruction BAT 4 Upper Register */
597 #define IBAT5L SPRN_IBAT5L /* Instruction BAT 5 Lower Register */
598 #define IBAT5U SPRN_IBAT5U /* Instruction BAT 5 Upper Register */
599 #define IBAT6L SPRN_IBAT6L /* Instruction BAT 6 Lower Register */
600 #define IBAT6U SPRN_IBAT6U /* Instruction BAT 6 Upper Register */
601 #define IBAT7L SPRN_IBAT7L /* Instruction BAT 7 Lower Register */
602 #define IBAT7U SPRN_IBAT7U /* Instruction BAT 7 Lower Register */
603 #define ICMP SPRN_ICMP /* Instruction TLB Compare Register */
604 #define IMISS SPRN_IMISS /* Instruction TLB Miss Register */
605 #define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */
606 #define LDSTCR SPRN_LDSTCR /* Load/Store Control Register */
607 #define L2CR SPRN_L2CR /* PPC 750 L2 control register */
608 #define LR SPRN_LR
609 #define MBAR SPRN_MBAR /* System memory base address */
610 #if defined(CONFIG_MPC86xx)
611 #define MSSCR0 SPRN_MSSCR0
612 #endif
613 #if defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
614 #define PIR SPRN_PIR
615 #endif
616 #define SVR SPRN_SVR /* System-On-Chip Version Register */
617 #define PVR SPRN_PVR /* Processor Version */
618 #define RPA SPRN_RPA /* Required Physical Address Register */
619 #define SDR1 SPRN_SDR1 /* MMU hash base register */
620 #define SPR0 SPRN_SPRG0 /* Supervisor Private Registers */
621 #define SPR1 SPRN_SPRG1
622 #define SPR2 SPRN_SPRG2
623 #define SPR3 SPRN_SPRG3
624 #define SPRG0 SPRN_SPRG0
625 #define SPRG1 SPRN_SPRG1
626 #define SPRG2 SPRN_SPRG2
627 #define SPRG3 SPRN_SPRG3
628 #define SPRG4 SPRN_SPRG4
629 #define SPRG5 SPRN_SPRG5
630 #define SPRG6 SPRN_SPRG6
631 #define SPRG7 SPRN_SPRG7
632 #define SRR0 SPRN_SRR0 /* Save and Restore Register 0 */
633 #define SRR1 SPRN_SRR1 /* Save and Restore Register 1 */
634 #define SRR2 SPRN_SRR2 /* Save and Restore Register 2 */
635 #define SRR3 SPRN_SRR3 /* Save and Restore Register 3 */
636 #define SVR SPRN_SVR /* System Version Register */
637 #define TBRL SPRN_TBRL /* Time Base Read Lower Register */
638 #define TBRU SPRN_TBRU /* Time Base Read Upper Register */
639 #define TBWL SPRN_TBWL /* Time Base Write Lower Register */
640 #define TBWU SPRN_TBWU /* Time Base Write Upper Register */
641 #define TCR SPRN_TCR /* Timer Control Register */
642 #define TSR SPRN_TSR /* Timer Status Register */
643 #define ICTC 1019
644 #define THRM1 SPRN_THRM1 /* Thermal Management Register 1 */
645 #define THRM2 SPRN_THRM2 /* Thermal Management Register 2 */
646 #define THRM3 SPRN_THRM3 /* Thermal Management Register 3 */
647 #define XER SPRN_XER
648
649 #define DECAR SPRN_DECAR
650 #define CSRR0 SPRN_CSRR0
651 #define CSRR1 SPRN_CSRR1
652 #define IVPR SPRN_IVPR
653 #define USPRG0 SPRN_USPRG
654 #define SPRG4R SPRN_SPRG4R
655 #define SPRG5R SPRN_SPRG5R
656 #define SPRG6R SPRN_SPRG6R
657 #define SPRG7R SPRN_SPRG7R
658 #define SPRG4W SPRN_SPRG4W
659 #define SPRG5W SPRN_SPRG5W
660 #define SPRG6W SPRN_SPRG6W
661 #define SPRG7W SPRN_SPRG7W
662 #define DEAR SPRN_DEAR
663 #define DBCR2 SPRN_DBCR2
664 #define IAC3 SPRN_IAC3
665 #define IAC4 SPRN_IAC4
666 #define DVC1 SPRN_DVC1
667 #define DVC2 SPRN_DVC2
668 #define IVOR0 SPRN_IVOR0
669 #define IVOR1 SPRN_IVOR1
670 #define IVOR2 SPRN_IVOR2
671 #define IVOR3 SPRN_IVOR3
672 #define IVOR4 SPRN_IVOR4
673 #define IVOR5 SPRN_IVOR5
674 #define IVOR6 SPRN_IVOR6
675 #define IVOR7 SPRN_IVOR7
676 #define IVOR8 SPRN_IVOR8
677 #define IVOR9 SPRN_IVOR9
678 #define IVOR10 SPRN_IVOR10
679 #define IVOR11 SPRN_IVOR11
680 #define IVOR12 SPRN_IVOR12
681 #define IVOR13 SPRN_IVOR13
682 #define IVOR14 SPRN_IVOR14
683 #define IVOR15 SPRN_IVOR15
684 #define IVOR32 SPRN_IVOR32
685 #define IVOR33 SPRN_IVOR33
686 #define IVOR34 SPRN_IVOR34
687 #define IVOR35 SPRN_IVOR35
688 #define MCSRR0 SPRN_MCSRR0
689 #define MCSRR1 SPRN_MCSRR1
690 #define L1CSR0 SPRN_L1CSR0
691 #define L1CSR1 SPRN_L1CSR1
692 #define L1CSR2 SPRN_L1CSR2
693 #define L1CFG0 SPRN_L1CFG0
694 #define L1CFG1 SPRN_L1CFG1
695 #define L2CFG0 SPRN_L2CFG0
696 #define L2CSR0 SPRN_L2CSR0
697 #define L2CSR1 SPRN_L2CSR1
698 #define MCSR SPRN_MCSR
699 #define MMUCSR0 SPRN_MMUCSR0
700 #define BUCSR SPRN_BUCSR
701 #define PID0 SPRN_PID
702 #define PID1 SPRN_PID1
703 #define PID2 SPRN_PID2
704 #define MAS0 SPRN_MAS0
705 #define MAS1 SPRN_MAS1
706 #define MAS2 SPRN_MAS2
707 #define MAS3 SPRN_MAS3
708 #define MAS4 SPRN_MAS4
709 #define MAS5 SPRN_MAS5
710 #define MAS6 SPRN_MAS6
711 #define MAS7 SPRN_MAS7
712
713 #if defined(CONFIG_4xx) || defined(CONFIG_44x) || defined(CONFIG_MPC85xx)
714 #define DAR_DEAR DEAR
715 #else
716 #define DAR_DEAR DAR
717 #endif
718
719 /* Device Control Registers */
720
721 #define DCRN_BEAR 0x090 /* Bus Error Address Register */
722 #define DCRN_BESR 0x091 /* Bus Error Syndrome Register */
723 #define BESR_DSES 0x80000000 /* Data-Side Error Status */
724 #define BESR_DMES 0x40000000 /* DMA Error Status */
725 #define BESR_RWS 0x20000000 /* Read/Write Status */
726 #define BESR_ETMASK 0x1C000000 /* Error Type */
727 #define ET_PROT 0
728 #define ET_PARITY 1
729 #define ET_NCFG 2
730 #define ET_BUSERR 4
731 #define ET_BUSTO 6
732 #define DCRN_DMACC0 0x0C4 /* DMA Chained Count Register 0 */
733 #define DCRN_DMACC1 0x0CC /* DMA Chained Count Register 1 */
734 #define DCRN_DMACC2 0x0D4 /* DMA Chained Count Register 2 */
735 #define DCRN_DMACC3 0x0DC /* DMA Chained Count Register 3 */
736 #define DCRN_DMACR0 0x0C0 /* DMA Channel Control Register 0 */
737 #define DCRN_DMACR1 0x0C8 /* DMA Channel Control Register 1 */
738 #define DCRN_DMACR2 0x0D0 /* DMA Channel Control Register 2 */
739 #define DCRN_DMACR3 0x0D8 /* DMA Channel Control Register 3 */
740 #define DCRN_DMACT0 0x0C1 /* DMA Count Register 0 */
741 #define DCRN_DMACT1 0x0C9 /* DMA Count Register 1 */
742 #define DCRN_DMACT2 0x0D1 /* DMA Count Register 2 */
743 #define DCRN_DMACT3 0x0D9 /* DMA Count Register 3 */
744 #define DCRN_DMADA0 0x0C2 /* DMA Destination Address Register 0 */
745 #define DCRN_DMADA1 0x0CA /* DMA Destination Address Register 1 */
746 #define DCRN_DMADA2 0x0D2 /* DMA Destination Address Register 2 */
747 #define DCRN_DMADA3 0x0DA /* DMA Destination Address Register 3 */
748 #define DCRN_DMASA0 0x0C3 /* DMA Source Address Register 0 */
749 #define DCRN_DMASA1 0x0CB /* DMA Source Address Register 1 */
750 #define DCRN_DMASA2 0x0D3 /* DMA Source Address Register 2 */
751 #define DCRN_DMASA3 0x0DB /* DMA Source Address Register 3 */
752 #define DCRN_DMASR 0x0E0 /* DMA Status Register */
753 #define DCRN_EXIER 0x042 /* External Interrupt Enable Register */
754 #define EXIER_CIE 0x80000000 /* Critical Interrupt Enable */
755 #define EXIER_SRIE 0x08000000 /* Serial Port Rx Int. Enable */
756 #define EXIER_STIE 0x04000000 /* Serial Port Tx Int. Enable */
757 #define EXIER_JRIE 0x02000000 /* JTAG Serial Port Rx Int. Enable */
758 #define EXIER_JTIE 0x01000000 /* JTAG Serial Port Tx Int. Enable */
759 #define EXIER_D0IE 0x00800000 /* DMA Channel 0 Interrupt Enable */
760 #define EXIER_D1IE 0x00400000 /* DMA Channel 1 Interrupt Enable */
761 #define EXIER_D2IE 0x00200000 /* DMA Channel 2 Interrupt Enable */
762 #define EXIER_D3IE 0x00100000 /* DMA Channel 3 Interrupt Enable */
763 #define EXIER_E0IE 0x00000010 /* External Interrupt 0 Enable */
764 #define EXIER_E1IE 0x00000008 /* External Interrupt 1 Enable */
765 #define EXIER_E2IE 0x00000004 /* External Interrupt 2 Enable */
766 #define EXIER_E3IE 0x00000002 /* External Interrupt 3 Enable */
767 #define EXIER_E4IE 0x00000001 /* External Interrupt 4 Enable */
768 #define DCRN_EXISR 0x040 /* External Interrupt Status Register */
769 #define DCRN_IOCR 0x0A0 /* Input/Output Configuration Register */
770 #define IOCR_E0TE 0x80000000
771 #define IOCR_E0LP 0x40000000
772 #define IOCR_E1TE 0x20000000
773 #define IOCR_E1LP 0x10000000
774 #define IOCR_E2TE 0x08000000
775 #define IOCR_E2LP 0x04000000
776 #define IOCR_E3TE 0x02000000
777 #define IOCR_E3LP 0x01000000
778 #define IOCR_E4TE 0x00800000
779 #define IOCR_E4LP 0x00400000
780 #define IOCR_EDT 0x00080000
781 #define IOCR_SOR 0x00040000
782 #define IOCR_EDO 0x00008000
783 #define IOCR_2XC 0x00004000
784 #define IOCR_ATC 0x00002000
785 #define IOCR_SPD 0x00001000
786 #define IOCR_BEM 0x00000800
787 #define IOCR_PTD 0x00000400
788 #define IOCR_ARE 0x00000080
789 #define IOCR_DRC 0x00000020
790 #define IOCR_RDM(x) (((x) & 0x3) << 3)
791 #define IOCR_TCS 0x00000004
792 #define IOCR_SCS 0x00000002
793 #define IOCR_SPC 0x00000001
794
795 /* System-On-Chip Version Register */
796
797 /* System-On-Chip Version Register (SVR) field extraction */
798
799 #define SVR_VER(svr) (((svr) >> 16) & 0xFFFF) /* Version field */
800 #define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revision field */
801
802 #define SVR_CID(svr) (((svr) >> 28) & 0x0F) /* Company or manufacturer ID */
803 #define SVR_SOCOP(svr) (((svr) >> 22) & 0x3F) /* SOC integration options */
804 #define SVR_SID(svr) (((svr) >> 16) & 0x3F) /* SOC ID */
805 #define SVR_PROC(svr) (((svr) >> 12) & 0x0F) /* Process revision field */
806 #define SVR_MFG(svr) (((svr) >> 8) & 0x0F) /* Manufacturing revision */
807 #define SVR_MJREV(svr) (((svr) >> 4) & 0x0F) /* Major SOC design revision indicator */
808 #define SVR_MNREV(svr) (((svr) >> 0) & 0x0F) /* Minor SOC design revision indicator */
809
810 /* Processor Version Register */
811
812 /* Processor Version Register (PVR) field extraction */
813
814 #define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */
815 #define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF) /* Revison field */
816
817 /*
818 * AMCC has further subdivided the standard PowerPC 16-bit version and
819 * revision subfields of the PVR for the PowerPC 403s into the following:
820 */
821
822 #define PVR_FAM(pvr) (((pvr) >> 20) & 0xFFF) /* Family field */
823 #define PVR_MEM(pvr) (((pvr) >> 16) & 0xF) /* Member field */
824 #define PVR_CORE(pvr) (((pvr) >> 12) & 0xF) /* Core field */
825 #define PVR_CFG(pvr) (((pvr) >> 8) & 0xF) /* Configuration field */
826 #define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF) /* Major revision field */
827 #define PVR_MIN(pvr) (((pvr) >> 0) & 0xF) /* Minor revision field */
828
829 /* e600 core PVR fields */
830
831 #define PVR_E600_VER(pvr) (((pvr) >> 15) & 0xFFFF) /* Version/type */
832 #define PVR_E600_TECH(pvr) (((pvr) >> 12) & 0xF) /* Technology */
833 #define PVR_E600_MAJ(pvr) (((pvr) >> 8) & 0xF) /* Major revision */
834 #define PVR_E600_MIN(pvr) (((pvr) >> 0) & 0xFF) /* Minor revision */
835
836 /* Processor Version Numbers */
837
838 #define PVR_403GA 0x00200000
839 #define PVR_403GB 0x00200100
840 #define PVR_403GC 0x00200200
841 #define PVR_403GCX 0x00201400
842 #define PVR_405GP 0x40110000
843 #define PVR_405GP_RB 0x40110040
844 #define PVR_405GP_RC 0x40110082
845 #define PVR_405GP_RD 0x401100C4
846 #define PVR_405GP_RE 0x40110145 /* same as pc405cr rev c */
847 #define PVR_405CR_RA 0x40110041
848 #define PVR_405CR_RB 0x401100C5
849 #define PVR_405CR_RC 0x40110145 /* same as pc405gp rev e */
850 #define PVR_405EP_RA 0x51210950
851 #define PVR_405GPR_RB 0x50910951
852 #define PVR_405EZ_RA 0x41511460
853 #define PVR_405EXR1_RA 0x12911473 /* 405EXr rev A/B with Security */
854 #define PVR_405EXR2_RA 0x12911471 /* 405EXr rev A/B without Security */
855 #define PVR_405EX1_RA 0x12911477 /* 405EX rev A/B with Security */
856 #define PVR_405EX2_RA 0x12911475 /* 405EX rev A/B without Security */
857 #define PVR_405EXR1_RC 0x1291147B /* 405EXr rev C with Security */
858 #define PVR_405EXR2_RC 0x12911479 /* 405EXr rev C without Security */
859 #define PVR_405EX1_RC 0x1291147F /* 405EX rev C with Security */
860 #define PVR_405EX2_RC 0x1291147D /* 405EX rev C without Security */
861 #define PVR_440GP_RB 0x40120440
862 #define PVR_440GP_RC 0x40120481
863 #define PVR_440EP_RA 0x42221850
864 #define PVR_440EP_RB 0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */
865 #define PVR_440EP_RC 0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */
866 #define PVR_440GR_RA 0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */
867 #define PVR_440GR_RB 0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */
868 #define PVR_440EPX1_RA 0x216218D0 /* 440EPX rev A with Security / Kasumi */
869 #define PVR_440EPX2_RA 0x216218D4 /* 440EPX rev A without Security / Kasumi */
870 #define PVR_440GRX1_RA 0x216218D0 /* 440GRX rev A with Security / Kasumi */
871 #define PVR_440GRX2_RA 0x216218D4 /* 440GRX rev A without Security / Kasumi */
872 #define PVR_440GX_RA 0x51B21850
873 #define PVR_440GX_RB 0x51B21851
874 #define PVR_440GX_RC 0x51B21892
875 #define PVR_440GX_RF 0x51B21894
876 #define PVR_405EP_RB 0x51210950
877 #define PVR_440SP_6_RAB 0x53221850 /* 440SP rev A&B with RAID 6 support enabled */
878 #define PVR_440SP_RAB 0x53321850 /* 440SP rev A&B without RAID 6 support */
879 #define PVR_440SP_6_RC 0x53221891 /* 440SP rev C with RAID 6 support enabled */
880 #define PVR_440SP_RC 0x53321891 /* 440SP rev C without RAID 6 support */
881 #define PVR_440SPe_6_RA 0x53421890 /* 440SPe rev A with RAID 6 support enabled */
882 #define PVR_440SPe_RA 0x53521890 /* 440SPe rev A without RAID 6 support */
883 #define PVR_440SPe_6_RB 0x53421891 /* 440SPe rev B with RAID 6 support enabled */
884 #define PVR_440SPe_RB 0x53521891 /* 440SPe rev B without RAID 6 support */
885 #define PVR_460EX_SE_RA 0x130218A2 /* 460EX rev A with Security Engine */
886 #define PVR_460EX_RA 0x130218A3 /* 460EX rev A without Security Engine */
887 #define PVR_460GT_SE_RA 0x130218A0 /* 460GT rev A with Security Engine */
888 #define PVR_460GT_RA 0x130218A1 /* 460GT rev A without Security Engine */
889 #define PVR_460SX_RA 0x13541800 /* 460SX rev A */
890 #define PVR_460SX_RA_V1 0x13541801 /* 460SX rev A Variant 1 Security disabled */
891 #define PVR_460GX_RA 0x13541802 /* 460GX rev A */
892 #define PVR_460GX_RA_V1 0x13541803 /* 460GX rev A Variant 1 Security disabled */
893 #define PVR_601 0x00010000
894 #define PVR_602 0x00050000
895 #define PVR_603 0x00030000
896 #define PVR_603e 0x00060000
897 #define PVR_603ev 0x00070000
898 #define PVR_603r 0x00071000
899 #define PVR_604 0x00040000
900 #define PVR_604e 0x00090000
901 #define PVR_604r 0x000A0000
902 #define PVR_620 0x00140000
903 #define PVR_740 0x00080000
904 #define PVR_750 PVR_740
905 #define PVR_740P 0x10080000
906 #define PVR_750P PVR_740P
907 #define PVR_7400 0x000C0000
908 #define PVR_7410 0x800C0000
909 #define PVR_7450 0x80000000
910
911 #define PVR_85xx 0x80200000
912 #define PVR_85xx_REV1 (PVR_85xx | 0x0010)
913 #define PVR_85xx_REV2 (PVR_85xx | 0x0020)
914
915 #define PVR_86xx 0x80040000
916
917 #define PVR_VIRTEX5 0x7ff21912
918
919 /*
920 * For the 8xx processors, all of them report the same PVR family for
921 * the PowerPC core. The various versions of these processors must be
922 * differentiated by the version number in the Communication Processor
923 * Module (CPM).
924 */
925 #define PVR_821 0x00500000
926 #define PVR_823 PVR_821
927 #define PVR_850 PVR_821
928 #define PVR_860 PVR_821
929 #define PVR_7400 0x000C0000
930 #define PVR_8240 0x00810100
931
932 /*
933 * PowerQUICC II family processors report different PVR values depending
934 * on silicon process (HiP3, HiP4, HiP7, etc.)
935 */
936 #define PVR_8260 PVR_8240
937 #define PVR_8260_HIP3 0x00810101
938 #define PVR_8260_HIP4 0x80811014
939 #define PVR_8260_HIP7 0x80822011
940 #define PVR_8260_HIP7R1 0x80822013
941 #define PVR_8260_HIP7RA 0x80822014
942
943 /*
944 * MPC 52xx
945 */
946 #define PVR_5200 0x80822011
947 #define PVR_5200B 0x80822014
948
949 /*
950 * System Version Register
951 */
952
953 /* System Version Register (SVR) field extraction */
954
955 #define SVR_VER(svr) (((svr) >> 16) & 0xFFFF) /* Version field */
956 #define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revison field */
957
958 #define SVR_SUBVER(svr) (((svr) >> 8) & 0xFF) /* Process/MFG sub-version */
959
960 #define SVR_FAM(svr) (((svr) >> 20) & 0xFFF) /* Family field */
961 #define SVR_MEM(svr) (((svr) >> 16) & 0xF) /* Member field */
962
963 #define SVR_MAJ(svr) (((svr) >> 4) & 0xF) /* Major revision field*/
964 #define SVR_MIN(svr) (((svr) >> 0) & 0xF) /* Minor revision field*/
965
966 /* Some parts define SVR[0:23] as the SOC version */
967 #define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFFFFF) /* SOC Version fields */
968
969 /* whether MPC8xxxE (i.e. has SEC) */
970 #if defined(CONFIG_MPC85xx)
971 #define IS_E_PROCESSOR(svr) (svr & 0x80000)
972 #else
973 #if defined(CONFIG_MPC83xx)
974 #define IS_E_PROCESSOR(spridr) (!(spridr & 0x00010000))
975 #endif
976 #endif
977
978 /*
979 * SVR_SOC_VER() Version Values
980 */
981
982 #define SVR_8533 0x803400
983 #define SVR_8533_E 0x803C00
984 #define SVR_8535 0x803701
985 #define SVR_8535_E 0x803F01
986 #define SVR_8536 0x803700
987 #define SVR_8536_E 0x803F00
988 #define SVR_8540 0x803000
989 #define SVR_8541 0x807200
990 #define SVR_8541_E 0x807A00
991 #define SVR_8543 0x803200
992 #define SVR_8543_E 0x803A00
993 #define SVR_8544 0x803401
994 #define SVR_8544_E 0x803C01
995 #define SVR_8545 0x803102
996 #define SVR_8545_E 0x803902
997 #define SVR_8547_E 0x803901
998 #define SVR_8548 0x803100
999 #define SVR_8548_E 0x803900
1000 #define SVR_8555 0x807100
1001 #define SVR_8555_E 0x807900
1002 #define SVR_8560 0x807000
1003 #define SVR_8567 0x807600
1004 #define SVR_8567_E 0x807E00
1005 #define SVR_8568 0x807500
1006 #define SVR_8568_E 0x807D00
1007 #define SVR_8569 0x808000
1008 #define SVR_8569_E 0x808800
1009 #define SVR_8572 0x80E000
1010 #define SVR_8572_E 0x80E800
1011 #define SVR_P2020 0x80E200
1012 #define SVR_P2020_E 0x80EA00
1013
1014 #define SVR_8610 0x80A000
1015 #define SVR_8641 0x809000
1016 #define SVR_8641D 0x809001
1017
1018 #define _GLOBAL(n)\
1019 .globl n;\
1020 n:
1021
1022 /* Macros for setting and retrieving special purpose registers */
1023
1024 #define stringify(s) tostring(s)
1025 #define tostring(s) #s
1026
1027 #define mfdcr(rn) ({unsigned int rval; \
1028 asm volatile("mfdcr %0," stringify(rn) \
1029 : "=r" (rval)); rval;})
1030 #define mtdcr(rn, v) asm volatile("mtdcr " stringify(rn) ",%0" : : "r" (v))
1031
1032 #define mfmsr() ({unsigned int rval; \
1033 asm volatile("mfmsr %0" : "=r" (rval)); rval;})
1034 #define mtmsr(v) asm volatile("mtmsr %0" : : "r" (v))
1035
1036 #define mfspr(rn) ({unsigned int rval; \
1037 asm volatile("mfspr %0," stringify(rn) \
1038 : "=r" (rval)); rval;})
1039 #define mtspr(rn, v) asm volatile("mtspr " stringify(rn) ",%0" : : "r" (v))
1040
1041 #define tlbie(v) asm volatile("tlbie %0 \n sync" : : "r" (v))
1042
1043 /* Segment Registers */
1044
1045 #define SR0 0
1046 #define SR1 1
1047 #define SR2 2
1048 #define SR3 3
1049 #define SR4 4
1050 #define SR5 5
1051 #define SR6 6
1052 #define SR7 7
1053 #define SR8 8
1054 #define SR9 9
1055 #define SR10 10
1056 #define SR11 11
1057 #define SR12 12
1058 #define SR13 13
1059 #define SR14 14
1060 #define SR15 15
1061
1062 #ifndef __ASSEMBLY__
1063
1064 struct cpu_type {
1065 char name[15];
1066 u32 soc_ver;
1067 };
1068
1069 struct cpu_type *identify_cpu(u32 ver);
1070
1071 #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
1072 #define CPU_TYPE_ENTRY(n, v) \
1073 { .name = #n, .soc_ver = SVR_##v, }
1074 #else
1075 #if defined(CONFIG_MPC83xx)
1076 #define CPU_TYPE_ENTRY(x) {#x, SPR_##x}
1077 #endif
1078 #endif
1079
1080
1081 #ifndef CONFIG_MACH_SPECIFIC
1082 extern int _machine;
1083 extern int have_of;
1084 #endif /* CONFIG_MACH_SPECIFIC */
1085
1086 /* what kind of prep workstation we are */
1087 extern int _prep_type;
1088 /*
1089 * This is used to identify the board type from a given PReP board
1090 * vendor. Board revision is also made available.
1091 */
1092 extern unsigned char ucSystemType;
1093 extern unsigned char ucBoardRev;
1094 extern unsigned char ucBoardRevMaj, ucBoardRevMin;
1095
1096 struct task_struct;
1097 void start_thread(struct pt_regs *regs, unsigned long nip, unsigned long sp);
1098 void release_thread(struct task_struct *);
1099
1100 /*
1101 * Create a new kernel thread.
1102 */
1103 extern long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
1104
1105 /*
1106 * Bus types
1107 */
1108 #define EISA_bus 0
1109 #define EISA_bus__is_a_macro /* for versions in ksyms.c */
1110 #define MCA_bus 0
1111 #define MCA_bus__is_a_macro /* for versions in ksyms.c */
1112
1113 /* Lazy FPU handling on uni-processor */
1114 extern struct task_struct *last_task_used_math;
1115 extern struct task_struct *last_task_used_altivec;
1116
1117 /*
1118 * this is the minimum allowable io space due to the location
1119 * of the io areas on prep (first one at 0x80000000) but
1120 * as soon as I get around to remapping the io areas with the BATs
1121 * to match the mac we can raise this. -- Cort
1122 */
1123 #define TASK_SIZE (0x80000000UL)
1124
1125 /* This decides where the kernel will search for a free chunk of vm
1126 * space during mmap's.
1127 */
1128 #define TASK_UNMAPPED_BASE (TASK_SIZE / 8 * 3)
1129
1130 typedef struct {
1131 unsigned long seg;
1132 } mm_segment_t;
1133
1134 struct thread_struct {
1135 unsigned long ksp; /* Kernel stack pointer */
1136 unsigned long wchan; /* Event task is sleeping on */
1137 struct pt_regs *regs; /* Pointer to saved register state */
1138 mm_segment_t fs; /* for get_fs() validation */
1139 void *pgdir; /* root of page-table tree */
1140 signed long last_syscall;
1141 double fpr[32]; /* Complete floating point set */
1142 unsigned long fpscr_pad; /* fpr ... fpscr must be contiguous */
1143 unsigned long fpscr; /* Floating point status */
1144 #ifdef CONFIG_ALTIVEC
1145 vector128 vr[32]; /* Complete AltiVec set */
1146 vector128 vscr; /* AltiVec status */
1147 unsigned long vrsave;
1148 #endif /* CONFIG_ALTIVEC */
1149 };
1150
1151 #define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack)
1152
1153 #define INIT_THREAD { \
1154 INIT_SP, /* ksp */ \
1155 0, /* wchan */ \
1156 (struct pt_regs *)INIT_SP - 1, /* regs */ \
1157 KERNEL_DS, /*fs*/ \
1158 swapper_pg_dir, /* pgdir */ \
1159 0, /* last_syscall */ \
1160 {0}, 0, 0 \
1161 }
1162
1163 /*
1164 * Note: the vm_start and vm_end fields here should *not*
1165 * be in kernel space. (Could vm_end == vm_start perhaps?)
1166 */
1167 #define INIT_MMAP { &init_mm, 0, 0x1000, NULL, \
1168 PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, \
1169 1, NULL, NULL }
1170
1171 /*
1172 * Return saved PC of a blocked thread. For now, this is the "user" PC
1173 */
thread_saved_pc(struct thread_struct * t)1174 static inline unsigned long thread_saved_pc(struct thread_struct *t)
1175 {
1176 return (t->regs) ? t->regs->nip : 0;
1177 }
1178
1179 #define copy_segments(tsk, mm) do { } while (0)
1180 #define release_segments(mm) do { } while (0)
1181 #define forget_segments() do { } while (0)
1182
1183 unsigned long get_wchan(struct task_struct *p);
1184
1185 #define KSTK_EIP(tsk) ((tsk)->thread.regs->nip)
1186 #define KSTK_ESP(tsk) ((tsk)->thread.regs->gpr[1])
1187
1188 /*
1189 * NOTE! The task struct and the stack go together
1190 */
1191 #define THREAD_SIZE (2*PAGE_SIZE)
1192 #define alloc_task_struct() \
1193 ((struct task_struct *) __get_free_pages(GFP_KERNEL,1))
1194 #define free_task_struct(p) free_pages((unsigned long)(p),1)
1195 #define get_task_struct(tsk) atomic_inc(&mem_map[MAP_NR(tsk)].count)
1196
1197 /* in process.c - for early bootup debug -- Cort */
1198 int ll_printk(const char *, ...);
1199 void ll_puts(const char *);
1200
1201 #define init_task (init_task_union.task)
1202 #define init_stack (init_task_union.stack)
1203
1204 /* In misc.c */
1205 void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
1206
1207 #endif /* ndef ASSEMBLY*/
1208
1209 #ifdef CONFIG_MACH_SPECIFIC
1210 #if defined(CONFIG_8xx)
1211 #define _machine _MACH_8xx
1212 #define have_of 0
1213 #elif defined(CONFIG_OAK)
1214 #define _machine _MACH_oak
1215 #define have_of 0
1216 #elif defined(CONFIG_WALNUT)
1217 #define _machine _MACH_walnut
1218 #define have_of 0
1219 #elif defined(CONFIG_APUS)
1220 #define _machine _MACH_apus
1221 #define have_of 0
1222 #elif defined(CONFIG_GEMINI)
1223 #define _machine _MACH_gemini
1224 #define have_of 0
1225 #elif defined(CONFIG_8260)
1226 #define _machine _MACH_8260
1227 #define have_of 0
1228 #elif defined(CONFIG_SANDPOINT)
1229 #define _machine _MACH_sandpoint
1230 #elif defined(CONFIG_HIDDEN_DRAGON)
1231 #define _machine _MACH_hidden_dragon
1232 #define have_of 0
1233 #else
1234 #error "Machine not defined correctly"
1235 #endif
1236 #endif /* CONFIG_MACH_SPECIFIC */
1237
1238 #endif /* __ASM_PPC_PROCESSOR_H */
1239