1 /** @file reg_mibspi.h 2 * @brief MIBSPI Register Layer Header File 3 * @date 29.May.2013 4 * @version 03.05.02 5 * 6 * This file contains: 7 * - Definitions 8 * - Types 9 * - Interface Prototypes 10 * . 11 * which are relevant for the MIBSPI driver. 12 */ 13 14 /* (c) Texas Instruments 2009-2013, All rights reserved. */ 15 16 #ifndef __REG_MIBSPI_H__ 17 #define __REG_MIBSPI_H__ 18 19 #include "sys_common.h" 20 #include "gio.h" 21 22 23 24 /* USER CODE BEGIN (0) */ 25 /* USER CODE END */ 26 27 /* Mibspi Register Frame Definition */ 28 /** @struct mibspiBase 29 * @brief MIBSPI Register Definition 30 * 31 * This structure is used to access the MIBSPI module registers. 32 */ 33 /** @typedef mibspiBASE_t 34 * @brief MIBSPI Register Frame Type Definition 35 * 36 * This type is used to access the MIBSPI Registers. 37 */ 38 typedef volatile struct mibspiBase 39 { 40 uint32 GCR0; /**< 0x0000: Global Control 0 */ 41 uint32 GCR1; /**< 0x0004: Global Control 1 */ 42 uint32 INT0; /**< 0x0008: Interrupt Register */ 43 uint32 LVL; /**< 0x000C: Interrupt Level */ 44 uint32 FLG; /**< 0x0010: Interrupt flags */ 45 uint32 PCFUN; /**< 0x0014: Function Pin Enable */ 46 uint32 PCDIR; /**< 0x0018: Pin Direction */ 47 uint32 PCDIN; /**< 0x001C: Pin Input Latch */ 48 uint32 PCDOUT; /**< 0x0020: Pin Output Latch */ 49 uint32 PCSET; /**< 0x0024: Output Pin Set */ 50 uint32 PCCLR; /**< 0x0028: Output Pin Clr */ 51 uint32 PCPDR; /**< 0x002C: Open Drain Output Enable */ 52 uint32 PCDIS; /**< 0x0030: Pullup/Pulldown Disable */ 53 uint32 PCPSL; /**< 0x0034: Pullup/Pulldown Selection */ 54 uint32 DAT0; /**< 0x0038: Transmit Data */ 55 uint32 DAT1; /**< 0x003C: Transmit Data with Format and Chip Select */ 56 uint32 BUF; /**< 0x0040: Receive Buffer */ 57 uint32 EMU; /**< 0x0044: Emulation Receive Buffer */ 58 uint32 DELAY; /**< 0x0048: Delays */ 59 uint32 CSDEF; /**< 0x004C: Default Chip Select */ 60 uint32 FMT0; /**< 0x0050: Data Format 0 */ 61 uint32 FMT1; /**< 0x0054: Data Format 1 */ 62 uint32 FMT2; /**< 0x0058: Data Format 2 */ 63 uint32 FMT3; /**< 0x005C: Data Format 3 */ 64 uint32 INTVECT0; /**< 0x0060: Interrupt Vector 0 */ 65 uint32 INTVECT1; /**< 0x0064: Interrupt Vector 1 */ 66 uint32 SRSEL; /**< 0x0068: Slew Rate Select */ 67 uint32 PMCTRL; /**< 0x006C: Parallel Mode Control */ 68 uint32 MIBSPIE; /**< 0x0070: Multi-buffer Mode Enable */ 69 uint32 TGITENST; /**< 0x0074: TG Interrupt Enable Set */ 70 uint32 TGITENCR; /**< 0x0078: TG Interrupt Enable Clear */ 71 uint32 TGITLVST; /**< 0x007C: Transfer Group Interrupt Level Set */ 72 uint32 TGITLVCR; /**< 0x0080: Transfer Group Interrupt Level Clear */ 73 uint32 TGINTFLG; /**< 0x0084: Transfer Group Interrupt Flag */ 74 uint32 rsvd1[2U]; /**< 0x0088: Reserved */ 75 uint32 TICKCNT; /**< 0x0090: Tick Counter */ 76 uint32 LTGPEND; /**< 0x0090: Last TG End Pointer */ 77 uint32 TGCTRL[16U]; /**< 0x0098 - 0x00D4: Transfer Group Control */ 78 uint32 DMACTRL[8U]; /**< 0x00D8 - 0x00F4: DMA Control */ 79 uint32 DMACOUNT[8U]; /**< 0x00F8 - 0x0114: DMA Count */ 80 uint32 DMACNTLEN; /**< 0x0118 - 0x0114: DMA Control length */ 81 uint32 rsvd2; /**< 0x011C: Reserved */ 82 uint32 UERRCTRL; /**< 0x0120: Multi-buffer RAM Uncorrectable Parity Error Control */ 83 uint32 UERRSTAT; /**< 0x0124: Multi-buffer RAM Uncorrectable Parity Error Status */ 84 uint32 UERRADDRRX; /**< 0x0128: RXRAM Uncorrectable Parity Error Address */ 85 uint32 UERRADDRTX; /**< 0x012C: TXRAM Uncorrectable Parity Error Address */ 86 uint32 RXOVRN_BUF_ADDR; /**< 0x0130: RXRAM Overrun Buffer Address */ 87 uint32 IOLPKTSTCR; /**< 0x0134: IO loopback */ 88 uint32 EXT_PRESCALE1; /**< 0x0138: */ 89 uint32 EXT_PRESCALE2; /**< 0x013C: */ 90 } mibspiBASE_t; 91 92 93 /** @def mibspiREG1 94 * @brief MIBSPI1 Register Frame Pointer 95 * 96 * This pointer is used by the MIBSPI driver to access the mibspi module registers. 97 */ 98 #define mibspiREG1 ((mibspiBASE_t *)0xFFF7F400U) 99 100 101 /** @def mibspiPORT1 102 * @brief MIBSPI1 GIO Port Register Pointer 103 * 104 * Pointer used by the GIO driver to access I/O PORT of MIBSPI1 105 * (use the GIO drivers to access the port pins). 106 */ 107 #define mibspiPORT1 ((gioPORT_t *)0xFFF7F418U) 108 109 /** @def mibspiREG3 110 * @brief MIBSPI3 Register Frame Pointer 111 * 112 * This pointer is used by the MIBSPI driver to access the mibspi module registers. 113 */ 114 #define mibspiREG3 ((mibspiBASE_t *)0xFFF7F800U) 115 116 117 /** @def mibspiPORT3 118 * @brief MIBSPI3 GIO Port Register Pointer 119 * 120 * Pointer used by the GIO driver to access I/O PORT of MIBSPI3 121 * (use the GIO drivers to access the port pins). 122 */ 123 #define mibspiPORT3 ((gioPORT_t *)0xFFF7F818U) 124 125 /** @def mibspiREG5 126 * @brief MIBSPI5 Register Frame Pointer 127 * 128 * This pointer is used by the MIBSPI driver to access the mibspi module registers. 129 */ 130 #define mibspiREG5 ((mibspiBASE_t *)0xFFF7FC00U) 131 132 133 /** @def mibspiPORT5 134 * @brief MIBSPI5 GIO Port Register Pointer 135 * 136 * Pointer used by the GIO driver to access I/O PORT of MIBSPI5 137 * (use the GIO drivers to access the port pins). 138 */ 139 #define mibspiPORT5 ((gioPORT_t *)0xFFF7FC18U) 140 141 142 /** @struct mibspiRamBase 143 * @brief MIBSPI Buffer RAM Definition 144 * 145 * This structure is used to access the MIBSPI buffer memory. 146 */ 147 /** @typedef mibspiRAM_t 148 * @brief MIBSPI RAM Type Definition 149 * 150 * This type is used to access the MIBSPI RAM. 151 */ 152 typedef volatile struct mibspiRamBase 153 { 154 struct 155 { 156 #if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1)) 157 uint16 data; /**< tx buffer data */ 158 uint16 control; /**< tx buffer control */ 159 #else 160 uint16 control; /**< tx buffer control */ 161 uint16 data; /**< tx buffer data */ 162 #endif 163 } tx[128]; 164 struct 165 { 166 #if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1)) 167 uint16 data; /**< rx buffer data */ 168 uint16 flags; /**< rx buffer flags */ 169 #else 170 uint16 flags; /**< rx buffer flags */ 171 uint16 data; /**< rx buffer data */ 172 #endif 173 } rx[128]; 174 } mibspiRAM_t; 175 176 177 /** @def mibspiRAM1 178 * @brief MIBSPI1 Buffer RAM Pointer 179 * 180 * This pointer is used by the MIBSPI driver to access the mibspi buffer memory. 181 */ 182 #define mibspiRAM1 ((mibspiRAM_t *)0xFF0E0000U) 183 184 /** @def mibspiRAM3 185 * @brief MIBSPI3 Buffer RAM Pointer 186 * 187 * This pointer is used by the MIBSPI driver to access the mibspi buffer memory. 188 */ 189 #define mibspiRAM3 ((mibspiRAM_t *)0xFF0C0000U) 190 191 /** @def mibspiRAM5 192 * @brief MIBSPI5 Buffer RAM Pointer 193 * 194 * This pointer is used by the MIBSPI driver to access the mibspi buffer memory. 195 */ 196 #define mibspiRAM5 ((mibspiRAM_t *)0xFF0A0000U) 197 198 /** @def mibspiPARRAM1 199 * @brief MIBSPI1 Buffer RAM PARITY Pointer 200 * 201 * This pointer is used by the MIBSPI driver to access the mibspi buffer memory. 202 */ 203 #define mibspiPARRAM1 (*(volatile uint32 *)(0xFF0E0000U + 0x00000400U)) 204 205 /** @def mibspiPARRAM3 206 * @brief MIBSPI3 Buffer RAM PARITY Pointer 207 * 208 * This pointer is used by the MIBSPI driver to access the mibspi buffer memory. 209 */ 210 #define mibspiPARRAM3 (*(volatile uint32 *)(0xFF0C0000U + 0x00000400U)) 211 212 213 /** @def mibspiPARRAM5 214 * @brief MIBSPI5 Buffer RAM PARITY Pointer 215 * 216 * This pointer is used by the MIBSPI driver to access the mibspi buffer memory. 217 */ 218 #define mibspiPARRAM5 (*(volatile uint32 *)(0xFF0A0000U + 0x00000400U)) 219 220 /* USER CODE BEGIN (1) */ 221 /* USER CODE END */ 222 223 224 #endif 225