1 /* 2 * Copyright (c) 2015, Freescale Semiconductor, Inc. 3 * Copyright 2016-2017 NXP 4 * All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef _FSL_SPECIFICATION_H_ 10 #define _FSL_SPECIFICATION_H_ 11 12 #include <stdint.h> 13 14 /******************************************************************************* 15 * Definitions 16 ******************************************************************************/ 17 /*! @brief SD/MMC card initialization clock frequency */ 18 #define SDMMC_CLOCK_400KHZ (400000U) 19 /*! @brief SD card bus frequency 1 in high-speed mode */ 20 #define SD_CLOCK_25MHZ (25000000U) 21 /*! @brief SD card bus frequency 2 in high-speed mode */ 22 #define SD_CLOCK_50MHZ (50000000U) 23 /*! @brief SD card bus frequency in SDR50 mode */ 24 #define SD_CLOCK_100MHZ (100000000U) 25 /*! @brief SD card bus frequency in SDR104 mode */ 26 #define SD_CLOCK_208MHZ (208000000U) 27 /*! @brief MMC card bus frequency 1 in high-speed mode */ 28 #define MMC_CLOCK_26MHZ (26000000U) 29 /*! @brief MMC card bus frequency 2 in high-speed mode */ 30 #define MMC_CLOCK_52MHZ (52000000U) 31 /*! @brief MMC card bus frequency in high-speed DDR52 mode */ 32 #define MMC_CLOCK_DDR52 (104000000U) 33 /*! @brief MMC card bus frequency in high-speed HS200 mode */ 34 #define MMC_CLOCK_HS200 (200000000U) 35 /*! @brief MMC card bus frequency in high-speed HS400 mode */ 36 #define MMC_CLOCK_HS400 (400000000U) 37 38 /*! @brief Card status bit in R1 */ 39 enum _sdmmc_r1_card_status_flag 40 { 41 kSDMMC_R1OutOfRangeFlag = (1U << 31U), /*!< Out of range status bit */ 42 kSDMMC_R1AddressErrorFlag = (1U << 30U), /*!< Address error status bit */ 43 kSDMMC_R1BlockLengthErrorFlag = (1U << 29U), /*!< Block length error status bit */ 44 kSDMMC_R1EraseSequenceErrorFlag = (1U << 28U), /*!< Erase sequence error status bit */ 45 kSDMMC_R1EraseParameterErrorFlag = (1U << 27U), /*!< Erase parameter error status bit */ 46 kSDMMC_R1WriteProtectViolationFlag = (1U << 26U), /*!< Write protection violation status bit */ 47 kSDMMC_R1CardIsLockedFlag = (1U << 25U), /*!< Card locked status bit */ 48 kSDMMC_R1LockUnlockFailedFlag = (1U << 24U), /*!< lock/unlock error status bit */ 49 kSDMMC_R1CommandCrcErrorFlag = (1U << 23U), /*!< CRC error status bit */ 50 kSDMMC_R1IllegalCommandFlag = (1U << 22U), /*!< Illegal command status bit */ 51 kSDMMC_R1CardEccFailedFlag = (1U << 21U), /*!< Card ecc error status bit */ 52 kSDMMC_R1CardControllerErrorFlag = (1U << 20U), /*!< Internal card controller error status bit */ 53 kSDMMC_R1ErrorFlag = (1U << 19U), /*!< A general or an unknown error status bit */ 54 kSDMMC_R1CidCsdOverwriteFlag = (1U << 16U), /*!< Cid/csd overwrite status bit */ 55 kSDMMC_R1WriteProtectEraseSkipFlag = (1U << 15U), /*!< Write protection erase skip status bit */ 56 kSDMMC_R1CardEccDisabledFlag = (1U << 14U), /*!< Card ecc disabled status bit */ 57 kSDMMC_R1EraseResetFlag = (1U << 13U), /*!< Erase reset status bit */ 58 kSDMMC_R1ReadyForDataFlag = (1U << 8U), /*!< Ready for data status bit */ 59 kSDMMC_R1SwitchErrorFlag = (1U << 7U), /*!< Switch error status bit */ 60 kSDMMC_R1ApplicationCommandFlag = (1U << 5U), /*!< Application command enabled status bit */ 61 kSDMMC_R1AuthenticationSequenceErrorFlag = (1U << 3U), /*!< error in the sequence of authentication process */ 62 63 kSDMMC_R1ErrorAllFlag = 64 (kSDMMC_R1OutOfRangeFlag | kSDMMC_R1AddressErrorFlag | kSDMMC_R1BlockLengthErrorFlag | 65 kSDMMC_R1EraseSequenceErrorFlag | kSDMMC_R1EraseParameterErrorFlag | kSDMMC_R1WriteProtectViolationFlag | 66 kSDMMC_R1CardIsLockedFlag | kSDMMC_R1LockUnlockFailedFlag | kSDMMC_R1CommandCrcErrorFlag | 67 kSDMMC_R1IllegalCommandFlag | kSDMMC_R1CardEccFailedFlag | kSDMMC_R1CardControllerErrorFlag | 68 kSDMMC_R1ErrorFlag | kSDMMC_R1CidCsdOverwriteFlag | 69 kSDMMC_R1AuthenticationSequenceErrorFlag), /*!< Card error status */ 70 }; 71 72 /*! @brief R1: current state */ 73 #define SDMMC_R1_CURRENT_STATE(x) (((x)&0x00001E00U) >> 9U) 74 75 /*! @brief CURRENT_STATE filed in R1 */ 76 typedef enum _sdmmc_r1_current_state 77 { 78 kSDMMC_R1StateIdle = 0U, /*!< R1: current state: idle */ 79 kSDMMC_R1StateReady = 1U, /*!< R1: current state: ready */ 80 kSDMMC_R1StateIdentify = 2U, /*!< R1: current state: identification */ 81 kSDMMC_R1StateStandby = 3U, /*!< R1: current state: standby */ 82 kSDMMC_R1StateTransfer = 4U, /*!< R1: current state: transfer */ 83 kSDMMC_R1StateSendData = 5U, /*!< R1: current state: sending data */ 84 kSDMMC_R1StateReceiveData = 6U, /*!< R1: current state: receiving data */ 85 kSDMMC_R1StateProgram = 7U, /*!< R1: current state: programming */ 86 kSDMMC_R1StateDisconnect = 8U, /*!< R1: current state: disconnect */ 87 } sdmmc_r1_current_state_t; 88 89 /*! @brief Error bit in SPI mode R1 */ 90 enum _sdspi_r1_error_status_flag 91 { 92 kSDSPI_R1InIdleStateFlag = (1U << 0U), /*!< In idle state */ 93 kSDSPI_R1EraseResetFlag = (1U << 1U), /*!< Erase reset */ 94 kSDSPI_R1IllegalCommandFlag = (1U << 2U), /*!< Illegal command */ 95 kSDSPI_R1CommandCrcErrorFlag = (1U << 3U), /*!< Com crc error */ 96 kSDSPI_R1EraseSequenceErrorFlag = (1U << 4U), /*!< Erase sequence error */ 97 kSDSPI_R1AddressErrorFlag = (1U << 5U), /*!< Address error */ 98 kSDSPI_R1ParameterErrorFlag = (1U << 6U), /*!< Parameter error */ 99 }; 100 101 /*! @brief Error bit in SPI mode R2 */ 102 enum _sdspi_r2_error_status_flag 103 { 104 kSDSPI_R2CardLockedFlag = (1U << 0U), /*!< Card is locked */ 105 kSDSPI_R2WriteProtectEraseSkip = (1U << 1U), /*!< Write protect erase skip */ 106 kSDSPI_R2LockUnlockFailed = (1U << 1U), /*!< Lock/unlock command failed */ 107 kSDSPI_R2ErrorFlag = (1U << 2U), /*!< Unknown error */ 108 kSDSPI_R2CardControllerErrorFlag = (1U << 3U), /*!< Card controller error */ 109 kSDSPI_R2CardEccFailedFlag = (1U << 4U), /*!< Card ecc failed */ 110 kSDSPI_R2WriteProtectViolationFlag = (1U << 5U), /*!< Write protect violation */ 111 kSDSPI_R2EraseParameterErrorFlag = (1U << 6U), /*!< Erase parameter error */ 112 kSDSPI_R2OutOfRangeFlag = (1U << 7U), /*!< Out of range */ 113 kSDSPI_R2CsdOverwriteFlag = (1U << 7U), /*!< CSD overwrite */ 114 }; 115 116 /*! @brief The bit mask for COMMAND VERSION field in R7 */ 117 #define SDSPI_R7_VERSION_SHIFT (28U) 118 /*! @brief The bit mask for COMMAND VERSION field in R7 */ 119 #define SDSPI_R7_VERSION_MASK (0xFU) 120 /*! @brief The bit shift for VOLTAGE ACCEPTED field in R7 */ 121 #define SDSPI_R7_VOLTAGE_SHIFT (8U) 122 /*! @brief The bit mask for VOLTAGE ACCEPTED field in R7 */ 123 #define SDSPI_R7_VOLTAGE_MASK (0xFU) 124 /*! @brief The bit mask for VOLTAGE 2.7V to 3.6V field in R7 */ 125 #define SDSPI_R7_VOLTAGE_27_36_MASK (0x1U << SDSPI_R7_VOLTAGE_SHIFT) 126 /*! @brief The bit shift for ECHO field in R7 */ 127 #define SDSPI_R7_ECHO_SHIFT (0U) 128 /*! @brief The bit mask for ECHO field in R7 */ 129 #define SDSPI_R7_ECHO_MASK (0xFFU) 130 131 /*! @brief Data error token mask */ 132 #define SDSPI_DATA_ERROR_TOKEN_MASK (0xFU) 133 /*! @brief Data Error Token mask bit */ 134 enum _sdspi_data_error_token 135 { 136 kSDSPI_DataErrorTokenError = (1U << 0U), /*!< Data error */ 137 kSDSPI_DataErrorTokenCardControllerError = (1U << 1U), /*!< Card controller error */ 138 kSDSPI_DataErrorTokenCardEccFailed = (1U << 2U), /*!< Card ecc error */ 139 kSDSPI_DataErrorTokenOutOfRange = (1U << 3U), /*!< Out of range */ 140 }; 141 142 /*! @brief Data Token */ 143 typedef enum _sdspi_data_token 144 { 145 kSDSPI_DataTokenBlockRead = 0xFEU, /*!< Single block read, multiple block read */ 146 kSDSPI_DataTokenSingleBlockWrite = 0xFEU, /*!< Single block write */ 147 kSDSPI_DataTokenMultipleBlockWrite = 0xFCU, /*!< Multiple block write */ 148 kSDSPI_DataTokenStopTransfer = 0xFDU, /*!< Stop transmission */ 149 } sdspi_data_token_t; 150 151 /* Data Response Token mask */ 152 #define SDSPI_DATA_RESPONSE_TOKEN_MASK (0x1FU) /*!< Mask for data response bits */ 153 /*! @brief Data Response Token */ 154 typedef enum _sdspi_data_response_token 155 { 156 kSDSPI_DataResponseTokenAccepted = 0x05U, /*!< Data accepted */ 157 kSDSPI_DataResponseTokenCrcError = 0x0BU, /*!< Data rejected due to CRC error */ 158 kSDSPI_DataResponseTokenWriteError = 0x0DU, /*!< Data rejected due to write error */ 159 } sdspi_data_response_token_t; 160 161 /*! @brief SD card individual commands */ 162 typedef enum _sd_command 163 { 164 kSD_SendRelativeAddress = 3U, /*!< Send Relative Address */ 165 kSD_Switch = 6U, /*!< Switch Function */ 166 kSD_SendInterfaceCondition = 8U, /*!< Send Interface Condition */ 167 kSD_VoltageSwitch = 11U, /*!< Voltage Switch */ 168 kSD_SpeedClassControl = 20U, /*!< Speed Class control */ 169 kSD_EraseWriteBlockStart = 32U, /*!< Write Block Start */ 170 kSD_EraseWriteBlockEnd = 33U, /*!< Write Block End */ 171 kSD_SendTuningBlock = 19U, /*!< Send Tuning Block */ 172 } sd_command_t; 173 174 /*! @brief SD card individual application commands */ 175 typedef enum _sd_application_command 176 { 177 kSD_ApplicationSetBusWdith = 6U, /*!< Set Bus Width */ 178 kSD_ApplicationStatus = 13U, /*!< Send SD status */ 179 kSD_ApplicationSendNumberWriteBlocks = 22U, /*!< Send Number Of Written Blocks */ 180 kSD_ApplicationSetWriteBlockEraseCount = 23U, /*!< Set Write Block Erase Count */ 181 kSD_ApplicationSendOperationCondition = 41U, /*!< Send Operation Condition */ 182 kSD_ApplicationSetClearCardDetect = 42U, /*!< Set Connnect/Disconnect pull up on detect pin */ 183 kSD_ApplicationSendScr = 51U, /*!< Send Scr */ 184 } sd_application_command_t; 185 186 /*! @brief SD card command class */ 187 enum _sdmmc_command_class 188 { 189 kSDMMC_CommandClassBasic = (1U << 0U), /*!< Card command class 0 */ 190 kSDMMC_CommandClassBlockRead = (1U << 2U), /*!< Card command class 2 */ 191 kSDMMC_CommandClassBlockWrite = (1U << 4U), /*!< Card command class 4 */ 192 kSDMMC_CommandClassErase = (1U << 5U), /*!< Card command class 5 */ 193 kSDMMC_CommandClassWriteProtect = (1U << 6U), /*!< Card command class 6 */ 194 kSDMMC_CommandClassLockCard = (1U << 7U), /*!< Card command class 7 */ 195 kSDMMC_CommandClassApplicationSpecific = (1U << 8U), /*!< Card command class 8 */ 196 kSDMMC_CommandClassInputOutputMode = (1U << 9U), /*!< Card command class 9 */ 197 kSDMMC_CommandClassSwitch = (1U << 10U), /*!< Card command class 10 */ 198 }; 199 200 /*! @brief OCR register in SD card */ 201 enum _sd_ocr_flag 202 { 203 kSD_OcrPowerUpBusyFlag = (1U << 31U), /*!< Power up busy status */ 204 kSD_OcrHostCapacitySupportFlag = (1U << 30U), /*!< Card capacity status */ 205 kSD_OcrCardCapacitySupportFlag = kSD_OcrHostCapacitySupportFlag, /*!< Card capacity status */ 206 kSD_OcrSwitch18RequestFlag = (1U << 24U), /*!< Switch to 1.8V request */ 207 kSD_OcrSwitch18AcceptFlag = kSD_OcrSwitch18RequestFlag, /*!< Switch to 1.8V accepted */ 208 kSD_OcrVdd27_28Flag = (1U << 15U), /*!< VDD 2.7-2.8 */ 209 kSD_OcrVdd28_29Flag = (1U << 16U), /*!< VDD 2.8-2.9 */ 210 kSD_OcrVdd29_30Flag = (1U << 17U), /*!< VDD 2.9-3.0 */ 211 kSD_OcrVdd30_31Flag = (1U << 18U), /*!< VDD 2.9-3.0 */ 212 kSD_OcrVdd31_32Flag = (1U << 19U), /*!< VDD 3.0-3.1 */ 213 kSD_OcrVdd32_33Flag = (1U << 20U), /*!< VDD 3.1-3.2 */ 214 kSD_OcrVdd33_34Flag = (1U << 21U), /*!< VDD 3.2-3.3 */ 215 kSD_OcrVdd34_35Flag = (1U << 22U), /*!< VDD 3.3-3.4 */ 216 kSD_OcrVdd35_36Flag = (1U << 23U), /*!< VDD 3.4-3.5 */ 217 }; 218 219 /*! @brief SD card specification version number */ 220 enum _sd_specification_version 221 { 222 kSD_SpecificationVersion1_0 = (1U << 0U), /*!< SD card version 1.0-1.01 */ 223 kSD_SpecificationVersion1_1 = (1U << 1U), /*!< SD card version 1.10 */ 224 kSD_SpecificationVersion2_0 = (1U << 2U), /*!< SD card version 2.00 */ 225 kSD_SpecificationVersion3_0 = (1U << 3U), /*!< SD card version 3.0 */ 226 }; 227 228 /*! @brief SD card bus width */ 229 typedef enum _sd_data_bus_width 230 { 231 kSD_DataBusWidth1Bit = 0U, /*!< SD data bus width 1-bit mode */ 232 kSD_DataBusWidth4Bit = 1U, /*!< SD data bus width 4-bit mode */ 233 } sd_data_bus_width_t; 234 235 /*! @brief SD card switch mode */ 236 typedef enum _sd_switch_mode 237 { 238 kSD_SwitchCheck = 0U, /*!< SD switch mode 0: check function */ 239 kSD_SwitchSet = 1U, /*!< SD switch mode 1: set function */ 240 } sd_switch_mode_t; 241 242 /*! @brief SD card CSD register flags */ 243 enum _sd_csd_flag 244 { 245 kSD_CsdReadBlockPartialFlag = (1U << 0U), /*!< Partial blocks for read allowed [79:79] */ 246 kSD_CsdWriteBlockMisalignFlag = (1U << 1U), /*!< Write block misalignment [78:78] */ 247 kSD_CsdReadBlockMisalignFlag = (1U << 2U), /*!< Read block misalignment [77:77] */ 248 kSD_CsdDsrImplementedFlag = (1U << 3U), /*!< DSR implemented [76:76] */ 249 kSD_CsdEraseBlockEnabledFlag = (1U << 4U), /*!< Erase single block enabled [46:46] */ 250 kSD_CsdWriteProtectGroupEnabledFlag = (1U << 5U), /*!< Write protect group enabled [31:31] */ 251 kSD_CsdWriteBlockPartialFlag = (1U << 6U), /*!< Partial blocks for write allowed [21:21] */ 252 kSD_CsdFileFormatGroupFlag = (1U << 7U), /*!< File format group [15:15] */ 253 kSD_CsdCopyFlag = (1U << 8U), /*!< Copy flag [14:14] */ 254 kSD_CsdPermanentWriteProtectFlag = (1U << 9U), /*!< Permanent write protection [13:13] */ 255 kSD_CsdTemporaryWriteProtectFlag = (1U << 10U), /*!< Temporary write protection [12:12] */ 256 }; 257 258 /*! @brief SD card SCR register flags */ 259 enum _sd_scr_flag 260 { 261 kSD_ScrDataStatusAfterErase = (1U << 0U), /*!< Data status after erases [55:55] */ 262 kSD_ScrSdSpecification3 = (1U << 1U), /*!< Specification version 3.00 or higher [47:47]*/ 263 }; 264 265 /*! @brief SD timing function number */ 266 enum _sd_timing_function 267 { 268 kSD_FunctionSDR12Deafult = 0U, /*!< SDR12 mode & default*/ 269 kSD_FunctionSDR25HighSpeed = 1U, /*!< SDR25 & high speed*/ 270 kSD_FunctionSDR50 = 2U, /*!< SDR50 mode*/ 271 kSD_FunctionSDR104 = 3U, /*!< SDR104 mode*/ 272 kSD_FunctionDDR50 = 4U, /*!< DDR50 mode*/ 273 }; 274 275 /*! @brief SD group number */ 276 enum _sd_group_num 277 { 278 kSD_GroupTimingMode = 0U, /*!< acess mode group*/ 279 kSD_GroupCommandSystem = 1U, /*!< command system group*/ 280 kSD_GroupDriverStrength = 2U, /*!< driver strength group*/ 281 kSD_GroupCurrentLimit = 3U, /*!< current limit group*/ 282 }; 283 284 /*! @brief SD card timing mode flags */ 285 typedef enum _sd_timing_mode 286 { 287 kSD_TimingSDR12DefaultMode = 0U, /*!< Identification mode & SDR12 */ 288 kSD_TimingSDR25HighSpeedMode = 1U, /*!< High speed mode & SDR25 */ 289 kSD_TimingSDR50Mode = 2U, /*!< SDR50 mode*/ 290 kSD_TimingSDR104Mode = 3U, /*!< SDR104 mode */ 291 kSD_TimingDDR50Mode = 4U, /*!< DDR50 mode */ 292 } sd_timing_mode_t; 293 294 /*! @brief SD card driver strength */ 295 typedef enum _sd_driver_strength 296 { 297 kSD_DriverStrengthTypeB = 0U, /*!< default driver strength*/ 298 kSD_DriverStrengthTypeA = 1U, /*!< driver strength TYPE A */ 299 kSD_DriverStrengthTypeC = 2U, /*!< driver strength TYPE C */ 300 kSD_DriverStrengthTypeD = 3U, /*!< driver strength TYPE D */ 301 } sd_driver_strength_t; 302 303 /*! @brief SD card current limit */ 304 typedef enum _sd_max_current 305 { 306 kSD_CurrentLimit200MA = 0U, /*!< default current limit */ 307 kSD_CurrentLimit400MA = 1U, /*!< current limit to 400MA */ 308 kSD_CurrentLimit600MA = 2U, /*!< current limit to 600MA */ 309 kSD_CurrentLimit800MA = 3U, /*!< current limit to 800MA */ 310 } sd_max_current_t; 311 312 /*! @brief SD/MMC card common commands */ 313 typedef enum _sdmmc_command 314 { 315 kSDMMC_GoIdleState = 0U, /*!< Go Idle State */ 316 kSDMMC_AllSendCid = 2U, /*!< All Send CID */ 317 kSDMMC_SetDsr = 4U, /*!< Set DSR */ 318 kSDMMC_SelectCard = 7U, /*!< Select Card */ 319 kSDMMC_SendCsd = 9U, /*!< Send CSD */ 320 kSDMMC_SendCid = 10U, /*!< Send CID */ 321 kSDMMC_StopTransmission = 12U, /*!< Stop Transmission */ 322 kSDMMC_SendStatus = 13U, /*!< Send Status */ 323 kSDMMC_GoInactiveState = 15U, /*!< Go Inactive State */ 324 kSDMMC_SetBlockLength = 16U, /*!< Set Block Length */ 325 kSDMMC_ReadSingleBlock = 17U, /*!< Read Single Block */ 326 kSDMMC_ReadMultipleBlock = 18U, /*!< Read Multiple Block */ 327 kSDMMC_SetBlockCount = 23U, /*!< Set Block Count */ 328 kSDMMC_WriteSingleBlock = 24U, /*!< Write Single Block */ 329 kSDMMC_WriteMultipleBlock = 25U, /*!< Write Multiple Block */ 330 kSDMMC_ProgramCsd = 27U, /*!< Program CSD */ 331 kSDMMC_SetWriteProtect = 28U, /*!< Set Write Protect */ 332 kSDMMC_ClearWriteProtect = 29U, /*!< Clear Write Protect */ 333 kSDMMC_SendWriteProtect = 30U, /*!< Send Write Protect */ 334 kSDMMC_Erase = 38U, /*!< Erase */ 335 kSDMMC_LockUnlock = 42U, /*!< Lock Unlock */ 336 kSDMMC_ApplicationCommand = 55U, /*!< Send Application Command */ 337 kSDMMC_GeneralCommand = 56U, /*!< General Purpose Command */ 338 kSDMMC_ReadOcr = 58U, /*!< Read OCR */ 339 } sdmmc_command_t; 340 341 /*! @brief sdio card cccr register addr */ 342 enum _sdio_cccr_reg 343 { 344 kSDIO_RegCCCRSdioVer = 0x00U, /*!< CCCR & SDIO version*/ 345 kSDIO_RegSDVersion = 0x01U, /*!< SD version */ 346 kSDIO_RegIOEnable = 0x02U, /*!< io enable register */ 347 kSDIO_RegIOReady = 0x03U, /*!< io ready register */ 348 kSDIO_RegIOIntEnable = 0x04U, /*!< io interrupt enable register */ 349 kSDIO_RegIOIntPending = 0x05U, /*!< io interrupt pending register */ 350 kSDIO_RegIOAbort = 0x06U, /*!< io abort register */ 351 kSDIO_RegBusInterface = 0x07U, /*!< bus interface register */ 352 kSDIO_RegCardCapability = 0x08U, /*!< card capability register */ 353 kSDIO_RegCommonCISPointer = 0x09U, /*!< common CIS pointer register */ 354 kSDIO_RegBusSuspend = 0x0C, /*!< bus suspend register */ 355 kSDIO_RegFunctionSelect = 0x0DU, /*!< function select register */ 356 kSDIO_RegExecutionFlag = 0x0EU, /*!< execution flag register */ 357 kSDIO_RegReadyFlag = 0x0FU, /*!< ready flag register */ 358 kSDIO_RegFN0BlockSizeLow = 0x10U, /*!< FN0 block size register */ 359 kSDIO_RegFN0BlockSizeHigh = 0x11U, /*!< FN0 block size register */ 360 kSDIO_RegPowerControl = 0x12U, /*!< power control register */ 361 kSDIO_RegHighSpeed = 0x13U, /*!< high speed register */ 362 }; 363 364 /*! @brief sdio card individual commands */ 365 typedef enum _sdio_command 366 { 367 kSDIO_SendRelativeAddress = 3U, /*!< send relative address */ 368 kSDIO_SendOperationCondition = 5U, /*!< send operation condition */ 369 kSDIO_SendInterfaceCondition = 8U, /*!< send interface condition */ 370 kSDIO_RWIODirect = 52U, /*!< read/write IO direct command */ 371 kSDIO_RWIOExtended = 53U, /*!< read/write IO extended command */ 372 } sdio_command_t; 373 374 /*! @brief sdio card individual commands */ 375 typedef enum _sdio_func_num 376 { 377 kSDIO_FunctionNum0, /*!< sdio function0*/ 378 kSDIO_FunctionNum1, /*!< sdio function1*/ 379 kSDIO_FunctionNum2, /*!< sdio function2*/ 380 kSDIO_FunctionNum3, /*!< sdio function3*/ 381 kSDIO_FunctionNum4, /*!< sdio function4*/ 382 kSDIO_FunctionNum5, /*!< sdio function5*/ 383 kSDIO_FunctionNum6, /*!< sdio function6*/ 384 kSDIO_FunctionNum7, /*!< sdio function7*/ 385 kSDIO_FunctionMemory, /*!< for combo card*/ 386 } sdio_func_num_t; 387 388 #define SDIO_CMD_ARGUMENT_RW_POS (31U) /*!< read/write flag position */ 389 #define SDIO_CMD_ARGUMENT_FUNC_NUM_POS (28U) /*!< function number position */ 390 #define SDIO_DIRECT_CMD_ARGUMENT_RAW_POS (27U) /*!< direct raw flag position */ 391 #define SDIO_CMD_ARGUMENT_REG_ADDR_POS (9U) /*!< direct reg addr position */ 392 #define SDIO_CMD_ARGUMENT_REG_ADDR_MASK (0x1FFFFU) /*!< direct reg addr mask */ 393 #define SDIO_DIRECT_CMD_DATA_MASK (0xFFU) /*!< data mask */ 394 395 #define SDIO_EXTEND_CMD_ARGUMENT_BLOCK_MODE_POS (27U) /*!< extended command argument block mode bit position */ 396 #define SDIO_EXTEND_CMD_ARGUMENT_OP_CODE_POS (26U) /*!< extended command argument OP Code bit position */ 397 #define SDIO_EXTEND_CMD_BLOCK_MODE_MASK (0x08000000U) /*!< block mode mask */ 398 #define SDIO_EXTEND_CMD_OP_CODE_MASK (0x04000000U) /*!< op code mask */ 399 #define SDIO_EXTEND_CMD_COUNT_MASK (0x1FFU) /*!< byte/block count mask */ 400 #define SDIO_MAX_BLOCK_SIZE (2048U) /*!< max block size */ 401 #define SDIO_FBR_BASE(x) (x * 0x100U) /*!< function basic register */ 402 #define SDIO_TPL_CODE_END (0xFFU) /*!< tuple end */ 403 #define SDIO_TPL_CODE_MANIFID (0x20U) /*!< manufacturer ID */ 404 #define SDIO_TPL_CODE_FUNCID (0x21U) /*!< function ID */ 405 #define SDIO_TPL_CODE_FUNCE (0x22U) /*!< function extension tuple*/ 406 /*! @brief sdio command response flag */ 407 enum _sdio_status_flag 408 { 409 kSDIO_StatusCmdCRCError = 0x8000U, /*!< the CRC check of the previous cmd fail*/ 410 kSDIO_StatusIllegalCmd = 0x4000U, /*!< cmd illegal for the card state */ 411 kSDIO_StatusR6Error = 0x2000U, /*!< special for R6 error status */ 412 kSDIO_StatusError = 0x0800U, /*!< A general or an unknown error occurred */ 413 kSDIO_StatusFunctionNumError = 0x0200U, /*!< invail function error */ 414 kSDIO_StatusOutofRange = 0x0100U, /*!< cmd argument was out of the allowed range*/ 415 }; 416 417 /*! @brief sdio operation condition flag */ 418 enum _sdio_ocr_flag 419 { 420 kSDIO_OcrPowerUpBusyFlag = (1U << 31U), /*!< Power up busy status */ 421 kSDIO_OcrIONumber = (7U << 28U), /*!< number of IO function */ 422 kSDIO_OcrMemPresent = (1U << 27U), /*!< memory present flag */ 423 424 kSDIO_OcrVdd20_21Flag = (1U << 8U), /*!< VDD 2.0-2.1 */ 425 kSDIO_OcrVdd21_22Flag = (1U << 9U), /*!< VDD 2.1-2.2 */ 426 kSDIO_OcrVdd22_23Flag = (1U << 10U), /*!< VDD 2.2-2.3 */ 427 kSDIO_OcrVdd23_24Flag = (1U << 11U), /*!< VDD 2.3-2.4 */ 428 kSDIO_OcrVdd24_25Flag = (1U << 12U), /*!< VDD 2.4-2.5 */ 429 kSDIO_OcrVdd25_26Flag = (1U << 13U), /*!< VDD 2.5-2.6 */ 430 kSDIO_OcrVdd26_27Flag = (1U << 14U), /*!< VDD 2.6-2.7 */ 431 kSDIO_OcrVdd27_28Flag = (1U << 15U), /*!< VDD 2.7-2.8 */ 432 kSDIO_OcrVdd28_29Flag = (1U << 16U), /*!< VDD 2.8-2.9 */ 433 kSDIO_OcrVdd29_30Flag = (1U << 17U), /*!< VDD 2.9-3.0 */ 434 kSDIO_OcrVdd30_31Flag = (1U << 18U), /*!< VDD 2.9-3.0 */ 435 kSDIO_OcrVdd31_32Flag = (1U << 19U), /*!< VDD 3.0-3.1 */ 436 kSDIO_OcrVdd32_33Flag = (1U << 20U), /*!< VDD 3.1-3.2 */ 437 kSDIO_OcrVdd33_34Flag = (1U << 21U), /*!< VDD 3.2-3.3 */ 438 kSDIO_OcrVdd34_35Flag = (1U << 22U), /*!< VDD 3.3-3.4 */ 439 kSDIO_OcrVdd35_36Flag = (1U << 23U), /*!< VDD 3.4-3.5 */ 440 441 }; 442 443 /*! @brief sdio capability flag */ 444 enum _sdio_capability_flag 445 { 446 kSDIO_CCCRSupportDirectCmdDuringDataTrans = (1U << 0U), /*!< support direct cmd during data transfer */ 447 kSDIO_CCCRSupportMultiBlock = (1U << 1U), /*!< support multi block mode */ 448 kSDIO_CCCRSupportReadWait = (1U << 2U), /*!< support read wait */ 449 kSDIO_CCCRSupportSuspendResume = (1U << 3U), /*!< support suspend resume */ 450 kSDIO_CCCRSupportIntDuring4BitDataTrans = (1U << 4U), /*!< support interrupt during 4-bit data transfer */ 451 kSDIO_CCCRSupportLowSpeed1Bit = (1U << 6U), /*!< support low speed 1bit mode */ 452 kSDIO_CCCRSupportLowSpeed4Bit = (1U << 7U), /*!< support low speed 4bit mode */ 453 kSDIO_CCCRSupportMasterPowerControl = (1U << 8U), /*!< support master power control */ 454 kSDIO_CCCRSupportHighSpeed = (1U << 9U), /*!< support high speed */ 455 kSDIO_CCCRSupportContinuousSPIInt = (1U << 10U), /*!< support continuous SPI interrupt */ 456 }; 457 458 /*! @brief sdio fbr flag */ 459 enum _sdio_fbr_flag 460 { 461 kSDIO_FBRSupportCSA = (1U << 0U), /*!< function support CSA */ 462 kSDIO_FBRSupportPowerSelection = (1U << 1U), /*!< function support power selection */ 463 }; 464 465 /*! @brief sdio bus width */ 466 typedef enum _sdio_bus_width 467 { 468 kSDIO_DataBus1Bit = 0x00U, /*!< 1bit bus mode */ 469 kSDIO_DataBus4Bit = 0X02U, /*!< 4 bit bus mode*/ 470 } sdio_bus_width_t; 471 472 /*! @brief MMC card individual commands */ 473 typedef enum _mmc_command 474 { 475 kMMC_SendOperationCondition = 1U, /*!< Send Operation Condition */ 476 kMMC_SetRelativeAddress = 3U, /*!< Set Relative Address */ 477 kMMC_SleepAwake = 5U, /*!< Sleep Awake */ 478 kMMC_Switch = 6U, /*!< Switch */ 479 kMMC_SendExtendedCsd = 8U, /*!< Send EXT_CSD */ 480 kMMC_ReadDataUntilStop = 11U, /*!< Read Data Until Stop */ 481 kMMC_BusTestRead = 14U, /*!< Test Read */ 482 kMMC_SendingBusTest = 19U, /*!< test bus width cmd*/ 483 kMMC_WriteDataUntilStop = 20U, /*!< Write Data Until Stop */ 484 kMMC_SendTuningBlock = 21U, /*!< MMC sending tuning block */ 485 kMMC_ProgramCid = 26U, /*!< Program CID */ 486 kMMC_EraseGroupStart = 35U, /*!< Erase Group Start */ 487 kMMC_EraseGroupEnd = 36U, /*!< Erase Group End */ 488 kMMC_FastInputOutput = 39U, /*!< Fast IO */ 489 kMMC_GoInterruptState = 40U, /*!< Go interrupt State */ 490 } mmc_command_t; 491 492 /*! @brief MMC card classified as voltage range */ 493 typedef enum _mmc_classified_voltage 494 { 495 kMMC_ClassifiedVoltageHigh = 0U, /*!< High-voltage MMC card */ 496 kMMC_ClassifiedVoltageDual = 1U, /*!< Dual-voltage MMC card */ 497 } mmc_classified_voltage_t; 498 499 /*! @brief MMC card classified as density level */ 500 typedef enum _mmc_classified_density 501 { 502 kMMC_ClassifiedDensityWithin2GB = 0U, /*!< Density byte is less than or equal 2GB */ 503 kMMC_ClassifiedDensityHigher2GB = 1U, /* Density byte is higher than 2GB */ 504 } mmc_classified_density_t; 505 506 /*! @brief The bit mask for VOLTAGE WINDOW 1.70V to 1.95V field in OCR */ 507 #define MMC_OCR_V170TO195_SHIFT (7U) 508 /*! @brief The bit mask for VOLTAGE WINDOW 1.70V to 1.95V field in OCR */ 509 #define MMC_OCR_V170TO195_MASK (0x00000080U) 510 /*! @brief The bit shift for VOLTAGE WINDOW 2.00V to 2.60V field in OCR */ 511 #define MMC_OCR_V200TO260_SHIFT (8U) 512 /*! @brief The bit mask for VOLTAGE WINDOW 2.00V to 2.60V field in OCR */ 513 #define MMC_OCR_V200TO260_MASK (0x00007F00U) 514 /*! @brief The bit shift for VOLTAGE WINDOW 2.70V to 3.60V field in OCR */ 515 #define MMC_OCR_V270TO360_SHIFT (15U) 516 /*! @brief The bit mask for VOLTAGE WINDOW 2.70V to 3.60V field in OCR */ 517 #define MMC_OCR_V270TO360_MASK (0x00FF8000U) 518 /*! @brief The bit shift for ACCESS MODE field in OCR */ 519 #define MMC_OCR_ACCESS_MODE_SHIFT (29U) 520 /*! @brief The bit mask for ACCESS MODE field in OCR */ 521 #define MMC_OCR_ACCESS_MODE_MASK (0x60000000U) 522 /*! @brief The bit shift for BUSY field in OCR */ 523 #define MMC_OCR_BUSY_SHIFT (31U) 524 /*! @brief The bit mask for BUSY field in OCR */ 525 #define MMC_OCR_BUSY_MASK (1U << MMC_OCR_BUSY_SHIFT) 526 527 /*! @brief MMC card access mode(Access mode in OCR). */ 528 typedef enum _mmc_access_mode 529 { 530 kMMC_AccessModeByte = 0U, /*!< The card should be accessed as byte */ 531 kMMC_AccessModeSector = 2U, /*!< The card should be accessed as sector */ 532 } mmc_access_mode_t; 533 534 /*! @brief MMC card voltage window(VDD voltage window in OCR). */ 535 typedef enum _mmc_voltage_window 536 { 537 kMMC_VoltageWindowNone = 0U, /*!< voltage window is not define by user*/ 538 kMMC_VoltageWindow120 = 0x01U, /*!< Voltage window is 1.20V */ 539 kMMC_VoltageWindow170to195 = 0x02U, /*!< Voltage window is 1.70V to 1.95V */ 540 kMMC_VoltageWindows270to360 = 0x1FFU, /*!< Voltage window is 2.70V to 3.60V */ 541 } mmc_voltage_window_t; 542 543 /*! @brief CSD structure version(CSD_STRUCTURE in CSD). */ 544 typedef enum _mmc_csd_structure_version 545 { 546 kMMC_CsdStrucureVersion10 = 0U, /*!< CSD version No. 1.0 */ 547 kMMC_CsdStrucureVersion11 = 1U, /*!< CSD version No. 1.1 */ 548 kMMC_CsdStrucureVersion12 = 2U, /*!< CSD version No. 1.2 */ 549 kMMC_CsdStrucureVersionInExtcsd = 3U, /*!< Version coded in Extended CSD */ 550 } mmc_csd_structure_version_t; 551 552 /*! @brief MMC card specification version(SPEC_VERS in CSD). */ 553 typedef enum _mmc_specification_version 554 { 555 kMMC_SpecificationVersion0 = 0U, /*!< Allocated by MMCA */ 556 kMMC_SpecificationVersion1 = 1U, /*!< Allocated by MMCA */ 557 kMMC_SpecificationVersion2 = 2U, /*!< Allocated by MMCA */ 558 kMMC_SpecificationVersion3 = 3U, /*!< Allocated by MMCA */ 559 kMMC_SpecificationVersion4 = 4U, /*!< Version 4.1/4.2/4.3/4.41-4.5-4.51-5.0 */ 560 } mmc_specification_version_t; 561 562 /*! @brief The bit shift for FREQUENCY UNIT field in TRANSFER SPEED(TRAN-SPEED in Extended CSD) */ 563 #define MMC_TRANSFER_SPEED_FREQUENCY_UNIT_SHIFT (0U) 564 /*! @brief The bit mask for FRQEUENCY UNIT in TRANSFER SPEED */ 565 #define MMC_TRANSFER_SPEED_FREQUENCY_UNIT_MASK (0x07U) 566 /*! @brief The bit shift for MULTIPLIER field in TRANSFER SPEED */ 567 #define MMC_TRANSFER_SPEED_MULTIPLIER_SHIFT (3U) 568 /*! @brief The bit mask for MULTIPLIER field in TRANSFER SPEED */ 569 #define MMC_TRANSFER_SPEED_MULTIPLIER_MASK (0x78U) 570 571 /*! @brief Read the value of FREQUENCY UNIT in TRANSFER SPEED. */ 572 #define READ_MMC_TRANSFER_SPEED_FREQUENCY_UNIT(CSD) \ 573 (((CSD.transferSpeed) & MMC_TRANSFER_SPEED_FREQUENCY_UNIT_MASK) >> MMC_TRANSFER_SPEED_FREQUENCY_UNIT_SHIFT) 574 /*! @brief Read the value of MULTIPLER filed in TRANSFER SPEED. */ 575 #define READ_MMC_TRANSFER_SPEED_MULTIPLIER(CSD) \ 576 (((CSD.transferSpeed) & MMC_TRANSFER_SPEED_MULTIPLIER_MASK) >> MMC_TRANSFER_SPEED_MULTIPLIER_SHIFT) 577 578 /*! @brief MMC card Extended CSD fix version(EXT_CSD_REV in Extended CSD) */ 579 enum _mmc_extended_csd_revision 580 { 581 kMMC_ExtendedCsdRevision10 = 0U, /*!< Revision 1.0 */ 582 kMMC_ExtendedCsdRevision11 = 1U, /*!< Revision 1.1 */ 583 kMMC_ExtendedCsdRevision12 = 2U, /*!< Revision 1.2 */ 584 kMMC_ExtendedCsdRevision13 = 3U, /*!< Revision 1.3 MMC4.3*/ 585 kMMC_ExtendedCsdRevision14 = 4U, /*!< Revision 1.4 obsolete*/ 586 kMMC_ExtendedCsdRevision15 = 5U, /*!< Revision 1.5 MMC4.41*/ 587 kMMC_ExtendedCsdRevision16 = 6U, /*!< Revision 1.6 MMC4.5*/ 588 kMMC_ExtendedCsdRevision17 = 7U, /*!< Revision 1.7 MMC5.0 */ 589 }; 590 591 /*! @brief MMC card command set(COMMAND_SET in Extended CSD) */ 592 typedef enum _mmc_command_set 593 { 594 kMMC_CommandSetStandard = 0U, /*!< Standard MMC */ 595 kMMC_CommandSet1 = 1U, /*!< Command set 1 */ 596 kMMC_CommandSet2 = 2U, /*!< Command set 2 */ 597 kMMC_CommandSet3 = 3U, /*!< Command set 3 */ 598 kMMC_CommandSet4 = 4U, /*!< Command set 4 */ 599 } mmc_command_set_t; 600 601 /*! @brief boot support(BOOT_INFO in Extended CSD) */ 602 enum _mmc_support_boot_mode 603 { 604 kMMC_SupportAlternateBoot = 1U, /*!< support alternative boot mode*/ 605 kMMC_SupportDDRBoot = 2U, /*!< support DDR boot mode*/ 606 kMMC_SupportHighSpeedBoot = 4U, /*!< support high speed boot mode*/ 607 }; 608 /*! @brief The power class value bit mask when bus in 4 bit mode */ 609 #define MMC_POWER_CLASS_4BIT_MASK (0x0FU) 610 /*! @brief The power class current value bit mask when bus in 8 bit mode */ 611 #define MMC_POWER_CLASS_8BIT_MASK (0xF0U) 612 613 /*! @brief MMC card high-speed timing(HS_TIMING in Extended CSD) */ 614 typedef enum _mmc_high_speed_timing 615 { 616 kMMC_HighSpeedTimingNone = 0U, /*!< MMC card using none high-speed timing */ 617 kMMC_HighSpeedTiming = 1U, /*!< MMC card using high-speed timing */ 618 kMMC_HighSpeed200Timing = 2U, /*!< MMC card high speed 200 timing*/ 619 kMMC_HighSpeed400Timing = 3U, /*!< MMC card high speed 400 timing*/ 620 kMMC_HighSpeed26MHZTiming = 4U, /*!< MMC high speed 26MHZ timing */ 621 kMMC_HighSpeed52MHZTiming = 5U, /*!< MMC high speed 52MHZ timing */ 622 kMMC_HighSpeedDDR52Timing = 6U, /*!< MMC high speed timing DDR52 1.8V */ 623 } mmc_high_speed_timing_t; 624 625 /*! @brief The number of data bus width type */ 626 #define MMC_DATA_BUS_WIDTH_TYPE_NUMBER (3U) 627 /*! @brief MMC card data bus width(BUS_WIDTH in Extended CSD) */ 628 typedef enum _mmc_data_bus_width 629 { 630 kMMC_DataBusWidth1bit = 0U, /*!< MMC data bus width is 1 bit */ 631 kMMC_DataBusWidth4bit = 1U, /*!< MMC data bus width is 4 bits */ 632 kMMC_DataBusWidth8bit = 2U, /*!< MMC data bus width is 8 bits */ 633 kMMC_DataBusWidth4bitDDR = 5U, /*!< MMC data bus width is 4 bits ddr */ 634 kMMC_DataBusWidth8bitDDR = 6U, /*!< MMC data bus width is 8 bits ddr */ 635 } mmc_data_bus_width_t; 636 637 /*! @brief MMC card boot partition enabled(BOOT_PARTITION_ENABLE in Extended CSD) */ 638 typedef enum _mmc_boot_partition_enable 639 { 640 kMMC_BootPartitionEnableNot = 0U, /*!< Device not boot enabled (default) */ 641 kMMC_BootPartitionEnablePartition1 = 1U, /*!< Boot partition 1 enabled for boot */ 642 kMMC_BootPartitionEnablePartition2 = 2U, /*!< Boot partition 2 enabled for boot */ 643 kMMC_BootPartitionEnableUserAera = 7U, /*!< User area enabled for boot */ 644 } mmc_boot_partition_enable_t; 645 646 /*! @brief MMC card partition to be accessed(BOOT_PARTITION_ACCESS in Extended CSD) */ 647 typedef enum _mmc_access_partition 648 { 649 kMMC_AccessPartitionUserAera = 0U, /*!< No access to boot partition (default), normal partition */ 650 kMMC_AccessPartitionBoot1 = 1U, /*!< Read/Write boot partition 1 */ 651 kMMC_AccessPartitionBoot2 = 2U, /*!< Read/Write boot partition 2*/ 652 kMMC_AccessRPMB = 3U, /*!< Replay protected mem block */ 653 kMMC_AccessGeneralPurposePartition1 = 4U, /*!< access to general purpose partition 1 */ 654 kMMC_AccessGeneralPurposePartition2 = 5U, /*!< access to general purpose partition 2 */ 655 kMMC_AccessGeneralPurposePartition3 = 6U, /*!< access to general purpose partition 3 */ 656 kMMC_AccessGeneralPurposePartition4 = 7U, /*!< access to general purpose partition 4 */ 657 } mmc_access_partition_t; 658 659 /*! @brief The bit shift for PARTITION ACCESS filed in BOOT CONFIG (BOOT_CONFIG in Extend CSD) */ 660 #define MMC_BOOT_CONFIG_PARTITION_ACCESS_SHIFT (0U) 661 /*! @brief The bit mask for PARTITION ACCESS field in BOOT CONFIG */ 662 #define MMC_BOOT_CONFIG_PARTITION_ACCESS_MASK (0x00000007U) 663 /*! @brief The bit shift for PARTITION ENABLE field in BOOT CONFIG */ 664 #define MMC_BOOT_CONFIG_PARTITION_ENABLE_SHIFT (3U) 665 /*! @brief The bit mask for PARTITION ENABLE field in BOOT CONFIG */ 666 #define MMC_BOOT_CONFIG_PARTITION_ENABLE_MASK (0x00000038U) 667 /*! @brief The bit shift for ACK field in BOOT CONFIG */ 668 #define MMC_BOOT_CONFIG_ACK_SHIFT (6U) 669 /*! @brief The bit mask for ACK field in BOOT CONFIG */ 670 #define MMC_BOOT_CONFIG_ACK_MASK (0x00000040U) 671 /*! @brief The bit shift for BOOT BUS WIDTH field in BOOT CONFIG */ 672 #define MMC_BOOT_BUS_WIDTH_WIDTH_SHIFT (8U) 673 /*! @brief The bit mask for BOOT BUS WIDTH field in BOOT CONFIG */ 674 #define MMC_BOOT_BUS_WIDTH_WIDTH_MASK (0x00000300U) 675 /*! @brief The bit shift for BOOT BUS WIDTH RESET field in BOOT CONFIG */ 676 #define MMC_BOOT_BUS_WIDTH_RESET_SHIFT (10U) 677 /*! @brief The bit mask for BOOT BUS WIDTH RESET field in BOOT CONFIG */ 678 #define MMC_BOOT_BUS_WIDTH_RESET_MASK (0x00000400U) 679 680 /*! @brief MMC card CSD register flags */ 681 enum _mmc_csd_flag 682 { 683 kMMC_CsdReadBlockPartialFlag = (1U << 0U), /*!< Partial blocks for read allowed */ 684 kMMC_CsdWriteBlockMisalignFlag = (1U << 1U), /*!< Write block misalignment */ 685 kMMC_CsdReadBlockMisalignFlag = (1U << 2U), /*!< Read block misalignment */ 686 kMMC_CsdDsrImplementedFlag = (1U << 3U), /*!< DSR implemented */ 687 kMMC_CsdWriteProtectGroupEnabledFlag = (1U << 4U), /*!< Write protect group enabled */ 688 kMMC_CsdWriteBlockPartialFlag = (1U << 5U), /*!< Partial blocks for write allowed */ 689 kMMC_ContentProtectApplicationFlag = (1U << 6U), /*!< Content protect application */ 690 kMMC_CsdFileFormatGroupFlag = (1U << 7U), /*!< File format group */ 691 kMMC_CsdCopyFlag = (1U << 8U), /*!< Copy flag */ 692 kMMC_CsdPermanentWriteProtectFlag = (1U << 9U), /*!< Permanent write protection */ 693 kMMC_CsdTemporaryWriteProtectFlag = (1U << 10U), /*!< Temporary write protection */ 694 }; 695 696 /*! @brief Extended CSD register access mode(Access mode in CMD6). */ 697 typedef enum _mmc_extended_csd_access_mode 698 { 699 kMMC_ExtendedCsdAccessModeCommandSet = 0U, /*!< Command set related setting */ 700 kMMC_ExtendedCsdAccessModeSetBits = 1U, /*!< Set bits in specific byte in Extended CSD */ 701 kMMC_ExtendedCsdAccessModeClearBits = 2U, /*!< Clear bits in specific byte in Extended CSD */ 702 kMMC_ExtendedCsdAccessModeWriteBits = 3U, /*!< Write a value to specific byte in Extended CSD */ 703 } mmc_extended_csd_access_mode_t; 704 705 /*! @brief EXT CSD byte index */ 706 typedef enum _mmc_extended_csd_index 707 { 708 kMMC_ExtendedCsdIndexEraseGroupDefinition = 175U, /*!< Erase Group Def */ 709 kMMC_ExtendedCsdIndexBootBusWidth = 177U, /*!< Boot Bus Width */ 710 kMMC_ExtendedCsdIndexBootConfig = 179U, /*!< Boot Config */ 711 kMMC_ExtendedCsdIndexBusWidth = 183U, /*!< Bus Width */ 712 kMMC_ExtendedCsdIndexHighSpeedTiming = 185U, /*!< High-speed Timing */ 713 kMMC_ExtendedCsdIndexPowerClass = 187U, /*!< Power Class */ 714 kMMC_ExtendedCsdIndexCommandSet = 191U, /*!< Command Set */ 715 } mmc_extended_csd_index_t; 716 717 /*! @brief mmc driver strength */ 718 enum _mmc_driver_strength 719 { 720 kMMC_DriverStrength0 = 0U, /*!< Driver type0 ,nominal impedance 50ohm */ 721 kMMC_DriverStrength1 = 1U, /*!< Driver type1 ,nominal impedance 33ohm */ 722 kMMC_DriverStrength2 = 2U, /*!< Driver type2 ,nominal impedance 66ohm */ 723 kMMC_DriverStrength3 = 3U, /*!< Driver type3 ,nominal impedance 100ohm */ 724 kMMC_DriverStrength4 = 4U, /*!< Driver type4 ,nominal impedance 40ohm */ 725 }; 726 727 /*! @brief mmc extended csd flags*/ 728 typedef enum _mmc_extended_csd_flags 729 { 730 kMMC_ExtCsdExtPartitionSupport = (1 << 0U), /*!< partitioning support[160] */ 731 kMMC_ExtCsdEnhancePartitionSupport = (1 << 1U), /*!< partitioning support[160] */ 732 kMMC_ExtCsdPartitioningSupport = (1 << 2U), /*!< partitioning support[160] */ 733 kMMC_ExtCsdPrgCIDCSDInDDRModeSupport = (1 << 3U), /*!< CMD26 and CMD27 are support dual data rate [130]*/ 734 kMMC_ExtCsdBKOpsSupport = (1 << 4U), /*!< background operation feature support [502]*/ 735 kMMC_ExtCsdDataTagSupport = (1 << 5U), /*!< data tag support[499]*/ 736 kMMC_ExtCsdModeOperationCodeSupport = (1 << 6U), /*!< mode operation code support[493]*/ 737 } mmc_extended_csd_flags_t; 738 739 /*! @brief The length of Extended CSD register, unit as bytes. */ 740 #define MMC_EXTENDED_CSD_BYTES (512U) 741 742 /*! @brief MMC card default relative address */ 743 #define MMC_DEFAULT_RELATIVE_ADDRESS (2U) 744 745 /*! @brief SD card product name length united as bytes. */ 746 #define SD_PRODUCT_NAME_BYTES (5U) 747 748 /*! @brief sdio card FBR register */ 749 typedef struct _sdio_fbr 750 { 751 uint8_t flags; /*!< current io flags */ 752 uint8_t ioStdFunctionCode; /*!< current io standard function code */ 753 uint8_t ioExtFunctionCode; /*!< current io extended function code*/ 754 uint32_t ioPointerToCIS; /*!< current io pointer to CIS */ 755 uint32_t ioPointerToCSA; /*!< current io pointer to CSA*/ 756 uint16_t ioBlockSize; /*!< current io block size */ 757 } sdio_fbr_t; 758 759 /*! @brief sdio card common CIS */ 760 typedef struct _sdio_common_cis 761 { 762 /* manufacturer identification string tuple */ 763 uint16_t mID; /*!< manufacturer code */ 764 uint16_t mInfo; /*!< manufacturer information */ 765 766 /*function identification tuple */ 767 uint8_t funcID; /*!< function ID */ 768 769 /* function extension tuple */ 770 uint16_t fn0MaxBlkSize; /*!< function 0 max block size */ 771 uint8_t maxTransSpeed; /*!< max data transfer speed for all function */ 772 773 } sdio_common_cis_t; 774 775 /*! @brief sdio card function CIS */ 776 typedef struct _sdio_func_cis 777 { 778 /*function identification tuple */ 779 uint8_t funcID; /*!< function ID */ 780 781 /* function extension tuple */ 782 uint8_t funcInfo; /*!< function info */ 783 uint8_t ioVersion; /*!< level of application specification this io support */ 784 uint32_t cardPSN; /*!< product serial number */ 785 uint32_t ioCSASize; /*!< avaliable CSA size for io */ 786 uint8_t ioCSAProperty; /*!< CSA property */ 787 uint16_t ioMaxBlockSize; /*!< io max transfer data size */ 788 uint32_t ioOCR; /*!< io ioeration condition */ 789 uint8_t ioOPMinPwr; /*!< min current in operation mode */ 790 uint8_t ioOPAvgPwr; /*!< average current in operation mode */ 791 uint8_t ioOPMaxPwr; /*!< max current in operation mode */ 792 uint8_t ioSBMinPwr; /*!< min current in standby mode */ 793 uint8_t ioSBAvgPwr; /*!< average current in standby mode */ 794 uint8_t ioSBMaxPwr; /*!< max current in standby mode */ 795 796 uint16_t ioMinBandWidth; /*!< io min transfer bandwidth */ 797 uint16_t ioOptimumBandWidth; /*!< io optimum transfer bandwidth */ 798 uint16_t ioReadyTimeout; /*!< timeout value from enalbe to ready */ 799 uint16_t ioHighCurrentAvgCurrent; /*!< the average peak current (mA) 800 when IO operating in high current mode */ 801 uint16_t ioHighCurrentMaxCurrent; /*!< the max peak current (mA) 802 when IO operating in high current mode */ 803 uint16_t ioLowCurrentAvgCurrent; /*!< the average peak current (mA) 804 when IO operating in lower current mode */ 805 uint16_t ioLowCurrentMaxCurrent; /*!< the max peak current (mA) 806 when IO operating in lower current mode */ 807 } sdio_func_cis_t; 808 809 /*! @brief SD card CID register */ 810 typedef struct _sd_cid 811 { 812 uint8_t manufacturerID; /*!< Manufacturer ID [127:120] */ 813 uint16_t applicationID; /*!< OEM/Application ID [119:104] */ 814 uint8_t productName[SD_PRODUCT_NAME_BYTES]; /*!< Product name [103:64] */ 815 uint8_t productVersion; /*!< Product revision [63:56] */ 816 uint32_t productSerialNumber; /*!< Product serial number [55:24] */ 817 uint16_t manufacturerData; /*!< Manufacturing date [19:8] */ 818 } sd_cid_t; 819 820 /*! @brief SD card CSD register */ 821 typedef struct _sd_csd 822 { 823 uint8_t csdStructure; /*!< CSD structure [127:126] */ 824 uint8_t dataReadAccessTime1; /*!< Data read access-time-1 [119:112] */ 825 uint8_t dataReadAccessTime2; /*!< Data read access-time-2 in clock cycles (NSAC*100) [111:104] */ 826 uint8_t transferSpeed; /*!< Maximum data transfer rate [103:96] */ 827 uint16_t cardCommandClass; /*!< Card command classes [95:84] */ 828 uint8_t readBlockLength; /*!< Maximum read data block length [83:80] */ 829 uint16_t flags; /*!< Flags in _sd_csd_flag */ 830 uint32_t deviceSize; /*!< Device size [73:62] */ 831 /* Following fields from 'readCurrentVddMin' to 'deviceSizeMultiplier' exist in CSD version 1 */ 832 uint8_t readCurrentVddMin; /*!< Maximum read current at VDD min [61:59] */ 833 uint8_t readCurrentVddMax; /*!< Maximum read current at VDD max [58:56] */ 834 uint8_t writeCurrentVddMin; /*!< Maximum write current at VDD min [55:53] */ 835 uint8_t writeCurrentVddMax; /*!< Maximum write current at VDD max [52:50] */ 836 uint8_t deviceSizeMultiplier; /*!< Device size multiplier [49:47] */ 837 838 uint8_t eraseSectorSize; /*!< Erase sector size [45:39] */ 839 uint8_t writeProtectGroupSize; /*!< Write protect group size [38:32] */ 840 uint8_t writeSpeedFactor; /*!< Write speed factor [28:26] */ 841 uint8_t writeBlockLength; /*!< Maximum write data block length [25:22] */ 842 uint8_t fileFormat; /*!< File format [11:10] */ 843 } sd_csd_t; 844 845 /*! @brief The bit shift for RATE UNIT field in TRANSFER SPEED */ 846 #define SD_TRANSFER_SPEED_RATE_UNIT_SHIFT (0U) 847 /*! @brief The bit mask for RATE UNIT field in TRANSFER SPEED */ 848 #define SD_TRANSFER_SPEED_RATE_UNIT_MASK (0x07U) 849 /*! @brief The bit shift for TIME VALUE field in TRANSFER SPEED */ 850 #define SD_TRANSFER_SPEED_TIME_VALUE_SHIFT (2U) 851 /*! @brief The bit mask for TIME VALUE field in TRANSFER SPEED */ 852 #define SD_TRANSFER_SPEED_TIME_VALUE_MASK (0x78U) 853 /*! @brief Read the value of FREQUENCY UNIT in TRANSFER SPEED field */ 854 #define SD_RD_TRANSFER_SPEED_RATE_UNIT(x) \ 855 (((x.transferSpeed) & SD_TRANSFER_SPEED_RATE_UNIT_MASK) >> SD_TRANSFER_SPEED_RATE_UNIT_SHIFT) 856 /*! @brief Read the value of TIME VALUE in TRANSFER SPEED field */ 857 #define SD_RD_TRANSFER_SPEED_TIME_VALUE(x) \ 858 (((x.transferSpeed) & SD_TRANSFER_SPEED_TIME_VALUE_MASK) >> SD_TRANSFER_SPEED_TIME_VALUE_SHIFT) 859 860 /*! @brief SD card SCR register */ 861 typedef struct _sd_scr 862 { 863 uint8_t scrStructure; /*!< SCR Structure [63:60] */ 864 uint8_t sdSpecification; /*!< SD memory card specification version [59:56] */ 865 uint16_t flags; /*!< SCR flags in _sd_scr_flag */ 866 uint8_t sdSecurity; /*!< Security specification supported [54:52] */ 867 uint8_t sdBusWidths; /*!< Data bus widths supported [51:48] */ 868 uint8_t extendedSecurity; /*!< Extended security support [46:43] */ 869 uint8_t commandSupport; /*!< Command support bits [33:32] 33-support CMD23, 32-support cmd20*/ 870 uint32_t reservedForManufacturer; /*!< reserved for manufacturer usage [31:0] */ 871 } sd_scr_t; 872 873 /*! @brief MMC card product name length united as bytes. */ 874 #define MMC_PRODUCT_NAME_BYTES (6U) 875 /*! @brief MMC card CID register. */ 876 typedef struct _mmc_cid 877 { 878 uint8_t manufacturerID; /*!< Manufacturer ID */ 879 uint16_t applicationID; /*!< OEM/Application ID */ 880 uint8_t productName[MMC_PRODUCT_NAME_BYTES]; /*!< Product name */ 881 uint8_t productVersion; /*!< Product revision */ 882 uint32_t productSerialNumber; /*!< Product serial number */ 883 uint8_t manufacturerData; /*!< Manufacturing date */ 884 } mmc_cid_t; 885 886 /*! @brief MMC card CSD register. */ 887 typedef struct _mmc_csd 888 { 889 uint8_t csdStructureVersion; /*!< CSD structure [127:126] */ 890 uint8_t systemSpecificationVersion; /*!< System specification version [125:122] */ 891 uint8_t dataReadAccessTime1; /*!< Data read access-time 1 [119:112] */ 892 uint8_t dataReadAccessTime2; /*!< Data read access-time 2 in CLOCK cycles (NSAC*100) [111:104] */ 893 uint8_t transferSpeed; /*!< Max. bus clock frequency [103:96] */ 894 uint16_t cardCommandClass; /*!< card command classes [95:84] */ 895 uint8_t readBlockLength; /*!< Max. read data block length [83:80] */ 896 uint16_t flags; /*!< Contain flags in _mmc_csd_flag */ 897 uint16_t deviceSize; /*!< Device size [73:62] */ 898 uint8_t readCurrentVddMin; /*!< Max. read current @ VDD min [61:59] */ 899 uint8_t readCurrentVddMax; /*!< Max. read current @ VDD max [58:56] */ 900 uint8_t writeCurrentVddMin; /*!< Max. write current @ VDD min [55:53] */ 901 uint8_t writeCurrentVddMax; /*!< Max. write current @ VDD max [52:50] */ 902 uint8_t deviceSizeMultiplier; /*!< Device size multiplier [49:47] */ 903 uint8_t eraseGroupSize; /*!< Erase group size [46:42] */ 904 uint8_t eraseGroupSizeMultiplier; /*!< Erase group size multiplier [41:37] */ 905 uint8_t writeProtectGroupSize; /*!< Write protect group size [36:32] */ 906 uint8_t defaultEcc; /*!< Manufacturer default ECC [30:29] */ 907 uint8_t writeSpeedFactor; /*!< Write speed factor [28:26] */ 908 uint8_t maxWriteBlockLength; /*!< Max. write data block length [25:22] */ 909 uint8_t fileFormat; /*!< File format [11:10] */ 910 uint8_t eccCode; /*!< ECC code [9:8] */ 911 } mmc_csd_t; 912 913 /*! @brief MMC card Extended CSD register (unit: byte). */ 914 typedef struct _mmc_extended_csd 915 { 916 uint32_t flags; 917 uint8_t SecureRemoveType; /*!< secure removal type[16]*/ 918 uint8_t enProductStateAware; /*!< product state awareness enablement[17]*/ 919 uint32_t maxPreLoadDataSize; /*!< max preload data size[21-18]*/ 920 uint32_t preLoadDataSize; /*!< pre-load data size[25-22]*/ 921 uint8_t ffuStatus; /*!< FFU status [26]*/ 922 uint8_t modeOperationCode; /*!< mode operation code[29]*/ 923 uint8_t modeConfig; /*!< mode config [30]*/ 924 uint8_t cacheCtrl; /*!< control to turn on/off cache[33]*/ 925 uint8_t pwroffNotify; /*!< power off notification[34]*/ 926 uint8_t packedCmdFailIndex; /*!< packed cmd fail index [35]*/ 927 uint8_t packedCmdStatus; /*!< packed cmd status[36]*/ 928 uint32_t contextConfig[4U]; /*!< context configuration[51-37]*/ 929 uint16_t extPartitionAttr; /*!< extended partitions attribut[53-52]*/ 930 uint16_t exceptEventStatus; /*!< exception events status[55-54]*/ 931 uint16_t exceptEventControl; /*!< exception events control[57-56]*/ 932 uint8_t toReleaseAddressedGroup; /*!< number of group to be released[58]*/ 933 uint8_t class6CmdCtrl; /*!< class 6 command control[59]*/ 934 uint8_t intTimeoutEmu; /*!< 1st initiallization after disabling sector size emu[60]*/ 935 uint8_t sectorSize; /*!< sector size[61] */ 936 uint8_t sectorSizeEmu; /*!< sector size emulation[62]*/ 937 uint8_t nativeSectorSize; /*!< native sector size[63]*/ 938 uint8_t periodWakeup; /*!< period wakeup [131]*/ 939 uint8_t tCASESupport; /*!< package case temperature is controlled[132]*/ 940 uint8_t productionStateAware; /*!< production state awareness[133]*/ 941 uint32_t enhanceUsrDataStartAddr; /*!< enhanced user data start addr [139-136]*/ 942 uint32_t enhanceUsrDataSize; /*!< enhanced user data area size[142-140]*/ 943 uint32_t generalPartitionSize[3]; /*!< general purpose partition size[154-143]*/ 944 uint8_t partitionAttribute; /*!< partition attribute [156]*/ 945 uint32_t maxEnhanceAreaSize; /*!< max enhance area size [159-157]*/ 946 uint8_t hpiManagementEn; /*!< HPI management [161]*/ 947 uint8_t writeReliabilityParameter; /*!< write reliability parameter register[166] */ 948 uint8_t writeReliabilitySet; /*!< write reliability setting register[167] */ 949 uint8_t rpmbSizeMult; /*!< RPMB size multi [168]*/ 950 uint8_t fwConfig; /*!< FW configuration[169]*/ 951 uint8_t userWPRegister; /*!< user write protect register[171] */ 952 uint8_t bootWPRegister; /*!< boot write protect register[173]*/ 953 uint8_t bootWPStatusRegister; /*!< boot write protect status register[174]*/ 954 uint8_t highDensityEraseGroupDefinition; /*!< High-density erase group definition [175] */ 955 uint8_t bootDataBusWidth; /*!< Boot bus width [177] */ 956 uint8_t bootConfigProtect; /*!< Boot config protection [178]*/ 957 uint8_t partitionConfig; /*!< Boot configuration [179] */ 958 uint8_t eraseMemoryContent; /*!< Erased memory content [181] */ 959 uint8_t dataBusWidth; /*!< Data bus width mode [183] */ 960 uint8_t highSpeedTiming; /*!< High-speed interface timing [185] */ 961 uint8_t powerClass; /*!< Power class [187] */ 962 uint8_t commandSetRevision; /*!< Command set revision [189] */ 963 uint8_t commandSet; /*!< Command set [191] */ 964 uint8_t extendecCsdVersion; /*!< Extended CSD revision [192] */ 965 uint8_t csdStructureVersion; /*!< CSD structure version [194] */ 966 uint8_t cardType; /*!< Card Type [196] */ 967 uint8_t ioDriverStrength; /*!< IO driver strength [197] */ 968 uint8_t OutofInterruptBusyTiming; /*!< out of interrupt busy timing [198] */ 969 uint8_t partitionSwitchTiming; /*!< partition switch timing [199] */ 970 uint8_t powerClass52MHz195V; /*!< Power Class for 52MHz @ 1.95V [200] */ 971 uint8_t powerClass26MHz195V; /*!< Power Class for 26MHz @ 1.95V [201] */ 972 uint8_t powerClass52MHz360V; /*!< Power Class for 52MHz @ 3.6V [202] */ 973 uint8_t powerClass26MHz360V; /*!< Power Class for 26MHz @ 3.6V [203] */ 974 uint8_t minimumReadPerformance4Bit26MHz; /*!< Minimum Read Performance for 4bit at 26MHz [205] */ 975 uint8_t minimumWritePerformance4Bit26MHz; /*!< Minimum Write Performance for 4bit at 26MHz [206] */ 976 uint8_t minimumReadPerformance8Bit26MHz4Bit52MHz; 977 /*!< Minimum read Performance for 8bit at 26MHz/4bit @52MHz [207] */ 978 uint8_t minimumWritePerformance8Bit26MHz4Bit52MHz; 979 /*!< Minimum Write Performance for 8bit at 26MHz/4bit @52MHz [208] */ 980 uint8_t minimumReadPerformance8Bit52MHz; /*!< Minimum Read Performance for 8bit at 52MHz [209] */ 981 uint8_t minimumWritePerformance8Bit52MHz; /*!< Minimum Write Performance for 8bit at 52MHz [210] */ 982 uint32_t sectorCount; /*!< Sector Count [215:212] */ 983 uint8_t sleepNotificationTimeout; /*!< sleep notification timeout [216]*/ 984 uint8_t sleepAwakeTimeout; /*!< Sleep/awake timeout [217] */ 985 uint8_t productionStateAwareTimeout; /*!< Production state awareness timeout [218]*/ 986 uint8_t sleepCurrentVCCQ; /*!< Sleep current (VCCQ) [219] */ 987 uint8_t sleepCurrentVCC; /*!< Sleep current (VCC) [220] */ 988 uint8_t highCapacityWriteProtectGroupSize; /*!< High-capacity write protect group size [221] */ 989 uint8_t reliableWriteSectorCount; /*!< Reliable write sector count [222] */ 990 uint8_t highCapacityEraseTimeout; /*!< High-capacity erase timeout [223] */ 991 uint8_t highCapacityEraseUnitSize; /*!< High-capacity erase unit size [224] */ 992 uint8_t accessSize; /*!< Access size [225] */ 993 uint8_t bootSizeMultiplier; /*!< Boot partition size [226] */ 994 uint8_t bootInformation; /*!< Boot information [228] */ 995 uint8_t secureTrimMultiplier; /*!< secure trim multiplier[229]*/ 996 uint8_t secureEraseMultiplier; /*!< secure erase multiplier[230]*/ 997 uint8_t secureFeatureSupport; /*!< secure feature support[231]*/ 998 uint32_t trimMultiplier; /*!< trim multiplier[232]*/ 999 uint8_t minReadPerformance8bitAt52MHZDDR; /*!< Minimum read performance for 8bit at DDR 52MHZ[234]*/ 1000 uint8_t minWritePerformance8bitAt52MHZDDR; /*!< Minimum write performance for 8bit at DDR 52MHZ[235]*/ 1001 uint8_t powerClass200MHZVCCQ130VVCC360V; /*!< power class for 200MHZ, at VCCQ= 1.3V,VCC=3.6V[236]*/ 1002 uint8_t powerClass200MHZVCCQ195VVCC360V; /*!< power class for 200MHZ, at VCCQ= 1.95V,VCC=3.6V[237]*/ 1003 uint8_t powerClass52MHZDDR195V; /*!< power class for 52MHZ,DDR at Vcc 1.95V[238]*/ 1004 uint8_t powerClass52MHZDDR360V; /*!< power class for 52MHZ,DDR at Vcc 3.6V[239]*/ 1005 uint8_t iniTimeoutAP; /*!< 1st initialization time after partitioning[241]*/ 1006 uint32_t correctPrgSectorNum; /*!< correct prg sectors number[245-242]*/ 1007 uint8_t bkOpsStatus; /*!< background operations status[246]*/ 1008 uint8_t powerOffNotifyTimeout; /*!< power off notification timeout[247]*/ 1009 uint8_t genericCMD6Timeout; /*!< generic CMD6 timeout[248]*/ 1010 uint32_t cacheSize; /*!< cache size[252-249]*/ 1011 uint8_t powerClass200MHZDDR360V; /*!< power class for 200MHZ, DDR at VCC=2.6V[253]*/ 1012 uint32_t fwVer[2U]; /*!< fw VERSION [261-254]*/ 1013 uint16_t deviveVer; /*!< device version[263-262]*/ 1014 uint8_t optimalTrimSize; /*!< optimal trim size[264]*/ 1015 uint8_t optimalWriteSize; /*!< optimal write size[265]*/ 1016 uint8_t optimalReadSize; /*!< optimal read size[266]*/ 1017 uint8_t preEolInfo; /*!< pre EOL information[267]*/ 1018 uint8_t deviceLifeTimeEstimationA; /*!< device life time estimation typeA[268]*/ 1019 uint8_t deviceLifeTimeEstimationB; /*!< device life time estimation typeB[269]*/ 1020 uint32_t correctPrgFWSectorNum; /*!< number of FW sectors correctly programmed[305-302]*/ 1021 uint32_t ffuArg; /*!< FFU argument[490-487]*/ 1022 uint8_t operationCodeTimeout; /*!< operation code timeout[491]*/ 1023 uint8_t supportMode; /*!< support mode [493]*/ 1024 uint8_t extPartitionSupport; /*!< extended partition attribute support[494]*/ 1025 uint8_t largeUnitSize; /*!< large unit size[495]*/ 1026 uint8_t contextManageCap; /*!< context management capability[496]*/ 1027 uint8_t tagResourceSize; /*!< tag resource size[497]*/ 1028 uint8_t tagUnitSize; /*!< tag unit size[498]*/ 1029 uint8_t maxPackedWriteCmd; /*!< max packed write cmd[500]*/ 1030 uint8_t maxPackedReadCmd; /*!< max packed read cmd[501]*/ 1031 uint8_t hpiFeature; /*!< HPI feature[503]*/ 1032 uint8_t supportedCommandSet; /*!< Supported Command Sets [504] */ 1033 uint8_t extSecurityCmdError; /*!< extended security commands error[505]*/ 1034 } mmc_extended_csd_t; 1035 1036 /*! @brief The bit shift for COMMAND SET field in SWITCH command. */ 1037 #define MMC_SWITCH_COMMAND_SET_SHIFT (0U) 1038 /*! @brief The bit mask for COMMAND set field in SWITCH command. */ 1039 #define MMC_SWITCH_COMMAND_SET_MASK (0x00000007U) 1040 /*! @brief The bit shift for VALUE field in SWITCH command */ 1041 #define MMC_SWITCH_VALUE_SHIFT (8U) 1042 /*! @brief The bit mask for VALUE field in SWITCH command */ 1043 #define MMC_SWITCH_VALUE_MASK (0x0000FF00U) 1044 /*! @brief The bit shift for BYTE INDEX field in SWITCH command */ 1045 #define MMC_SWITCH_BYTE_INDEX_SHIFT (16U) 1046 /*! @brief The bit mask for BYTE INDEX field in SWITCH command */ 1047 #define MMC_SWITCH_BYTE_INDEX_MASK (0x00FF0000U) 1048 /*! @brief The bit shift for ACCESS MODE field in SWITCH command */ 1049 #define MMC_SWITCH_ACCESS_MODE_SHIFT (24U) 1050 /*! @brief The bit mask for ACCESS MODE field in SWITCH command */ 1051 #define MMC_SWTICH_ACCESS_MODE_MASK (0x03000000U) 1052 1053 /*! @brief MMC Extended CSD configuration. */ 1054 typedef struct _mmc_extended_csd_config 1055 { 1056 mmc_command_set_t commandSet; /*!< Command set */ 1057 uint8_t ByteValue; /*!< The value to set */ 1058 uint8_t ByteIndex; /*!< The byte index in Extended CSD(mmc_extended_csd_index_t) */ 1059 mmc_extended_csd_access_mode_t accessMode; /*!< Access mode */ 1060 } mmc_extended_csd_config_t; 1061 1062 #endif /* _FSL_SPECIFICATION_H_ */ 1063