1 /*
2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
3 * Copyright 2016-2017 NXP
4 *
5 * Redistribution and use in source and binary forms, with or without modification,
6 * are permitted provided that the following conditions are met:
7 *
8 * o Redistributions of source code must retain the above copyright notice, this list
9 * of conditions and the following disclaimer.
10 *
11 * o Redistributions in binary form must reproduce the above copyright notice, this
12 * list of conditions and the following disclaimer in the documentation and/or
13 * other materials provided with the distribution.
14 *
15 * o Neither the name of the copyright holder nor the names of its
16 * contributors may be used to endorse or promote products derived from this
17 * software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
31 #include "fsl_cmt.h"
32
33 /*******************************************************************************
34 * Definitions
35 ******************************************************************************/
36
37 /* The standard intermediate frequency (IF). */
38 #define CMT_INTERMEDIATEFREQUENCY_8MHZ (8000000U)
39 /* CMT data modulate mask. */
40 #define CMT_MODULATE_COUNT_WIDTH (8U)
41 /* CMT diver 1. */
42 #define CMT_CMTDIV_ONE (1)
43 /* CMT diver 2. */
44 #define CMT_CMTDIV_TWO (2)
45 /* CMT diver 4. */
46 #define CMT_CMTDIV_FOUR (4)
47 /* CMT diver 8. */
48 #define CMT_CMTDIV_EIGHT (8)
49
50 /*******************************************************************************
51 * Prototypes
52 ******************************************************************************/
53
54 /*!
55 * @brief Get instance number for CMT module.
56 *
57 * @param base CMT peripheral base address.
58 */
59 static uint32_t CMT_GetInstance(CMT_Type *base);
60
61 /*******************************************************************************
62 * Variables
63 ******************************************************************************/
64
65 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
66 /*! @brief Pointers to cmt clocks for each instance. */
67 static const clock_ip_name_t s_cmtClock[FSL_FEATURE_SOC_CMT_COUNT] = CMT_CLOCKS;
68 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
69
70 /*! @brief Pointers to cmt bases for each instance. */
71 static CMT_Type *const s_cmtBases[] = CMT_BASE_PTRS;
72
73 /*! @brief Pointers to cmt IRQ number for each instance. */
74 static const IRQn_Type s_cmtIrqs[] = CMT_IRQS;
75
76 /*******************************************************************************
77 * Codes
78 ******************************************************************************/
79
CMT_GetInstance(CMT_Type * base)80 static uint32_t CMT_GetInstance(CMT_Type *base)
81 {
82 uint32_t instance;
83
84 /* Find the instance index from base address mappings. */
85 for (instance = 0; instance < ARRAY_SIZE(s_cmtBases); instance++)
86 {
87 if (s_cmtBases[instance] == base)
88 {
89 break;
90 }
91 }
92
93 assert(instance < ARRAY_SIZE(s_cmtBases));
94
95 return instance;
96 }
97
CMT_GetDefaultConfig(cmt_config_t * config)98 void CMT_GetDefaultConfig(cmt_config_t *config)
99 {
100 assert(config);
101
102 /* Default infrared output is enabled and set with high active, the divider is set to 1. */
103 config->isInterruptEnabled = false;
104 config->isIroEnabled = true;
105 config->iroPolarity = kCMT_IROActiveHigh;
106 config->divider = kCMT_SecondClkDiv1;
107 }
108
CMT_Init(CMT_Type * base,const cmt_config_t * config,uint32_t busClock_Hz)109 void CMT_Init(CMT_Type *base, const cmt_config_t *config, uint32_t busClock_Hz)
110 {
111 assert(config);
112 assert(busClock_Hz >= CMT_INTERMEDIATEFREQUENCY_8MHZ);
113
114 uint8_t divider;
115
116 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
117 /* Ungate clock. */
118 CLOCK_EnableClock(s_cmtClock[CMT_GetInstance(base)]);
119 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
120
121 /* Sets clock divider. The divider set in pps should be set
122 to make sycClock_Hz/divder = 8MHz */
123 base->PPS = CMT_PPS_PPSDIV(busClock_Hz / CMT_INTERMEDIATEFREQUENCY_8MHZ - 1);
124 divider = base->MSC;
125 divider &= ~CMT_MSC_CMTDIV_MASK;
126 divider |= CMT_MSC_CMTDIV(config->divider);
127 base->MSC = divider;
128
129 /* Set the IRO signal. */
130 base->OC = CMT_OC_CMTPOL(config->iroPolarity) | CMT_OC_IROPEN(config->isIroEnabled);
131
132 /* Set interrupt. */
133 if (config->isInterruptEnabled)
134 {
135 CMT_EnableInterrupts(base, kCMT_EndOfCycleInterruptEnable);
136 EnableIRQ(s_cmtIrqs[CMT_GetInstance(base)]);
137 }
138 }
139
CMT_Deinit(CMT_Type * base)140 void CMT_Deinit(CMT_Type *base)
141 {
142 /*Disable the CMT modulator. */
143 base->MSC = 0;
144
145 /* Disable the interrupt. */
146 CMT_DisableInterrupts(base, kCMT_EndOfCycleInterruptEnable);
147 DisableIRQ(s_cmtIrqs[CMT_GetInstance(base)]);
148
149 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
150 /* Gate the clock. */
151 CLOCK_DisableClock(s_cmtClock[CMT_GetInstance(base)]);
152 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
153 }
154
CMT_SetMode(CMT_Type * base,cmt_mode_t mode,cmt_modulate_config_t * modulateConfig)155 void CMT_SetMode(CMT_Type *base, cmt_mode_t mode, cmt_modulate_config_t *modulateConfig)
156 {
157 uint8_t mscReg = base->MSC;
158
159 /* Judge the mode. */
160 if (mode != kCMT_DirectIROCtl)
161 {
162 assert(modulateConfig);
163
164 /* Set carrier generator. */
165 CMT_SetCarrirGenerateCountOne(base, modulateConfig->highCount1, modulateConfig->lowCount1);
166 if (mode == kCMT_FSKMode)
167 {
168 CMT_SetCarrirGenerateCountTwo(base, modulateConfig->highCount2, modulateConfig->lowCount2);
169 }
170
171 /* Set carrier modulator. */
172 CMT_SetModulateMarkSpace(base, modulateConfig->markCount, modulateConfig->spaceCount);
173 mscReg &= ~ (CMT_MSC_FSK_MASK | CMT_MSC_BASE_MASK);
174 mscReg |= mode;
175 }
176 else
177 {
178 mscReg &= ~CMT_MSC_MCGEN_MASK;
179 }
180 /* Set the CMT mode. */
181 base->MSC = mscReg;
182 }
183
CMT_GetMode(CMT_Type * base)184 cmt_mode_t CMT_GetMode(CMT_Type *base)
185 {
186 uint8_t mode = base->MSC;
187
188 if (!(mode & CMT_MSC_MCGEN_MASK))
189 { /* Carrier modulator disabled and the IRO signal is in direct software control. */
190 return kCMT_DirectIROCtl;
191 }
192 else
193 {
194 /* Carrier modulator is enabled. */
195 if (mode & CMT_MSC_BASE_MASK)
196 {
197 /* Base band mode. */
198 return kCMT_BasebandMode;
199 }
200 else if (mode & CMT_MSC_FSK_MASK)
201 {
202 /* FSK mode. */
203 return kCMT_FSKMode;
204 }
205 else
206 {
207 /* Time mode. */
208 return kCMT_TimeMode;
209 }
210 }
211 }
212
CMT_GetCMTFrequency(CMT_Type * base,uint32_t busClock_Hz)213 uint32_t CMT_GetCMTFrequency(CMT_Type *base, uint32_t busClock_Hz)
214 {
215 uint32_t frequency;
216 uint32_t divider;
217
218 /* Get intermediate frequency. */
219 frequency = busClock_Hz / ((base->PPS & CMT_PPS_PPSDIV_MASK) + 1);
220
221 /* Get the second divider. */
222 divider = ((base->MSC & CMT_MSC_CMTDIV_MASK) >> CMT_MSC_CMTDIV_SHIFT);
223 /* Get CMT frequency. */
224 switch ((cmt_second_clkdiv_t)divider)
225 {
226 case kCMT_SecondClkDiv1:
227 frequency = frequency / CMT_CMTDIV_ONE;
228 break;
229 case kCMT_SecondClkDiv2:
230 frequency = frequency / CMT_CMTDIV_TWO;
231 break;
232 case kCMT_SecondClkDiv4:
233 frequency = frequency / CMT_CMTDIV_FOUR;
234 break;
235 case kCMT_SecondClkDiv8:
236 frequency = frequency / CMT_CMTDIV_EIGHT;
237 break;
238 default:
239 frequency = frequency / CMT_CMTDIV_ONE;
240 break;
241 }
242
243 return frequency;
244 }
245
CMT_SetModulateMarkSpace(CMT_Type * base,uint32_t markCount,uint32_t spaceCount)246 void CMT_SetModulateMarkSpace(CMT_Type *base, uint32_t markCount, uint32_t spaceCount)
247 {
248 /* Set modulate mark. */
249 base->CMD1 = (markCount >> CMT_MODULATE_COUNT_WIDTH) & CMT_CMD1_MB_MASK;
250 base->CMD2 = (markCount & CMT_CMD2_MB_MASK);
251 /* Set modulate space. */
252 base->CMD3 = (spaceCount >> CMT_MODULATE_COUNT_WIDTH) & CMT_CMD3_SB_MASK;
253 base->CMD4 = spaceCount & CMT_CMD4_SB_MASK;
254 }
255
CMT_SetIroState(CMT_Type * base,cmt_infrared_output_state_t state)256 void CMT_SetIroState(CMT_Type *base, cmt_infrared_output_state_t state)
257 {
258 uint8_t ocReg = base->OC;
259
260 ocReg &= ~CMT_OC_IROL_MASK;
261 ocReg |= CMT_OC_IROL(state);
262
263 /* Set the infrared output signal control. */
264 base->OC = ocReg;
265 }
266