1 /** @file system.c
2 * @brief System Driver Source File
3 * @date 29.May.2013
4 * @version 03.05.02
5 *
6 * This file contains:
7 * - API Functions
8 * .
9 * which are relevant for the System driver.
10 */
11
12 /* (c) Texas Instruments 2009-2013, All rights reserved. */
13
14 /* USER CODE BEGIN (0) */
15 /* USER CODE END */
16
17
18 /* Include Files */
19
20 #include "system.h"
21 #include "sys_selftest.h"
22 #include "sys_pcr.h"
23 #include "pinmux.h"
24
25 /* USER CODE BEGIN (1) */
26 /* USER CODE END */
27
28 /** @fn void systemInit(void)
29 * @brief Initializes System Driver
30 *
31 * This function initializes the System driver.
32 *
33 */
34
35 /* USER CODE BEGIN (2) */
36 /* USER CODE END */
37
setupPLL(void)38 void setupPLL(void)
39 {
40
41 /* USER CODE BEGIN (3) */
42 /* USER CODE END */
43
44 /** - Configure PLL control registers */
45 /** @b Initialize @b Pll1: */
46
47 /** - Setup pll control register 1:
48 * - Setup reset on oscillator slip
49 * - Setup bypass on pll slip
50 * - setup Pll output clock divider to max before Lock
51 * - Setup reset on oscillator fail
52 * - Setup reference clock divider
53 * - Setup Pll multiplier
54 */
55 systemREG1->PLLCTL1 = 0x00000000U
56 | 0x20000000U
57 | ((0x1FU)<< 24U)
58 | 0x00000000U
59 | ((6U - 1U)<< 16U)
60 | ((150U - 1U)<< 8U);
61
62 /** - Setup pll control register 2
63 * - Enable/Disable frequency modulation
64 * - Setup spreading rate
65 * - Setup bandwidth adjustment
66 * - Setup internal Pll output divider
67 * - Setup spreading amount
68 */
69 systemREG1->PLLCTL2 = 0x00000000U
70 | (255U << 22U)
71 | (7U << 12U)
72 | ((2U - 1U)<< 9U)
73 | 61U;
74
75 /** @b Initialize @b Pll2: */
76
77 /** - Setup pll2 control register :
78 * - setup Pll output clock divider to max before Lock
79 * - Setup reference clock divider
80 * - Setup internal Pll output divider
81 * - Setup Pll multiplier
82 */
83 systemREG2->PLLCTL3 = ((2U - 1U) << 29U)
84 | ((0x1FU)<< 24U)
85 | ((6U - 1U)<< 16U)
86 | ((150U - 1U) << 8U);
87
88 /** - Enable PLL(s) to start up or Lock */
89 systemREG1->CSDIS = 0x00000000U
90 | 0x00000000U
91 | 0x00000008U
92 | 0x00000080U
93 | 0x00000000U
94 | 0x00000000U
95 | 0x00000000U;
96 }
97
trimLPO(void)98 void trimLPO(void)
99 {
100
101 /* USER CODE BEGIN (4) */
102 /* USER CODE END */
103
104 /** @b Initialize Lpo: */
105 /** Load TRIM values from OTP if present else load user defined values */
106 if(LPO_TRIM_VALUE != 0xFFFFU)
107 {
108
109 systemREG1->LPOMONCTL = (1U << 24U)
110 | LPO_TRIM_VALUE;
111 }
112 else
113 {
114
115 systemREG1->LPOMONCTL = (1U << 24U)
116 | (16U << 8U)
117 | 8U;
118 }
119
120 /* USER CODE BEGIN (5) */
121 /* USER CODE END */
122
123 }
124
setupFlash(void)125 void setupFlash(void)
126 {
127
128 /* USER CODE BEGIN (6) */
129 /* USER CODE END */
130
131 /** - Setup flash read mode, address wait states and data wait states */
132 flashWREG->FRDCNTL = 0x00000000U
133 | (3U << 8U)
134 | (1U << 4U)
135 | 1U;
136
137 /** - Setup flash access wait states for bank 7 */
138 FSM_WR_ENA_HL = 0x5U;
139 EEPROM_CONFIG_HL = 0x00000002U
140 | (3U << 16U) ;
141
142 /* USER CODE BEGIN (7) */
143 /* USER CODE END */
144
145 /** - Disable write access to flash state machine registers */
146 FSM_WR_ENA_HL = 0xAU;
147
148 /** - Setup flash bank power modes */
149 flashWREG->FBFALLBACK = 0x00000000U
150 | (SYS_ACTIVE << 14U)
151 | (SYS_SLEEP << 12U)
152 | (SYS_SLEEP << 10U)
153 | (SYS_SLEEP << 8U)
154 | (SYS_SLEEP << 6U)
155 | (SYS_SLEEP << 4U)
156 | (SYS_ACTIVE << 2U)
157 | SYS_ACTIVE;
158
159 /* USER CODE BEGIN (8) */
160 /* USER CODE END */
161
162 }
163
periphInit(void)164 void periphInit(void)
165 {
166
167 /* USER CODE BEGIN (9) */
168 /* USER CODE END */
169
170 /** - Disable Peripherals before peripheral powerup*/
171 systemREG1->CLKCNTL &= 0xFFFFFEFFU;
172
173 /** - Release peripherals from reset and enable clocks to all peripherals */
174 /** - Power-up all peripherals */
175 pcrREG->PSPWRDWNCLR0 = 0xFFFFFFFFU;
176 pcrREG->PSPWRDWNCLR1 = 0xFFFFFFFFU;
177 pcrREG->PSPWRDWNCLR2 = 0xFFFFFFFFU;
178 pcrREG->PSPWRDWNCLR3 = 0xFFFFFFFFU;
179
180 /** - Enable Peripherals */
181 systemREG1->CLKCNTL |= 1U << 8U;
182
183 /* USER CODE BEGIN (10) */
184 /* USER CODE END */
185
186 }
187
mapClocks(void)188 void mapClocks(void)
189 {
190
191 /* USER CODE BEGIN (11) */
192 /* USER CODE END */
193
194 /** @b Initialize @b Clock @b Tree: */
195 /** - Disable / Enable clock domain */
196 systemREG1->CDDIS= (FALSE << 4U ) /* AVCLK 1 OFF */
197 |(TRUE << 5U ) /* AVCLK 2 OFF */
198 |(FALSE << 8U ) /* VCLK3 OFF */
199 |(FALSE << 9U ) /* VCLK4 OFF */
200 |(FALSE << 10U) /* AVCLK 3 OFF */
201 |(FALSE << 11U); /* AVCLK 4 OFF */
202
203
204 /* Work Around for Errata SYS#46:
205 *
206 * Errata Description:
207 * Clock Source Switching Not Qualified with Clock Source Enable And Clock Source Valid
208 * Workaround:
209 * Always check the CSDIS register to make sure the clock source is turned on and check
210 * the CSVSTAT register to make sure the clock source is valid. Then write to GHVSRC to switch the clock.
211 */
212 /** - Wait for until clocks are locked */
213 while ((systemREG1->CSVSTAT & ((systemREG1->CSDIS ^ 0xFFU) & 0xFFU)) != ((systemREG1->CSDIS ^ 0xFFU) & 0xFFU))
214 {
215 } /* Wait */
216
217 /* USER CODE BEGIN (12) */
218 /* USER CODE END */
219
220 /* Now the PLLs are locked and the PLL outputs can be sped up */
221 /* The R-divider was programmed to be 0xF. Now this divider is changed to programmed value */
222 systemREG1->PLLCTL1 = (systemREG1->PLLCTL1 & 0xE0FFFFFFU)|((1U - 1U)<< 24U);
223 systemREG2->PLLCTL3 = (systemREG2->PLLCTL3 & 0xE0FFFFFFU)|((1U - 1U)<< 24U);
224
225 /** - Map device clock domains to desired sources and configure top-level dividers */
226 /** - All clock domains are working off the default clock sources until now */
227 /** - The below assignments can be easily modified using the HALCoGen GUI */
228
229 /** - Setup GCLK, HCLK and VCLK clock source for normal operation, power down mode and after wakeup */
230 systemREG1->GHVSRC = (SYS_PLL1 << 24U)
231 | (SYS_PLL1 << 16U)
232 | SYS_PLL1;
233
234 /** - Setup synchronous peripheral clock dividers for VCLK1, VCLK2, VCLK3 */
235 systemREG1->CLKCNTL = (systemREG1->CLKCNTL & 0xF0F0FFFFU)
236 | (1U << 24U)
237 | (1U << 16U);
238 systemREG2->CLK2CNTL = (systemREG2->CLK2CNTL & 0xFFFFF0F0U)
239 | (1U) << 8U
240 | (1U);
241
242 /* USER CODE BEGIN (13) */
243 /* USER CODE END */
244
245 /** - Setup RTICLK1 and RTICLK2 clocks */
246 systemREG1->RCLKSRC = (1U << 24U)
247 | (SYS_VCLK << 16U)
248 | (1U << 8U)
249 | SYS_VCLK;
250
251 /** - Setup asynchronous peripheral clock sources for AVCLK1 and AVCLK2 */
252 systemREG1->VCLKASRC = (SYS_VCLK << 8U)
253 | SYS_VCLK;
254
255 systemREG2->VCLKACON1 = ((1U - 1U ) << 24U)
256 | (0U << 20U)
257 | (SYS_VCLK << 16U)
258 | ((1U - 1U ) << 8U)
259 | (0U << 4U)
260 | SYS_VCLK;
261
262 /* USER CODE BEGIN (14) */
263 /* USER CODE END */
264
265 }
266
systemInit(void)267 void systemInit(void)
268 {
269 /* USER CODE BEGIN (15) */
270 /* USER CODE END */
271
272 /* Configure PLL control registers and enable PLLs.
273 * The PLL takes (127 + 1024 * NR) oscillator cycles to acquire lock.
274 * This initialization sequence performs all the tasks that are not
275 * required to be done at full application speed while the PLL locks.
276 */
277 setupPLL();
278
279 /* USER CODE BEGIN (16) */
280 /* USER CODE END */
281
282 /* Run eFuse controller start-up checks and start eFuse controller ECC self-test.
283 * This includes a check for the eFuse controller error outputs to be stuck-at-zero.
284 */
285 //efcCheck();
286
287 /* USER CODE BEGIN (17) */
288 /* USER CODE END */
289
290 /* Enable clocks to peripherals and release peripheral reset */
291 periphInit();
292
293 /* USER CODE BEGIN (18) */
294 /* USER CODE END */
295
296 /* Configure device-level multiplexing and I/O multiplexing */
297 //muxInit();
298
299 /* USER CODE BEGIN (19) */
300 /* USER CODE END */
301
302 #if 0
303 /* Wait for eFuse controller self-test to complete and check results */
304 if ((!checkefcSelfTest()) !=0U) /* eFuse controller ECC logic self-test failed */
305 {
306 efcClass2Error(); /* device operation is not reliable */
307 }
308 #endif
309 /* USER CODE BEGIN (20) */
310 /* USER CODE END */
311
312 /** - Set up flash address and data wait states based on the target CPU clock frequency
313 * The number of address and data wait states for the target CPU clock frequency are specified
314 * in the specific part's datasheet.
315 */
316 setupFlash();
317
318 /* USER CODE BEGIN (21) */
319 /* USER CODE END */
320
321 /** - Configure the LPO such that HF LPO is as close to 10MHz as possible */
322 trimLPO();
323
324 /* USER CODE BEGIN (23) */
325 /* USER CODE END */
326
327 /** - Wait for PLLs to start up and map clock domains to desired clock sources */
328 mapClocks();
329
330 /* USER CODE BEGIN (24) */
331 /* USER CODE END */
332
333 /** - set ECLK pins functional mode */
334 systemREG1->SYSPC1 = 0U;
335
336 /** - set ECLK pins default output value */
337 systemREG1->SYSPC4 = 0U;
338
339 /** - set ECLK pins output direction */
340 systemREG1->SYSPC2 = 1U;
341
342 /** - set ECLK pins open drain enable */
343 systemREG1->SYSPC7 = 0U;
344
345 /** - set ECLK pins pullup/pulldown enable */
346 systemREG1->SYSPC8 = 0U;
347
348 /** - set ECLK pins pullup/pulldown select */
349 systemREG1->SYSPC9 = 1U;
350
351 /** - Setup ECLK */
352 systemREG1->ECPCNTL = (0U << 24U)
353 | (0U << 23U)
354 | ((8U - 1U) & 0xFFFFU);
355
356 /* USER CODE BEGIN (25) */
357 /* USER CODE END */
358 }
359
systemPowerDown(uint32 mode)360 void systemPowerDown(uint32 mode)
361 {
362
363 /* USER CODE BEGIN (26) */
364 /* USER CODE END */
365
366 /* Disable clock sources */
367 systemREG1->CSDISSET = mode & 0x000000FFU;
368
369 /* Disable clock domains */
370 systemREG1->CDDIS = (mode >> 8U) & 0x00000FFFU;
371
372 /* Idle CPU */
373 /*SAFETYMCUSW 88 S MR:2.1 <REVIEWED> "Assembly in C needed" */
374 asm(" wfi");
375
376 /* USER CODE BEGIN (27) */
377 /* USER CODE END */
378
379 }
380
381 /* USER CODE BEGIN (28) */
382 /* USER CODE END */
383
384 /** @fn void systemGetConfigValue(system_config_reg_t *config_reg, config_value_type_t type)
385 * @brief Get the initial or current values of the configuration registers
386 *
387 * @param[in] *config_reg: pointer to the struct to which the initial or current value of the configuration registers need to be stored
388 * @param[in] type: whether initial or current value of the configuration registers need to be stored
389 * - InitialValue: initial value of the configuration registers will be stored in the struct pointed by config_reg
390 * - CurrentValue: initial value of the configuration registers will be stored in the struct pointed by config_reg
391 *
392 * This function will copy the initial or current value (depending on the parameter 'type') of the configuration registers to the struct pointed by config_reg
393 *
394 */
395
systemGetConfigValue(system_config_reg_t * config_reg,config_value_type_t type)396 void systemGetConfigValue(system_config_reg_t *config_reg, config_value_type_t type)
397 {
398 if (type == InitialValue)
399 {
400 config_reg->CONFIG_SYSPC1 = SYS_SYSPC1_CONFIGVALUE;
401 config_reg->CONFIG_SYSPC2 = SYS_SYSPC2_CONFIGVALUE;
402 config_reg->CONFIG_SYSPC7 = SYS_SYSPC7_CONFIGVALUE;
403 config_reg->CONFIG_SYSPC8 = SYS_SYSPC8_CONFIGVALUE;
404 config_reg->CONFIG_SYSPC9 = SYS_SYSPC9_CONFIGVALUE;
405 config_reg->CONFIG_CSDIS = SYS_CSDIS_CONFIGVALUE;
406 config_reg->CONFIG_CDDIS = SYS_CDDIS_CONFIGVALUE;
407 config_reg->CONFIG_GHVSRC = SYS_GHVSRC_CONFIGVALUE;
408 config_reg->CONFIG_VCLKASRC = SYS_VCLKASRC_CONFIGVALUE;
409 config_reg->CONFIG_RCLKSRC = SYS_RCLKSRC_CONFIGVALUE;
410 config_reg->CONFIG_MSTGCR = SYS_MSTGCR_CONFIGVALUE;
411 config_reg->CONFIG_MINITGCR = SYS_MINITGCR_CONFIGVALUE;
412 config_reg->CONFIG_MSINENA = SYS_MSINENA_CONFIGVALUE;
413 config_reg->CONFIG_PLLCTL1 = SYS_PLLCTL1_CONFIGVALUE_2;
414 config_reg->CONFIG_PLLCTL2 = SYS_PLLCTL2_CONFIGVALUE;
415 config_reg->CONFIG_UERFLAG = SYS_UERFLAG_CONFIGVALUE;
416 if(LPO_TRIM_VALUE != 0xFFFFU)
417 {
418 config_reg->CONFIG_LPOMONCTL = SYS_LPOMONCTL_CONFIGVALUE_1;
419 }
420 else
421 {
422 config_reg->CONFIG_LPOMONCTL = SYS_LPOMONCTL_CONFIGVALUE_2;
423 }
424 config_reg->CONFIG_CLKTEST = SYS_CLKTEST_CONFIGVALUE;
425 config_reg->CONFIG_DFTCTRLREG1 = SYS_DFTCTRLREG1_CONFIGVALUE;
426 config_reg->CONFIG_DFTCTRLREG2 = SYS_DFTCTRLREG2_CONFIGVALUE;
427 config_reg->CONFIG_GPREG1 = SYS_GPREG1_CONFIGVALUE;
428 config_reg->CONFIG_RAMGCR = SYS_RAMGCR_CONFIGVALUE;
429 config_reg->CONFIG_BMMCR1 = SYS_BMMCR1_CONFIGVALUE;
430 config_reg->CONFIG_MMUGCR = SYS_MMUGCR_CONFIGVALUE;
431 config_reg->CONFIG_CLKCNTL = SYS_CLKCNTL_CONFIGVALUE;
432 config_reg->CONFIG_ECPCNTL = SYS_ECPCNTL_CONFIGVALUE;
433 config_reg->CONFIG_DEVCR1 = SYS_DEVCR1_CONFIGVALUE;
434 config_reg->CONFIG_SYSECR = SYS_SYSECR_CONFIGVALUE;
435
436 config_reg->CONFIG_PLLCTL3 = SYS2_PLLCTL3_CONFIGVALUE_2;
437 config_reg->CONFIG_STCCLKDIV = SYS2_STCCLKDIV_CONFIGVALUE;
438 config_reg->CONFIG_CLK2CNTL = SYS2_CLK2CNTL_CONFIGVALUE;
439 config_reg->CONFIG_VCLKACON1 = SYS2_VCLKACON1_CONFIGVALUE;
440 config_reg->CONFIG_CLKSLIP = SYS2_CLKSLIP_CONFIGVALUE;
441 config_reg->CONFIG_EFC_CTLEN = SYS2_EFC_CTLEN_CONFIGVALUE;
442 }
443 else
444 {
445 config_reg->CONFIG_SYSPC1 = systemREG1->SYSPC1;
446 config_reg->CONFIG_SYSPC2 = systemREG1->SYSPC2;
447 config_reg->CONFIG_SYSPC7 = systemREG1->SYSPC7;
448 config_reg->CONFIG_SYSPC8 = systemREG1->SYSPC8;
449 config_reg->CONFIG_SYSPC9 = systemREG1->SYSPC9;
450 config_reg->CONFIG_CSDIS = systemREG1->CSDIS;
451 config_reg->CONFIG_CDDIS = systemREG1->CDDIS;
452 config_reg->CONFIG_GHVSRC = systemREG1->GHVSRC;
453 config_reg->CONFIG_VCLKASRC = systemREG1->VCLKASRC;
454 config_reg->CONFIG_RCLKSRC = systemREG1->RCLKSRC;
455 config_reg->CONFIG_MSTGCR = systemREG1->MSTGCR;
456 config_reg->CONFIG_MINITGCR = systemREG1->MINITGCR;
457 config_reg->CONFIG_MSINENA = systemREG1->MSINENA;
458 config_reg->CONFIG_PLLCTL1 = systemREG1->PLLCTL1;
459 config_reg->CONFIG_PLLCTL2 = systemREG1->PLLCTL2;
460 config_reg->CONFIG_UERFLAG = systemREG1->UERFLAG;
461 config_reg->CONFIG_LPOMONCTL = systemREG1->LPOMONCTL;
462 config_reg->CONFIG_CLKTEST = systemREG1->CLKTEST;
463 config_reg->CONFIG_DFTCTRLREG1 = systemREG1->DFTCTRLREG1;
464 config_reg->CONFIG_DFTCTRLREG2 = systemREG1->DFTCTRLREG2;
465 config_reg->CONFIG_GPREG1 = systemREG1->GPREG1;
466 config_reg->CONFIG_RAMGCR = systemREG1->RAMGCR;
467 config_reg->CONFIG_BMMCR1 = systemREG1->BMMCR1;
468 config_reg->CONFIG_MMUGCR = systemREG1->MMUGCR;
469 config_reg->CONFIG_CLKCNTL = systemREG1->CLKCNTL;
470 config_reg->CONFIG_ECPCNTL = systemREG1->ECPCNTL;
471 config_reg->CONFIG_DEVCR1 = systemREG1->DEVCR1;
472 config_reg->CONFIG_SYSECR = systemREG1->SYSECR;
473
474 config_reg->CONFIG_PLLCTL3 = systemREG2->PLLCTL3;
475 config_reg->CONFIG_STCCLKDIV = systemREG2->STCCLKDIV;
476 config_reg->CONFIG_CLK2CNTL = systemREG2->CLK2CNTL;
477 config_reg->CONFIG_VCLKACON1 = systemREG2->VCLKACON1;
478 config_reg->CONFIG_CLKSLIP = systemREG2->CLKSLIP;
479 config_reg->CONFIG_EFC_CTLEN = systemREG2->EFC_CTLEN;
480 }
481 }
482
483 /** @fn void tcmflashGetConfigValue(tcmflash_config_reg_t *config_reg, config_value_type_t type)
484 * @brief Get the initial or current values of the configuration registers
485 *
486 * @param[in] *config_reg: pointer to the struct to which the initial or current value of the configuration registers need to be stored
487 * @param[in] type: whether initial or current value of the configuration registers need to be stored
488 * - InitialValue: initial value of the configuration registers will be stored in the struct pointed by config_reg
489 * - CurrentValue: initial value of the configuration registers will be stored in the struct pointed by config_reg
490 *
491 * This function will copy the initial or current value (depending on the parameter 'type') of the configuration registers to the struct pointed by config_reg
492 *
493 */
494
tcmflashGetConfigValue(tcmflash_config_reg_t * config_reg,config_value_type_t type)495 void tcmflashGetConfigValue(tcmflash_config_reg_t *config_reg, config_value_type_t type)
496 {
497 if (type == InitialValue)
498 {
499 config_reg-> CONFIG_FRDCNTL = TCMFLASH_FRDCNTL_CONFIGVALUE;
500 config_reg-> CONFIG_FEDACCTRL1 = TCMFLASH_FEDACCTRL1_CONFIGVALUE;
501 config_reg-> CONFIG_FEDACCTRL2 = TCMFLASH_FEDACCTRL2_CONFIGVALUE;
502 config_reg-> CONFIG_FEDACSDIS = TCMFLASH_FEDACSDIS_CONFIGVALUE;
503 config_reg-> CONFIG_FBPROT = TCMFLASH_FBPROT_CONFIGVALUE;
504 config_reg-> CONFIG_FBSE = TCMFLASH_FBSE_CONFIGVALUE;
505 config_reg-> CONFIG_FBAC = TCMFLASH_FBAC_CONFIGVALUE;
506 config_reg-> CONFIG_FBFALLBACK = TCMFLASH_FBFALLBACK_CONFIGVALUE;
507 config_reg-> CONFIG_FPAC1 = TCMFLASH_FPAC1_CONFIGVALUE;
508 config_reg-> CONFIG_FPAC2 = TCMFLASH_FPAC2_CONFIGVALUE;
509 config_reg-> CONFIG_FMAC = TCMFLASH_FMAC_CONFIGVALUE;
510 config_reg-> CONFIG_FLOCK = TCMFLASH_FLOCK_CONFIGVALUE;
511 config_reg-> CONFIG_FDIAGCTRL = TCMFLASH_FDIAGCTRL_CONFIGVALUE;
512 config_reg-> CONFIG_FEDACSDIS2 = TCMFLASH_FEDACSDIS2_CONFIGVALUE;
513 }
514 else
515 {
516 config_reg-> CONFIG_FRDCNTL = flashWREG->FRDCNTL;
517 config_reg-> CONFIG_FEDACCTRL1 = flashWREG->FEDACCTRL1;
518 config_reg-> CONFIG_FEDACCTRL2 = flashWREG->FEDACCTRL2;
519 config_reg-> CONFIG_FEDACSDIS = flashWREG->FEDACSDIS;
520 config_reg-> CONFIG_FBPROT = flashWREG->FBPROT;
521 config_reg-> CONFIG_FBSE = flashWREG->FBSE;
522 config_reg-> CONFIG_FBAC = flashWREG->FBAC;
523 config_reg-> CONFIG_FBFALLBACK = flashWREG->FBFALLBACK;
524 config_reg-> CONFIG_FPAC1 = flashWREG->FPAC1;
525 config_reg-> CONFIG_FPAC2 = flashWREG->FPAC2;
526 config_reg-> CONFIG_FMAC = flashWREG->FMAC;
527 config_reg-> CONFIG_FLOCK = flashWREG->FLOCK;
528 config_reg-> CONFIG_FDIAGCTRL = flashWREG->FDIAGCTRL;
529 config_reg-> CONFIG_FEDACSDIS2 = flashWREG->FEDACSDIS2;
530 }
531 }
532
533
534
535 /** @fn void sramGetConfigValue(sram_config_reg_t *config_reg, config_value_type_t type)
536 * @brief Get the initial or current values of the configuration registers
537 *
538 * @param[in] *config_reg: pointer to the struct to which the initial or current value of the configuration registers need to be stored
539 * @param[in] type: whether initial or current value of the configuration registers need to be stored
540 * - InitialValue: initial value of the configuration registers will be stored in the struct pointed by config_reg
541 * - CurrentValue: initial value of the configuration registers will be stored in the struct pointed by config_reg
542 *
543 * This function will copy the initial or current value (depending on the parameter 'type') of the configuration registers to the struct pointed by config_reg
544 *
545 */
546
sramGetConfigValue(sram_config_reg_t * config_reg,config_value_type_t type)547 void sramGetConfigValue(sram_config_reg_t *config_reg, config_value_type_t type)
548 {
549 if (type == InitialValue)
550 {
551 config_reg->CONFIG_RAMCTRL[0U] = SRAM_RAMCTRL_CONFIGVALUE;
552 config_reg->CONFIG_RAMTHRESHOLD[0U] = SRAM_RAMTHRESHOLD_CONFIGVALUE;
553 config_reg->CONFIG_RAMINTCTRL[0U] = SRAM_RAMINTCTRL_CONFIGVALUE;
554 config_reg->CONFIG_RAMTEST[0U] = SRAM_RAMTEST_CONFIGVALUE;
555 config_reg->CONFIG_RAMADDRDECVECT[0U] = SRAM_RAMADDRDECVECT_CONFIGVALUE;
556
557 config_reg->CONFIG_RAMCTRL[1U] = SRAM_RAMCTRL_CONFIGVALUE;
558 config_reg->CONFIG_RAMTHRESHOLD[1U] = SRAM_RAMTHRESHOLD_CONFIGVALUE;
559 config_reg->CONFIG_RAMINTCTRL[1U] = SRAM_RAMINTCTRL_CONFIGVALUE;
560 config_reg->CONFIG_RAMTEST[1U] = SRAM_RAMTEST_CONFIGVALUE;
561 config_reg->CONFIG_RAMADDRDECVECT[1U] = SRAM_RAMADDRDECVECT_CONFIGVALUE;
562 }
563 else
564 {
565 config_reg->CONFIG_RAMCTRL[0U] = tcram1REG->RAMCTRL;
566 config_reg->CONFIG_RAMTHRESHOLD[0U] = tcram1REG->RAMTHRESHOLD;
567 config_reg->CONFIG_RAMINTCTRL[0U] = tcram1REG->RAMINTCTRL;
568 config_reg->CONFIG_RAMTEST[0U] = tcram1REG->RAMTEST;
569 config_reg->CONFIG_RAMADDRDECVECT[0U] = tcram1REG->RAMADDRDECVECT;
570
571 config_reg->CONFIG_RAMCTRL[1U] = tcram2REG->RAMCTRL;
572 config_reg->CONFIG_RAMTHRESHOLD[1U] = tcram2REG->RAMTHRESHOLD;
573 config_reg->CONFIG_RAMINTCTRL[1U] = tcram2REG->RAMINTCTRL;
574 config_reg->CONFIG_RAMTEST[1U] = tcram2REG->RAMTEST;
575 config_reg->CONFIG_RAMADDRDECVECT[1U] = tcram2REG->RAMADDRDECVECT;
576 }
577 }
578