1 /*
2 * Copyright (c) 2006-2024 RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2022-11-22 GuEe-GUI first version
9 */
10
11 /*
12 * The Synopsys DesignWare 8250 has an extra feature whereby it detects if the
13 * LCR is written whilst busy. If it is, then a busy detect interrupt is
14 * raised, the LCR needs to be rewritten and the uart status register read.
15 */
16
17 #include <rtthread.h>
18
19 #include "8250.h"
20
21 /* Offsets for the DesignWare specific registers */
22 #define DW_UART_USR 0x1f /* UART Status Register */
23 #define DW_UART_DMASA 0xa8 /* DMA Software Ack */
24
25 #define OCTEON_UART_USR 0x27 /* UART Status Register */
26
27 #define RZN1_UART_TDMACR 0x10c /* DMA Control Register Transmit Mode */
28 #define RZN1_UART_RDMACR 0x110 /* DMA Control Register Receive Mode */
29
30 /* DesignWare specific register fields */
31 #define DW_UART_MCR_SIRE RT_BIT(6)
32
33 /* Renesas specific register fields */
34 #define RZN1_UART_xDMACR_DMA_EN RT_BIT(0)
35 #define RZN1_UART_xDMACR_1_WORD_BURST (0 << 1)
36 #define RZN1_UART_xDMACR_4_WORD_BURST (1 << 1)
37 #define RZN1_UART_xDMACR_8_WORD_BURST (2 << 1)
38 #define RZN1_UART_xDMACR_BLK_SZ(x) ((x) << 3)
39
40 /* Quirks */
41 #define DW_UART_QUIRK_OCTEON RT_BIT(0)
42 #define DW_UART_QUIRK_ARMADA_38X RT_BIT(1)
43 #define DW_UART_QUIRK_SKIP_SET_RATE RT_BIT(2)
44 #define DW_UART_QUIRK_IS_DMA_FC RT_BIT(3)
45
46 struct dw8250_platform_data
47 {
48 rt_uint8_t usr_reg;
49 rt_uint32_t cpr_val;
50 rt_uint32_t quirks;
51 };
52
53 struct dw8250
54 {
55 struct serial8250 parent;
56 struct rt_spinlock spinlock;
57
58 struct rt_clk *pclk;
59
60 rt_bool_t uart_16550_compatible;
61 struct dw8250_platform_data *platform_data;
62 };
63
64 #define to_dw8250(serial8250) rt_container_of(serial8250, struct dw8250, parent)
65
dw8250_check_lcr(struct serial8250 * serial,int value)66 static void dw8250_check_lcr(struct serial8250 *serial, int value)
67 {
68 void *offset = (void *)(serial->base + (UART_LCR << serial->regshift));
69 int tries = 1000;
70
71 /* Make sure LCR write wasn't ignored */
72 while (tries--)
73 {
74 rt_uint32_t lcr = serial->serial_in(serial, UART_LCR);
75
76 if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
77 {
78 break;
79 }
80
81 serial->serial_out(serial, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
82 serial->serial_in(serial, UART_RX);
83
84 if (serial->iotype == PORT_MMIO32)
85 {
86 HWREG32(offset) = value;
87 }
88 else if (serial->iotype == PORT_MMIO32BE)
89 {
90 HWREG32(offset) = rt_cpu_to_be32(value);
91 }
92 else
93 {
94 HWREG8(offset) = value;
95 }
96 }
97 }
98
dw8250_serial_out32(struct serial8250 * serial,int offset,int value)99 static void dw8250_serial_out32(struct serial8250 *serial, int offset, int value)
100 {
101 struct dw8250 *dw8250 = to_dw8250(serial);
102
103 HWREG32(serial->base + (offset << serial->regshift)) = value;
104
105 if (offset == UART_LCR && !dw8250->uart_16550_compatible)
106 {
107 dw8250_check_lcr(serial, value);
108 }
109 }
110
dw8250_serial_in32(struct serial8250 * serial,int offset)111 static rt_uint32_t dw8250_serial_in32(struct serial8250 *serial, int offset)
112 {
113 return HWREG32(serial->base + (offset << serial->regshift));
114 }
115
dw8250_isr(struct serial8250 * serial,int irq)116 static rt_err_t dw8250_isr(struct serial8250 *serial, int irq)
117 {
118 unsigned int iir, status;
119 struct dw8250 *dw8250 = to_dw8250(serial);
120
121 iir = serial8250_in(serial, UART_IIR);
122
123 /*
124 * If don't do this in non-DMA mode then the "RX TIMEOUT" interrupt will
125 * fire forever.
126 */
127 if ((iir & 0x3f) == UART_IIR_RX_TIMEOUT)
128 {
129 rt_base_t level = rt_spin_lock_irqsave(&dw8250->spinlock);
130
131 status = serial8250_in(serial, UART_LSR);
132
133 if (!(status & (UART_LSR_DR | UART_LSR_BI)))
134 {
135 serial8250_in(serial, UART_RX);
136 }
137
138 rt_spin_unlock_irqrestore(&dw8250->spinlock, level);
139 }
140
141 if (!(iir & UART_IIR_NO_INT))
142 {
143 rt_hw_serial_isr(&serial->parent, RT_SERIAL_EVENT_RX_IND);
144 }
145
146 if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY)
147 {
148 /* Clear the USR */
149 serial8250_in(serial, dw8250->platform_data->usr_reg);
150 }
151
152 return RT_EOK;
153 }
154
dw8250_free_resource(struct dw8250 * dw8250)155 static void dw8250_free_resource(struct dw8250 *dw8250)
156 {
157 struct serial8250 *serial = &dw8250->parent;
158
159 if (serial->base)
160 {
161 rt_iounmap(serial->base);
162 }
163
164 if (serial->clk)
165 {
166 rt_clk_disable_unprepare(serial->clk);
167 rt_clk_put(serial->clk);
168 }
169
170 if (dw8250->pclk)
171 {
172 rt_clk_disable_unprepare(dw8250->pclk);
173 rt_clk_put(dw8250->pclk);
174 }
175
176 rt_free(dw8250);
177 }
178
dw8250_remove(struct serial8250 * serial)179 static void dw8250_remove(struct serial8250 *serial)
180 {
181 struct dw8250 *dw8250 = to_dw8250(serial);
182
183 dw8250_free_resource(dw8250);
184 }
185
dw8250_probe(struct rt_platform_device * pdev)186 static rt_err_t dw8250_probe(struct rt_platform_device *pdev)
187 {
188 rt_err_t err;
189 rt_uint32_t val;
190 struct serial8250 *serial;
191 struct rt_device *dev = &pdev->parent;
192 struct dw8250 *dw8250 = serial8250_alloc(dw8250);
193 struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
194
195 if (!dw8250)
196 {
197 return -RT_ENOMEM;
198 }
199
200 serial = &dw8250->parent;
201 serial->base = rt_dm_dev_iomap(dev, 0);
202
203 if (!serial->base)
204 {
205 err = -RT_EIO;
206
207 goto _free_res;
208 }
209
210 serial->irq = rt_dm_dev_get_irq(dev, 0);
211
212 if (serial->irq < 0)
213 {
214 err = serial->irq;
215
216 goto _free_res;
217 }
218
219 serial->clk = rt_clk_get_by_name(dev, "baudclk");
220 dw8250->pclk = rt_clk_get_by_name(dev, "apb_pclk");
221
222 if (!serial->clk)
223 {
224 if ((err = rt_dm_dev_prop_read_u32(dev, "clock-frequency", &serial->freq)))
225 {
226 goto _free_res;
227 }
228 }
229 else
230 {
231 if ((err = rt_clk_prepare_enable(serial->clk)))
232 {
233 goto _free_res;
234 }
235
236 serial->freq = rt_clk_get_rate(serial->clk);
237 }
238
239 if (!dw8250->pclk)
240 {
241 err = -RT_EIO;
242
243 goto _free_res;
244 }
245
246 if ((err = rt_clk_prepare_enable(dw8250->pclk)))
247 {
248 goto _free_res;
249 }
250
251 rt_dm_dev_prop_read_u32(dev, "reg-shift", &serial->regshift);
252
253 if (!rt_dm_dev_prop_read_u32(dev, "reg-io-width", &val) && val == 4)
254 {
255 serial->iotype = PORT_MMIO32;
256 serial->serial_in = &dw8250_serial_in32;
257 serial->serial_out = &dw8250_serial_out32;
258 }
259
260 dw8250->uart_16550_compatible = rt_dm_dev_prop_read_bool(dev, "snps,uart-16550-compatible");
261 dw8250->platform_data = (struct dw8250_platform_data *)pdev->id->data;
262
263 rt_dm_dev_bind_fwdata(&serial->parent.parent, pdev->parent.ofw_node, &serial->parent);
264
265 serial = &dw8250->parent;
266 serial->parent.ops = &serial8250_uart_ops;
267 serial->parent.config = config;
268 serial->handle_irq = &dw8250_isr;
269 serial->remove = &dw8250_remove;
270 serial->data = dw8250;
271
272 rt_spin_lock_init(&dw8250->spinlock);
273
274 if ((err = serial8250_setup(serial)))
275 {
276 goto _free_res;
277 }
278
279 return RT_EOK;
280
281 _free_res:
282 dw8250_free_resource(dw8250);
283
284 return err;
285 }
286
287 static const struct dw8250_platform_data dw8250_dw_apb =
288 {
289 .usr_reg = DW_UART_USR,
290 };
291
292 static const struct dw8250_platform_data dw8250_octeon_3860_data =
293 {
294 .usr_reg = OCTEON_UART_USR,
295 .quirks = DW_UART_QUIRK_OCTEON,
296 };
297
298 static const struct dw8250_platform_data dw8250_armada_38x_data =
299 {
300 .usr_reg = DW_UART_USR,
301 .quirks = DW_UART_QUIRK_ARMADA_38X,
302 };
303
304 static const struct dw8250_platform_data dw8250_renesas_rzn1_data =
305 {
306 .usr_reg = DW_UART_USR,
307 .cpr_val = 0x00012f32,
308 .quirks = DW_UART_QUIRK_IS_DMA_FC,
309 };
310
311 static const struct dw8250_platform_data dw8250_starfive_jh7100_data =
312 {
313 .usr_reg = DW_UART_USR,
314 .quirks = DW_UART_QUIRK_SKIP_SET_RATE,
315 };
316
317 static const struct rt_ofw_node_id dw8250_ofw_ids[] =
318 {
319 { .type = "ttyS", .compatible = "snps,dw-apb-uart", .data = &dw8250_dw_apb },
320 { .type = "ttyS", .compatible = "cavium,octeon-3860-uart", .data = &dw8250_octeon_3860_data },
321 { .type = "ttyS", .compatible = "marvell,armada-38x-uart", .data = &dw8250_armada_38x_data },
322 { .type = "ttyS", .compatible = "renesas,rzn1-uart", .data = &dw8250_renesas_rzn1_data },
323 { .type = "ttyS", .compatible = "starfive,jh7100-uart", .data = &dw8250_starfive_jh7100_data },
324 { /* sentinel */ }
325 };
326
327 static struct rt_platform_driver dw8250_driver =
328 {
329 .name = "dw-apb-uart",
330 .ids = dw8250_ofw_ids,
331
332 .probe = dw8250_probe,
333 };
334
dw8250_drv_register(void)335 static int dw8250_drv_register(void)
336 {
337 rt_platform_driver_register(&dw8250_driver);
338
339 return 0;
340 }
341 INIT_PLATFORM_EXPORT(dw8250_drv_register);
342