| /bsp/hpmicro/libraries/hpm_sdk/drivers/inc/ |
| A D | hpm_pllctl_drv.h | 58 static inline void pllctl_pll_unlock(PLLCTL_Type *ptr, uint8_t pll, uint32_t lock_mask) in pllctl_pll_unlock()
71 static inline void pllctl_pll_lock(PLLCTL_Type *ptr, uint8_t pll, uint32_t lock_mask) in pllctl_pll_lock()
84 static inline hpm_stat_t pllctl_pll_ss_disable(PLLCTL_Type *ptr, uint8_t pll) in pllctl_pll_ss_disable()
104 static inline hpm_stat_t pllctl_pll_powerdown(PLLCTL_Type *ptr, uint8_t pll) in pllctl_pll_powerdown()
124 static inline hpm_stat_t pllctl_pll_poweron(PLLCTL_Type *ptr, uint8_t pll) in pllctl_pll_poweron()
160 static inline hpm_stat_t pllctl_pll_ss_enable(PLLCTL_Type *ptr, uint8_t pll, in pllctl_pll_ss_enable()
195 static inline hpm_stat_t pllctl_set_postdiv1(PLLCTL_Type *ptr, uint8_t pll, uint8_t div) in pllctl_set_postdiv1()
263 static inline hpm_stat_t pllctl_set_frac(PLLCTL_Type *ptr, uint8_t pll, uint32_t frac) in pllctl_set_frac()
283 static inline hpm_stat_t pllctl_get_div(PLLCTL_Type *ptr, uint8_t pll, uint8_t div_index) in pllctl_get_div()
333 static inline bool pllctl_div_is_stable(PLLCTL_Type *ptr, uint8_t pll, uint8_t div_index) in pllctl_div_is_stable()
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| A D | hpm_pllctlv2_drv.h | 61 static inline bool pllctlv2_pll_is_stable(PLLCTLV2_Type *ptr, uint8_t pll) in pllctlv2_pll_is_stable()
72 static inline bool pllctlv2_pll_is_enabled(PLLCTLV2_Type *ptr, uint8_t pll) in pllctlv2_pll_is_enabled()
85 static inline void pllctlv2_select_reference_clock(PLLCTLV2_Type *ptr, uint8_t pll, uint8_t src) in pllctlv2_select_reference_clock()
104 static inline void pllctlv2_disable_spread_spectrum(PLLCTLV2_Type *ptr, uint8_t pll) in pllctlv2_disable_spread_spectrum()
115 static inline void pllctlv2_set_pll_lock_time(PLLCTLV2_Type *ptr, uint8_t pll, uint32_t xtal_cycles) in pllctlv2_set_pll_lock_time()
126 static inline void pllctlv2_set_pll_step_time(PLLCTLV2_Type *ptr, uint8_t pll, uint32_t xtal_cycles) in pllctlv2_set_pll_step_time()
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| /bsp/hpmicro/libraries/hpm_sdk/drivers/src/ |
| A D | hpm_pllctlv2_drv.c | 21 hpm_stat_t pllctlv2_set_pll_with_mfi_mfn(PLLCTLV2_Type *ptr, uint8_t pll, uint32_t mfi, uint32_t mf… in pllctlv2_set_pll_with_mfi_mfn()
39 hpm_stat_t pllctlv2_init_pll_with_freq(PLLCTLV2_Type *ptr, uint8_t pll, uint32_t freq_in_hz) in pllctlv2_init_pll_with_freq()
64 void pllctlv2_enable_spread_spectrum(PLLCTLV2_Type *ptr, uint8_t pll, uint32_t step, uint32_t stop) in pllctlv2_enable_spread_spectrum()
82 void pllctlv2_set_postdiv(PLLCTLV2_Type *ptr, uint8_t pll, uint8_t div_index, uint8_t div_value) in pllctlv2_set_postdiv()
91 uint32_t pllctlv2_get_pll_freq_in_hz(PLLCTLV2_Type *ptr, uint8_t pll) in pllctlv2_get_pll_freq_in_hz()
103 uint32_t pllctlv2_get_pll_postdiv_freq_in_hz(PLLCTLV2_Type *ptr, uint8_t pll, uint8_t div_index) in pllctlv2_get_pll_postdiv_freq_in_hz()
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| A D | hpm_pllctl_drv.c | 26 hpm_stat_t pllctl_set_pll_work_mode(PLLCTL_Type *ptr, uint8_t pll, bool int_mode) in pllctl_set_pll_work_mode()
50 hpm_stat_t pllctl_set_refdiv(PLLCTL_Type *ptr, uint8_t pll, uint8_t div) in pllctl_set_refdiv()
81 hpm_stat_t pllctl_init_int_pll_with_freq(PLLCTL_Type *ptr, uint8_t pll, in pllctl_init_int_pll_with_freq()
148 hpm_stat_t pllctl_init_frac_pll_with_freq(PLLCTL_Type *ptr, uint8_t pll, in pllctl_init_frac_pll_with_freq()
220 uint32_t pllctl_get_pll_freq_in_hz(PLLCTL_Type *ptr, uint8_t pll) in pllctl_get_pll_freq_in_hz()
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| /bsp/k230/drivers/interdrv/sysctl/sysctl_boot/ |
| A D | sysctl_boot.h | 32 typedef struct pll { struct
40 * pll related registers see TRM 2.2.4 Table 2-2-8 argument
45 pll_t pll[4]; member
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| /bsp/rockchip/rk3500/driver/clk/ |
| A D | clk-pll-rk3588.c | 303 static const struct rk_pll_rate_table *rk_get_pll_settings(struct rk_pll_clock *pll, rt_ubase_t rat… in rk_get_pll_settings()
329 static int rk3036_pll_set_rate(struct rk_pll_clock *pll, void *base, rt_ubase_t pll_id, rt_ubase_t … in rk3036_pll_set_rate()
378 static rt_ubase_t rk3036_pll_get_rate(struct rk_pll_clock *pll, void *base, rt_ubase_t pll_id) in rk3036_pll_get_rate()
424 static int rk3588_pll_set_rate(struct rk_pll_clock *pll, in rk3588_pll_set_rate()
546 static rt_ubase_t rk3588_pll_get_rate(struct rk_pll_clock *pll, in rk3588_pll_get_rate()
596 rt_ubase_t rk_pll_get_rate(struct rk_pll_clock *pll, in rk_pll_get_rate()
623 int rk_pll_set_rate(struct rk_pll_clock *pll, in rk_pll_set_rate()
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| A D | clk-pll-rk3568.c | 203 static const struct rk_pll_rate_table *rk_get_pll_settings(struct rk_pll_clock *pll, rt_ubase_t rat… in rk_get_pll_settings()
228 static int rk_pll_set_rate(struct rk_pll_clock *pll, void *base, rt_ubase_t drate) in rk_pll_set_rate()
283 static rt_ubase_t rk_pll_get_rate(struct rk_pll_clock *pll, void *base) in rk_pll_get_rate()
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| A D | clk-rk3568.c | 36 struct rk_pll pll[2]; member
49 struct rk_pll pll[6]; member
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| A D | clk-rk3588.c | 47 …struct rk3588_pll pll[18]; … member
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| /bsp/avr32/software_framework/drivers/pm/ |
| A D | pm.c | 61 unsigned long pll; member
393 unsigned int pll, in pm_pll_setup()
411 unsigned int pll, in pm_pll_set_option()
423 unsigned int pll) in pm_pll_get_option()
430 unsigned int pll) in pm_pll_enable()
437 unsigned int pll) in pm_pll_disable()
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| /bsp/at91/at91sam9260/platform/ |
| A D | system_clock.c | 112 static rt_uint32_t at91_pll_rate(struct clk *pll, rt_uint32_t freq, rt_uint32_t reg) in at91_pll_rate()
175 static rt_uint32_t at91_usb_rate(struct clk *pll, rt_uint32_t freq, rt_uint32_t reg) in at91_usb_rate()
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| /bsp/loongson/ls1bdev/drivers/ |
| A D | display_controller.c | 49 int pll,ctrl,div,div1,frac; in caclulate_freq() local
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| /bsp/loongson/ls2kdev/drivers/ |
| A D | clk.c | 45 volatile struct loongson_pll *pll = (void *)PLL_SYS_BASE; variable
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| /bsp/Infineon/psoc6-cy8ckit-062-WIFI-BT/libs/TARGET_CY8CKIT-062-WIFI-BT/config/GeneratedSource/ |
| A D | cycfg_system.c | 855 … for (uint32_t pll = CY_SRSS_NUM_PLL; pll > 0UL; --pll) /* PLL 1 is the first PLL. 0 is invalid. */ in init_cycfg_system() local
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| /bsp/Infineon/psoc6-cy8ckit-062-BLE/libs/TARGET_CY8CKIT-062-BLE/config/GeneratedSource/ |
| A D | cycfg_system.c | 855 … for (uint32_t pll = CY_SRSS_NUM_PLL; pll > 0UL; --pll) /* PLL 1 is the first PLL. 0 is invalid. */ in init_cycfg_system() local
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| /bsp/allwinner_tina/drivers/ |
| A D | drv_clock.c | 516 unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly; in mmc_set_clk() local
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| /bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/config/GeneratedSource/ |
| A D | cycfg_system.c | 868 … for (uint32_t pll = CY_SRSS_NUM_PLL; pll > 0UL; --pll) /* PLL 1 is the first PLL. 0 is invalid. */ in init_cycfg_system() local
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| /bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/config/GeneratedSource/ |
| A D | cycfg_system.c | 868 … for (uint32_t pll = CY_SRSS_NUM_PLL; pll > 0UL; --pll) /* PLL 1 is the first PLL. 0 is invalid. */ in init_cycfg_system() local
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| /bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/src/ |
| A D | bl808_glb.c | 5331 BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_PSram_CLK(uint8_t id, uint8_t enable, GLB_PSRAM_PLL_Type pll… in GLB_Set_PSram_CLK()
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