1 
2 /* Copyright (c) 2019-2025 Allwinner Technology Co., Ltd. ALL rights reserved.
3 
4  * Allwinner is a trademark of Allwinner Technology Co.,Ltd., registered in
5  * the the People's Republic of China and other countries.
6  * All Allwinner Technology Co.,Ltd. trademarks are used with permission.
7 
8  * DISCLAIMER
9  * THIRD PARTY LICENCES MAY BE REQUIRED TO IMPLEMENT THE SOLUTION/PRODUCT.
10  * IF YOU NEED TO INTEGRATE THIRD PARTY’S TECHNOLOGY (SONY, DTS, DOLBY, AVS OR MPEGLA, ETC.)
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14  * COVERED UNDER ANY REQUIRED THIRD PARTY LICENSE.
15  * YOU ARE SOLELY RESPONSIBLE FOR YOUR USAGE OF THIRD PARTY’S TECHNOLOGY.
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17 
18  * THIS SOFTWARE IS PROVIDED BY ALLWINNER"AS IS" AND TO THE MAXIMUM EXTENT
19  * PERMITTED BY LAW, ALLWINNER EXPRESSLY DISCLAIMS ALL WARRANTIES OF ANY KIND,
20  * WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING WITHOUT LIMITATION REGARDING
21  * THE TITLE, NON-INFRINGEMENT, ACCURACY, CONDITION, COMPLETENESS, PERFORMANCE
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31 
32  */
33 
34 #ifndef __SUNXI_HAL_PWM_H__
35 #define __SUNXI_HAL_PWM_H__
36 
37 #ifdef __cplusplus
38 extern "C" {
39 #endif
40 
41 #include <hal_clk.h>
42 #include <hal_reset.h>
43 #include <sunxi_hal_common.h>
44 // #include <init.h>
45 #include <pwm/platform_pwm.h>
46 
47 //#define CONFIG_DRIVERS_PWM_DEBUG
48 #ifdef CONFIG_DRIVERS_PWM_DEBUG
49 #define PWM_INFO(fmt, arg...) hal_log_info(fmt, ##arg)
50 #else
51 #define PWM_INFO(fmt, arg...) do {}while(0)
52 #endif
53 
54 #define PWM_ERR(fmt, arg...) hal_log_err(fmt, ##arg)
55 
56 #undef readl
57 #undef writel
58 #define readl(addr)     (*((volatile unsigned long  *)(addr)))
59 #define writel(v, addr) (*((volatile unsigned long  *)(addr)) = (unsigned long)(v))
60 
61 #define PRESCALE_MAX 256
62 
63 /*************
64  *SET_BITS set
65  * **********/
66 #define SETMASK(width, shift)   ((width?((-1U) >> (32-width)):0)  << (shift))
67 #define CLRMASK(width, shift)   (~(SETMASK(width, shift)))
68 #define GET_BITS(shift, width, reg)     \
69     (((reg) & SETMASK(width, shift)) >> (shift))
70 #define SET_BITS(shift, width, reg, val) \
71     (((reg) & CLRMASK(width, shift)) | (val << (shift)))
72 
73 /* define shift and width */
74 #define PWM_CLK_SRC_SHIFT 0x7
75 #define PWM_CLK_SRC_WIDTH 0x2
76 
77 #define PWM_DIV_M_SHIFT 0x0
78 #define PWM_DIV_M_WIDTH 0x4
79 
80 #define PWM_PRESCAL_SHIFT 0x0
81 #define PWM_PRESCAL_WIDTH 0x8
82 
83 #define PWM_ACT_CYCLES_SHIFT 0x0
84 #define PWM_ACT_CYCLES_WIDTH 0x10
85 
86 #define PWM_PERIOD_CYCLES_SHIFT 0x10
87 #define PWM_PERIOD_CYCLES_WIDTH 0x10
88 
89 /*****************************************************************************
90  * Enums
91  *****************************************************************************/
92 typedef unsigned long pwm_status_t;
93 
94 typedef enum
95 {
96     PWM_CLK_OSC,
97     PWM_CLK_APB,
98 } hal_pwm_clk_src;
99 
100 typedef enum
101 {
102     PWM_POLARITY_INVERSED = 0,
103     PWM_POLARITY_NORMAL = 1,
104 } hal_pwm_polarity;
105 
106 typedef enum
107 {
108     PWM_CONTROL = 0,
109     PWM_CHANNEL_INT = 1,
110     PWM_CHANNEL_UNINT = 2,
111 } hal_pwm_cmd_t;
112 
113 typedef struct pwm_config
114 {
115     uint32_t        duty_ns;
116     uint32_t        period_ns;
117     hal_pwm_polarity    polarity;
118 } pwm_config_t;
119 
120 typedef struct
121 {
122    hal_clk_type_t pwm_clk_type;
123    hal_clk_id_t pwm_bus_clk_id;
124    hal_clk_t pwm_bus_clk;
125    hal_reset_type_t pwm_reset_type;
126    hal_reset_id_t pwm_reset_id;
127    struct reset_control *pwm_reset;
128 
129     gpio_pin_t pin[8];
130     gpio_muxsel_t enable_muxsel[8];
131 } hal_pwm_t;
132 
133 pwm_status_t hal_pwm_init(void);
134 pwm_status_t hal_pwm_control(int channel, struct pwm_config *config_pwm);
135 void hal_pwm_enable_controller(uint32_t channel_in);
136 void hal_pwm_disable_controller(uint32_t channel_in);
137 pwm_status_t hal_pwm_deinit(void);
138 
139 pwm_status_t hal_pwm_resume(void);
140 pwm_status_t hal_pwm_suspend(void);
141 
142 #ifdef __cplusplus
143 }
144 #endif
145 
146 #endif /* __SUNXI_HAL_PWM_H__ */
147 
148 
149