1 /* THIS FILE HAS BEEN GENERATED, DO NOT MODIFY IT. */ 2 /* 3 * Copyright (C) 2019 ETH Zurich, University of Bologna 4 * and GreenWaves Technologies 5 * 6 * Licensed under the Apache License, Version 2.0 (the "License"); 7 * you may not use this file except in compliance with the License. 8 * You may obtain a copy of the License at 9 * 10 * http://www.apache.org/licenses/LICENSE-2.0 11 * 12 * Unless required by applicable law or agreed to in writing, software 13 * distributed under the License is distributed on an "AS IS" BASIS, 14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 * See the License for the specific language governing permissions and 16 * limitations under the License. 17 */ 18 19 20 #ifndef HAL_INCLUDE_HAL_PWM_CTRL_PERIPH_H_ 21 #define HAL_INCLUDE_HAL_PWM_CTRL_PERIPH_H_ 22 23 /* ---------------------------------------------------------------------------- 24 -- PWM_CTRL Peripheral Access Layer -- 25 ---------------------------------------------------------------------------- */ 26 27 /** PWM_CTRL_Type Register Layout Typedef */ 28 typedef struct 29 { 30 volatile uint32_t event_cfg; /**< ADV_TIMERS events configuration register. */ 31 volatile uint32_t cg; /**< ADV_TIMERS channels clock gating configuration register. */ 32 } pwm_ctrl_t; 33 34 /* ---------------------------------------------------------------------------- 35 -- PWM_CTRL Register Bitfield Access -- 36 ---------------------------------------------------------------------------- */ 37 38 /*! @name EVENT_CFG */ 39 /* ADV_TIMER output event 0 source configuration bitfiled: 40 - 4'h0: ADV_TIMER0 channel 0. 41 - 4'h1: ADV_TIMER0 channel 1. 42 - 4'h2: ADV_TIMER0 channel 2. 43 - 4'h3: ADV_TIMER0 channel 3. 44 - 4'h4: ADV_TIMER1 channel 0. 45 - 4'h5: ADV_TIMER1 channel 1. 46 - 4'h6: ADV_TIMER1 channel 2. 47 - 4'h7: ADV_TIMER1 channel 3. 48 - 4'h8: ADV_TIMER2 channel 0. 49 - 4'h9: ADV_TIMER2 channel 1. 50 - 4'hA: ADV_TIMER2 channel 2. 51 - 4'hB: ADV_TIMER2 channel 3. 52 - 4'hC: ADV_TIMER3 channel 0. 53 - 4'hD: ADV_TIMER3 channel 1. 54 - 4'hE: ADV_TIMER3 channel 2. 55 - 4'hF: ADV_TIMER3 channel 3. */ 56 #define PWM_CTRL_EVENT_CFG_SEL0_MASK (0xf) 57 #define PWM_CTRL_EVENT_CFG_SEL0_SHIFT (0) 58 #define PWM_CTRL_EVENT_CFG_SEL0(val) (((uint32_t)(((uint32_t)(val)) << PWM_CTRL_EVENT_CFG_SEL0_SHIFT)) & PWM_CTRL_EVENT_CFG_SEL0_MASK) 59 60 /* ADV_TIMER output event 1 source configuration bitfiled: 61 - 4'h0: ADV_TIMER0 channel 0. 62 - 4'h1: ADV_TIMER0 channel 1. 63 - 4'h2: ADV_TIMER0 channel 2. 64 - 4'h3: ADV_TIMER0 channel 3. 65 - 4'h4: ADV_TIMER1 channel 0. 66 - 4'h5: ADV_TIMER1 channel 1. 67 - 4'h6: ADV_TIMER1 channel 2. 68 - 4'h7: ADV_TIMER1 channel 3. 69 - 4'h8: ADV_TIMER2 channel 0. 70 - 4'h9: ADV_TIMER2 channel 1. 71 - 4'hA: ADV_TIMER2 channel 2. 72 - 4'hB: ADV_TIMER2 channel 3. 73 - 4'hC: ADV_TIMER3 channel 0. 74 - 4'hD: ADV_TIMER3 channel 1. 75 - 4'hE: ADV_TIMER3 channel 2. 76 - 4'hF: ADV_TIMER3 channel 3. */ 77 #define PWM_CTRL_EVENT_CFG_SEL1_MASK (0xf0) 78 #define PWM_CTRL_EVENT_CFG_SEL1_SHIFT (4) 79 #define PWM_CTRL_EVENT_CFG_SEL1(val) (((uint32_t)(((uint32_t)(val)) << PWM_CTRL_EVENT_CFG_SEL1_SHIFT)) & PWM_CTRL_EVENT_CFG_SEL1_MASK) 80 81 /* ADV_TIMER output event 2 source configuration bitfiled: 82 - 4'h0: ADV_TIMER0 channel 0. 83 - 4'h1: ADV_TIMER0 channel 1. 84 - 4'h2: ADV_TIMER0 channel 2. 85 - 4'h3: ADV_TIMER0 channel 3. 86 - 4'h4: ADV_TIMER1 channel 0. 87 - 4'h5: ADV_TIMER1 channel 1. 88 - 4'h6: ADV_TIMER1 channel 2. 89 - 4'h7: ADV_TIMER1 channel 3. 90 - 4'h8: ADV_TIMER2 channel 0. 91 - 4'h9: ADV_TIMER2 channel 1. 92 - 4'hA: ADV_TIMER2 channel 2. 93 - 4'hB: ADV_TIMER2 channel 3. 94 - 4'hC: ADV_TIMER3 channel 0. 95 - 4'hD: ADV_TIMER3 channel 1. 96 - 4'hE: ADV_TIMER3 channel 2. 97 - 4'hF: ADV_TIMER3 channel 3. */ 98 #define PWM_CTRL_EVENT_CFG_SEL2_MASK (0xf00) 99 #define PWM_CTRL_EVENT_CFG_SEL2_SHIFT (8) 100 #define PWM_CTRL_EVENT_CFG_SEL2(val) (((uint32_t)(((uint32_t)(val)) << PWM_CTRL_EVENT_CFG_SEL2_SHIFT)) & PWM_CTRL_EVENT_CFG_SEL2_MASK) 101 102 /* ADV_TIMER output event 3 source configuration bitfiled: 103 - 4'h0: ADV_TIMER0 channel 0. 104 - 4'h1: ADV_TIMER0 channel 1. 105 - 4'h2: ADV_TIMER0 channel 2. 106 - 4'h3: ADV_TIMER0 channel 3. 107 - 4'h4: ADV_TIMER1 channel 0. 108 - 4'h5: ADV_TIMER1 channel 1. 109 - 4'h6: ADV_TIMER1 channel 2. 110 - 4'h7: ADV_TIMER1 channel 3. 111 - 4'h8: ADV_TIMER2 channel 0. 112 - 4'h9: ADV_TIMER2 channel 1. 113 - 4'hA: ADV_TIMER2 channel 2. 114 - 4'hB: ADV_TIMER2 channel 3. 115 - 4'hC: ADV_TIMER3 channel 0. 116 - 4'hD: ADV_TIMER3 channel 1. 117 - 4'hE: ADV_TIMER3 channel 2. 118 - 4'hF: ADV_TIMER3 channel 3. */ 119 #define PWM_CTRL_EVENT_CFG_SEL3_MASK (0xf000) 120 #define PWM_CTRL_EVENT_CFG_SEL3_SHIFT (12) 121 #define PWM_CTRL_EVENT_CFG_SEL3(val) (((uint32_t)(((uint32_t)(val)) << PWM_CTRL_EVENT_CFG_SEL3_SHIFT)) & PWM_CTRL_EVENT_CFG_SEL3_MASK) 122 123 /* ADV_TIMER output event enable configuration bitfield. ENA[i]=1 enables output event i generation. */ 124 #define PWM_CTRL_EVENT_CFG_ENA_MASK (0xf0000) 125 #define PWM_CTRL_EVENT_CFG_ENA_SHIFT (16) 126 #define PWM_CTRL_EVENT_CFG_ENA(val) (((uint32_t)(((uint32_t)(val)) << PWM_CTRL_EVENT_CFG_ENA_SHIFT)) & PWM_CTRL_EVENT_CFG_ENA_MASK) 127 128 129 /*! @name CG */ 130 /* ADV_TIMER clock gating configuration bitfield. 131 - ENA[i]=0: clock gate ADV_TIMERi. 132 - ENA[i]=1: enable ADV_TIMERi. */ 133 #define PWM_CTRL_CG_ENA_MASK (0xffff) 134 #define PWM_CTRL_CG_ENA_SHIFT (0) 135 #define PWM_CTRL_CG_ENA(val) (((uint32_t)(((uint32_t)(val)) << PWM_CTRL_CG_ENA_SHIFT)) & PWM_CTRL_CG_ENA_MASK) 136 137 138 /*! @name EVENT_CFG */ 139 typedef union 140 { 141 struct 142 { 143 /* ADV_TIMER output event 0 source configuration bitfiled: 144 - 4'h0: ADV_TIMER0 channel 0. 145 - 4'h1: ADV_TIMER0 channel 1. 146 - 4'h2: ADV_TIMER0 channel 2. 147 - 4'h3: ADV_TIMER0 channel 3. 148 - 4'h4: ADV_TIMER1 channel 0. 149 - 4'h5: ADV_TIMER1 channel 1. 150 - 4'h6: ADV_TIMER1 channel 2. 151 - 4'h7: ADV_TIMER1 channel 3. 152 - 4'h8: ADV_TIMER2 channel 0. 153 - 4'h9: ADV_TIMER2 channel 1. 154 - 4'hA: ADV_TIMER2 channel 2. 155 - 4'hB: ADV_TIMER2 channel 3. 156 - 4'hC: ADV_TIMER3 channel 0. 157 - 4'hD: ADV_TIMER3 channel 1. 158 - 4'hE: ADV_TIMER3 channel 2. 159 - 4'hF: ADV_TIMER3 channel 3. */ 160 uint32_t sel0:4; 161 /* ADV_TIMER output event 1 source configuration bitfiled: 162 - 4'h0: ADV_TIMER0 channel 0. 163 - 4'h1: ADV_TIMER0 channel 1. 164 - 4'h2: ADV_TIMER0 channel 2. 165 - 4'h3: ADV_TIMER0 channel 3. 166 - 4'h4: ADV_TIMER1 channel 0. 167 - 4'h5: ADV_TIMER1 channel 1. 168 - 4'h6: ADV_TIMER1 channel 2. 169 - 4'h7: ADV_TIMER1 channel 3. 170 - 4'h8: ADV_TIMER2 channel 0. 171 - 4'h9: ADV_TIMER2 channel 1. 172 - 4'hA: ADV_TIMER2 channel 2. 173 - 4'hB: ADV_TIMER2 channel 3. 174 - 4'hC: ADV_TIMER3 channel 0. 175 - 4'hD: ADV_TIMER3 channel 1. 176 - 4'hE: ADV_TIMER3 channel 2. 177 - 4'hF: ADV_TIMER3 channel 3. */ 178 uint32_t sel1:4; 179 /* ADV_TIMER output event 2 source configuration bitfiled: 180 - 4'h0: ADV_TIMER0 channel 0. 181 - 4'h1: ADV_TIMER0 channel 1. 182 - 4'h2: ADV_TIMER0 channel 2. 183 - 4'h3: ADV_TIMER0 channel 3. 184 - 4'h4: ADV_TIMER1 channel 0. 185 - 4'h5: ADV_TIMER1 channel 1. 186 - 4'h6: ADV_TIMER1 channel 2. 187 - 4'h7: ADV_TIMER1 channel 3. 188 - 4'h8: ADV_TIMER2 channel 0. 189 - 4'h9: ADV_TIMER2 channel 1. 190 - 4'hA: ADV_TIMER2 channel 2. 191 - 4'hB: ADV_TIMER2 channel 3. 192 - 4'hC: ADV_TIMER3 channel 0. 193 - 4'hD: ADV_TIMER3 channel 1. 194 - 4'hE: ADV_TIMER3 channel 2. 195 - 4'hF: ADV_TIMER3 channel 3. */ 196 uint32_t sel2:4; 197 /* ADV_TIMER output event 3 source configuration bitfiled: 198 - 4'h0: ADV_TIMER0 channel 0. 199 - 4'h1: ADV_TIMER0 channel 1. 200 - 4'h2: ADV_TIMER0 channel 2. 201 - 4'h3: ADV_TIMER0 channel 3. 202 - 4'h4: ADV_TIMER1 channel 0. 203 - 4'h5: ADV_TIMER1 channel 1. 204 - 4'h6: ADV_TIMER1 channel 2. 205 - 4'h7: ADV_TIMER1 channel 3. 206 - 4'h8: ADV_TIMER2 channel 0. 207 - 4'h9: ADV_TIMER2 channel 1. 208 - 4'hA: ADV_TIMER2 channel 2. 209 - 4'hB: ADV_TIMER2 channel 3. 210 - 4'hC: ADV_TIMER3 channel 0. 211 - 4'hD: ADV_TIMER3 channel 1. 212 - 4'hE: ADV_TIMER3 channel 2. 213 - 4'hF: ADV_TIMER3 channel 3. */ 214 uint32_t sel3:4; 215 /* ADV_TIMER output event enable configuration bitfield. ENA[i]=1 enables output event i generation. */ 216 uint32_t ena:4; 217 } field; 218 uint32_t word; 219 } pwm_ctrl_event_cfg_t; 220 221 /*! @name CG */ 222 typedef union 223 { 224 struct 225 { 226 /* ADV_TIMER clock gating configuration bitfield. 227 - ENA[i]=0: clock gate ADV_TIMERi. 228 - ENA[i]=1: enable ADV_TIMERi. */ 229 uint32_t ena:16; 230 } field; 231 uint32_t word; 232 } pwm_ctrl_cg_t; 233 234 235 #endif /* HAL_INCLUDE_HAL_PWM_CTRL_PERIPH_H_ */ 236