1 /*
2 * Copyright (c) 2023-2024 HPMicro
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 *
6 */
7
8 #ifndef HPM_QEIV2_DRV_H
9 #define HPM_QEIV2_DRV_H
10
11 #include "hpm_common.h"
12 #include "hpm_soc_ip_feature.h"
13 #include "hpm_qeiv2_regs.h"
14 /**
15 * @brief QEIV2 driver APIs
16 * @defgroup qeiv2_interface QEIV2 driver APIs
17 * @ingroup io_interfaces
18 * @{
19 */
20 #define QEIV2_EVENT_WDOG_FLAG_MASK (1U << 31U) /**< watchdog flag */
21 #define QEIV2_EVENT_HOME_FLAG_MASK (1U << 30U) /**< home flag */
22 #define QEIV2_EVENT_POSITION_COMPARE_FLAG_MASK (1U << 29U) /**< postion compare match flag */
23 #define QEIV2_EVENT_Z_PHASE_FLAG_MASK (1U << 28U) /**< z input flag */
24 #define QEIV2_EVENT_Z_MISS_FLAG_MASK (1U << 27U) /**< z miss flag */
25 #define QEIV2_EVENT_WIDTH_TIME_FLAG_MASK (1U << 26U) /**< width time flag */
26 #define QEIV2_EVENT_POSITION2_COMPARE_FLAG_MASK (1U << 25U) /**< postion2 compare match flag */
27 #define QEIV2_EVENT_DIR_CHG_FLAG_MASK (1U << 24U) /**< direction change flag */
28 #define QEIV2_EVENT_CYCLE0_FLAG_MASK (1U << 23U) /**< cycle0 flag */
29 #define QEIV2_EVENT_CYCLE1_FLAG_MASK (1U << 22U) /**< cycle1 flag */
30 #define QEIV2_EVENT_PULSE0_FLAG_MASK (1U << 21U) /**< pulse0 flag */
31 #define QEIV2_EVENT_PULSE1_FLAG_MASK (1U << 20U) /**< pulse1 flag */
32 #define QEIV2_EVENT_HOME2_FLAG_MASK (1U << 19U) /**< home2 flag */
33 #define QEIV2_EVENT_FAULT_FLAG_MASK (1U << 18U) /**< fault flag */
34
35 /**
36 * @brief qeiv2 work mode
37 *
38 */
39 typedef enum qeiv2_work_mode {
40 qeiv2_work_mode_abz = 0, /**< Orthogonal decoder mode */
41 qeiv2_work_mode_pd = 1, /**< Directional (PD) mode */
42 qeiv2_work_mode_ud = 2, /**< Up and Down (UD) mode */
43 qeiv2_work_mode_uvw = 3, /**< UVW mode */
44 qeiv2_work_mode_single = 4, /**< Single-phase mode */
45 qeiv2_work_mode_sin = 5, /**< Single sinewave mode */
46 qeiv2_work_mode_sincos = 6, /**< Orthogonal sinewave mode */
47 } qeiv2_work_mode_t;
48
49 /**
50 * @brief spd and tmr read selection
51 *
52 */
53 typedef enum qeiv2_spd_tmr_content {
54 qeiv2_spd_tmr_as_spd_tm = 0, /**< spd and timer register as spd and time */
55 qeiv2_spd_tmr_as_pos_angle = 1, /**< spd and timer register as position and angle */
56 } qeiv2_spd_tmr_content_t;
57
58 /**
59 * @brief compare match rotate direction
60 *
61 */
62 typedef enum qeiv2_rotate_dir {
63 qeiv2_rotate_dir_forward = 0,
64 qeiv2_rotate_dir_reverse = 1,
65 } qeiv2_rotate_dir_t; /**< compare match rotate direction */
66
67 /**
68 * @brief compare match position direction
69 *
70 */
71 typedef enum qeiv2_position_dir {
72 qeiv2_pos_dir_decrease = 0,
73 qeiv2_pos_dir_increase = 1,
74 } qeiv2_position_dir_t; /**< compare match position direction */
75
76 /**
77 * @brief counting mode of Z-phase counter
78 *
79 */
80 typedef enum qeiv2_z_count_work_mode {
81 qeiv2_z_count_inc_on_z_input_assert = 0, /**< zcnt will increment or decrement when Z input assert */
82 qeiv2_z_count_inc_on_phase_count_max = 1, /**< zcnt will increment when phcnt upcount to phmax, decrement when phcnt downcount to 0 */
83 } qeiv2_z_count_work_mode_t;
84
85 /**
86 * @brief counter type
87 *
88 */
89 typedef enum qeiv2_counter_type {
90 qeiv2_counter_type_z = 0, /**< Z counter */
91 qeiv2_counter_type_phase = 1, /**< Phase counter */
92 qeiv2_counter_type_speed = 2, /**< Speed counter */
93 qeiv2_counter_type_timer = 3, /**< Timer counter */
94 } qeiv2_counter_type_t;
95
96 /**
97 * @brief filter mode
98 *
99 */
100 typedef enum qeiv2_filter_mode {
101 qeiv2_filter_mode_bypass = 0, /**< bypass */
102 qeiv2_filter_mode_burr = 4, /**< rapid change mode */
103 qeiv2_filter_mode_delay, /**< delay filter mode */
104 qeiv2_filter_mode_peak, /**< stable low mode */
105 qeiv2_filter_mode_valley, /**< stable high mode */
106 } qeiv2_filter_mode_t;
107
108 /**
109 * @brief filter type
110 *
111 */
112 typedef enum qeiv2_filter_phase {
113 qeiv2_filter_phase_a = 0, /**< filter phase a */
114 qeiv2_filter_phase_b, /**< filter phase b */
115 qeiv2_filter_phase_z, /**< filter phase z */
116 qeiv2_filter_phase_h, /**< filter phase h */
117 qeiv2_filter_phase_h2, /**< filter phase h2 */
118 qeiv2_filter_phase_f, /**< filter phase f */
119 } qeiv2_filter_phase_t; /**< qeiv2_filter_phase_t */
120
121 /**
122 * @brief uvw position option
123 *
124 */
125 typedef enum qeiv2_uvw_pos_opt {
126 qeiv2_uvw_pos_opt_current = 0, /**< output exact point position, MMC use this */
127 qeiv2_uvw_pos_opt_next, /**< output next area position, QEO use this */
128 } qeiv2_uvw_pos_opt_t;
129
130 typedef enum qeiv2_uvw_pos_sel {
131 qeiv2_uvw_pos_sel_low = 0,
132 qeiv2_uvw_pos_sel_high,
133 qeiv2_uvw_pos_sel_edge
134 } qeiv2_uvw_pos_sel_t; /**< qeiv2_uvw_pos_sel_t */
135
136 /**
137 * @brief qeiv2 uvw position selection
138 *
139 */
140 #define QEIV2_UVW_POS_OPT_CUR_SEL_LOW 0u
141 #define QEIV2_UVW_POS_OPT_CUR_SEL_HIGH 1u
142 #define QEIV2_UVW_POS_OPT_CUR_SEL_EDGE 2u
143 #define QEIV2_UVW_POS_OPT_NEX_SEL_LOW 0u
144 #define QEIV2_UVW_POS_OPT_NEX_SEL_HIGH 3u
145
146 typedef enum qeiv2_uvw_pos_idx {
147 qeiv2_uvw_pos0 = 0,
148 qeiv2_uvw_pos1,
149 qeiv2_uvw_pos2,
150 qeiv2_uvw_pos3,
151 qeiv2_uvw_pos4,
152 qeiv2_uvw_pos5,
153 } qeiv2_uvw_pos_idx_t; /**< qeiv2_uvw_pos_idx_t */
154
155 /**
156 * @brief phase counter compare match config structure
157 *
158 */
159 typedef struct {
160 uint32_t phcnt_cmp_value;
161 bool ignore_rotate_dir;
162 qeiv2_rotate_dir_t rotate_dir;
163 bool ignore_zcmp;
164 uint32_t zcmp_value;
165 } qeiv2_phcnt_cmp_match_config_t;
166
167 /**
168 * @brief position compare match config structure
169 *
170 */
171 typedef struct {
172 uint32_t pos_cmp_value;
173 bool ignore_pos_dir;
174 qeiv2_position_dir_t pos_dir;
175 } qeiv2_pos_cmp_match_config_t;
176
177 /**
178 * @brief uvw config structure
179 */
180 typedef struct {
181 qeiv2_uvw_pos_opt_t pos_opt;
182 qeiv2_uvw_pos_sel_t u_pos_sel[6];
183 qeiv2_uvw_pos_sel_t v_pos_sel[6];
184 qeiv2_uvw_pos_sel_t w_pos_sel[6];
185 uint32_t pos_cfg[6];
186 } qeiv2_uvw_config_t;
187
188 /**
189 * @brief adc config structure
190 */
191 typedef struct {
192 uint8_t adc_select;
193 uint8_t adc_channel;
194 int16_t param0;
195 int16_t param1;
196 uint32_t offset;
197 } qeiv2_adc_config_t;
198
199 #ifdef __cplusplus
200 extern "C" {
201 #endif
202
203 /**
204 * @brief load phcnt, zcnt, spdcnt and tmrcnt into their read registers
205 *
206 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
207 */
qeiv2_load_counter_to_read_registers(QEIV2_Type * qeiv2_x)208 static inline void qeiv2_load_counter_to_read_registers(QEIV2_Type *qeiv2_x)
209 {
210 qeiv2_x->CR |= QEIV2_CR_READ_MASK;
211 }
212
213 /**
214 * @brief config z phase counter increment and decrement mode
215 *
216 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
217 * @param[in] mode
218 * @arg 1 zcnt will increment when phcnt upcount to phmax, decrement when phcnt downcount to 0
219 * @arg 0 zcnt will increment or decrement when Z input assert
220 */
qeiv2_config_z_phase_counter_mode(QEIV2_Type * qeiv2_x,qeiv2_z_count_work_mode_t mode)221 static inline void qeiv2_config_z_phase_counter_mode(QEIV2_Type *qeiv2_x, qeiv2_z_count_work_mode_t mode)
222 {
223 qeiv2_x->CR = (qeiv2_x->CR & ~QEIV2_CR_ZCNTCFG_MASK) | QEIV2_CR_ZCNTCFG_SET(mode);
224 }
225
226 /**
227 * @brief config phase max value and phase param
228 *
229 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
230 * @param[in] phmax maximum phcnt number, phcnt will rollover to 0 when it upcount to phmax
231 */
qeiv2_config_phmax_phparam(QEIV2_Type * qeiv2_x,uint32_t phmax)232 static inline void qeiv2_config_phmax_phparam(QEIV2_Type *qeiv2_x, uint32_t phmax)
233 {
234 uint32_t tmp;
235
236 if (phmax > 0u) {
237 phmax--;
238 }
239 qeiv2_x->PHCFG = QEIV2_PHCFG_PHMAX_SET(phmax);
240 if (phmax == 0u) {
241 qeiv2_x->PHASE_PARAM = 0xFFFFFFFFu;
242 } else {
243 tmp = (0x80000000u / (phmax + 1u));
244 tmp <<= 1u;
245 qeiv2_x->PHASE_PARAM = QEIV2_PHASE_PARAM_PHASE_PARAM_SET(tmp);
246 }
247 }
248
249 /**
250 * @brief config phase calibration value trigged by z phase
251 *
252 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
253 * @param[in] enable phcnt will set to phidx when Z input assert
254 * @param[in] phidx phcnt reset value
255 * @param[in] mode qeiv2_work_mode_t
256 */
qeiv2_config_z_phase_calibration(QEIV2_Type * qeiv2_x,uint32_t phidx,bool enable,qeiv2_work_mode_t mode)257 static inline void qeiv2_config_z_phase_calibration(QEIV2_Type *qeiv2_x, uint32_t phidx, bool enable, qeiv2_work_mode_t mode)
258 {
259 uint32_t tmp = qeiv2_x->CR;
260 qeiv2_x->PHIDX = QEIV2_PHIDX_PHIDX_SET(phidx);
261 if (enable) {
262 tmp |= QEIV2_CR_PHCALIZ_MASK;
263 } else {
264 tmp &= ~QEIV2_CR_PHCALIZ_MASK;
265 }
266 if (enable && ((mode == qeiv2_work_mode_sin) || (mode == qeiv2_work_mode_sincos))) {
267 tmp |= QEIV2_CR_Z_ONLY_EN_MASK;
268 } else {
269 tmp &= ~QEIV2_CR_Z_ONLY_EN_MASK;
270 }
271 qeiv2_x->CR = tmp;
272 }
273
274 /**
275 * @brief pause counter when pause assert
276 *
277 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
278 * @param[in] counter_mask
279 * @arg QEIV2_CR_PAUSEPOS_MASK
280 * @arg QEIV2_CR_PAUSESPD_MASK
281 * @arg QEIV2_CR_PAUSEPH_MASK
282 * @arg QEIV2_CR_PAUSEZ_MASK
283 * @param[in] enable enable or disable pause
284 */
qeiv2_pause_counter(QEIV2_Type * qeiv2_x,uint32_t counter_mask,bool enable)285 static inline void qeiv2_pause_counter(QEIV2_Type *qeiv2_x, uint32_t counter_mask, bool enable)
286 {
287 if (enable) {
288 qeiv2_x->CR |= counter_mask;
289 } else {
290 qeiv2_x->CR &= ~counter_mask;
291 }
292 }
293
294 /**
295 * @brief pause pos counter when fault assert
296 *
297 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
298 * @param[in] enable enable or disable pause
299 */
qeiv2_pause_pos_counter_on_fault(QEIV2_Type * qeiv2_x,bool enable)300 static inline void qeiv2_pause_pos_counter_on_fault(QEIV2_Type *qeiv2_x, bool enable)
301 {
302 if (enable) {
303 qeiv2_x->CR |= QEIV2_CR_FAULTPOS_MASK;
304 } else {
305 qeiv2_x->CR &= ~QEIV2_CR_FAULTPOS_MASK;
306 }
307 }
308
309 /**
310 * @brief enable load phcnt, zcnt, spdcnt and tmrcnt into their snap registers
311 *
312 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
313 */
qeiv2_enable_snap(QEIV2_Type * qeiv2_x)314 static inline void qeiv2_enable_snap(QEIV2_Type *qeiv2_x)
315 {
316 qeiv2_x->CR |= QEIV2_CR_SNAPEN_MASK;
317 }
318
319 /**
320 * @brief disable snap
321 *
322 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
323 */
qeiv2_disable_snap(QEIV2_Type * qeiv2_x)324 static inline void qeiv2_disable_snap(QEIV2_Type *qeiv2_x)
325 {
326 qeiv2_x->CR &= ~QEIV2_CR_SNAPEN_MASK;
327 }
328
329 /**
330 * @brief reset zcnt, spdcnt and tmrcnt to 0, reset phcnt to phidx.
331 *
332 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
333 */
qeiv2_reset_counter(QEIV2_Type * qeiv2_x)334 static inline void qeiv2_reset_counter(QEIV2_Type *qeiv2_x)
335 {
336 qeiv2_x->CR |= QEIV2_CR_RSTCNT_MASK;
337 }
338
339 /**
340 * @brief release counter.
341 *
342 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
343 */
qeiv2_release_counter(QEIV2_Type * qeiv2_x)344 static inline void qeiv2_release_counter(QEIV2_Type *qeiv2_x)
345 {
346 qeiv2_x->CR &= ~QEIV2_CR_RSTCNT_MASK;
347 }
348
349 /**
350 * @brief select spd and tmr register content
351 *
352 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
353 * @param[in] content @ref qeiv2_spd_tmr_content_t
354 */
qeiv2_select_spd_tmr_register_content(QEIV2_Type * qeiv2_x,qeiv2_spd_tmr_content_t content)355 static inline void qeiv2_select_spd_tmr_register_content(QEIV2_Type *qeiv2_x, qeiv2_spd_tmr_content_t content)
356 {
357 qeiv2_x->CR = (qeiv2_x->CR & ~QEIV2_CR_RD_SEL_MASK) | QEIV2_CR_RD_SEL_SET(content);
358 }
359
360 /**
361 * @brief check spd and tmr register content as pos and angle
362 *
363 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
364 * @return true if spd and timer register as pos and angle register
365 */
qeiv2_check_spd_tmr_as_pos_angle(QEIV2_Type * qeiv2_x)366 static inline bool qeiv2_check_spd_tmr_as_pos_angle(QEIV2_Type *qeiv2_x)
367 {
368 return ((qeiv2_x->CR & QEIV2_CR_RD_SEL_MASK) != 0) ? true : false;
369 }
370
371 /**
372 * @brief set qeiv2 work mode
373 *
374 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
375 * @param[in] mode @ref qeiv2_work_mode_t
376 */
qeiv2_set_work_mode(QEIV2_Type * qeiv2_x,qeiv2_work_mode_t mode)377 static inline void qeiv2_set_work_mode(QEIV2_Type *qeiv2_x, qeiv2_work_mode_t mode)
378 {
379 qeiv2_x->CR = (qeiv2_x->CR & ~QEIV2_CR_ENCTYP_MASK) | QEIV2_CR_ENCTYP_SET(mode);
380 }
381
382 /**
383 * @brief config watchdog
384 *
385 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
386 * @param[in] timeout watchdog timeout time
387 * @param[in] clr_phcnt the phase_cnt time passed, then clear wdog counter
388 * @param[in] enable
389 * @arg 1 - enable watchdog
390 * @arg 0 - disable watchdog
391 */
qeiv2_config_wdog(QEIV2_Type * qeiv2_x,uint32_t timeout,uint8_t clr_phcnt,bool enable)392 static inline void qeiv2_config_wdog(QEIV2_Type *qeiv2_x, uint32_t timeout, uint8_t clr_phcnt, bool enable)
393 {
394 uint32_t tmp;
395 tmp = QEIV2_WDGCFG_WDGTO_SET(timeout) | QEIV2_WDGCFG_WDOG_CFG_SET(clr_phcnt);
396 if (enable) {
397 tmp |= QEIV2_WDGCFG_WDGEN_MASK;
398 } else {
399 tmp &= ~QEIV2_WDGCFG_WDGEN_MASK;
400 }
401 qeiv2_x->WDGCFG = tmp;
402 }
403
404 /**
405 * @brief enable trig out trigger event
406 *
407 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
408 * @param[in] event_mask
409 * @arg @ref QEIV2_EVENT_WDOG_FLAG_MASK
410 * @arg @ref QEIV2_EVENT_HOME_FLAG_MASK
411 * @arg @ref QEIV2_EVENT_POSITION_COMPARE_FLAG_MASK
412 * @arg @ref QEIV2_EVENT_Z_PHASE_FLAG_MASK
413 * @arg @ref QEIV2_EVENT_Z_MISS_FLAG_MASK
414 * @arg @ref QEIV2_EVENT_WIDTH_TIME_FLAG_MASK
415 * @arg @ref QEIV2_EVENT_POSITION2_COMPARE_FLAG_MASK
416 * @arg @ref QEIV2_EVENT_DIR_CHG_FLAG_MASK
417 * @arg @ref QEIV2_EVENT_CYCLE0_FLAG_MASK
418 * @arg @ref QEIV2_EVENT_CYCLE1_FLAG_MASK
419 * @arg @ref QEIV2_EVENT_PULSE0_FLAG_MASK
420 * @arg @ref QEIV2_EVENT_PULSE1_FLAG_MASK
421 * @arg @ref QEIV2_EVENT_HOME2_FLAG_MASK
422 * @arg @ref QEIV2_EVENT_FAULT_FLAG_MASK
423 */
qeiv2_enable_trig_out_trigger_event(QEIV2_Type * qeiv2_x,uint32_t event_mask)424 static inline void qeiv2_enable_trig_out_trigger_event(QEIV2_Type *qeiv2_x, uint32_t event_mask)
425 {
426 qeiv2_x->TRGOEN |= event_mask;
427 }
428
429 /**
430 * @brief disable trig out trigger event
431 *
432 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
433 * @param[in] event_mask
434 * @arg @ref QEIV2_EVENT_WDOG_FLAG_MASK
435 * @arg @ref QEIV2_EVENT_HOME_FLAG_MASK
436 * @arg @ref QEIV2_EVENT_POSITION_COMPARE_FLAG_MASK
437 * @arg @ref QEIV2_EVENT_Z_PHASE_FLAG_MASK
438 * @arg @ref QEIV2_EVENT_Z_MISS_FLAG_MASK
439 * @arg @ref QEIV2_EVENT_WIDTH_TIME_FLAG_MASK
440 * @arg @ref QEIV2_EVENT_POSITION2_COMPARE_FLAG_MASK
441 * @arg @ref QEIV2_EVENT_DIR_CHG_FLAG_MASK
442 * @arg @ref QEIV2_EVENT_CYCLE0_FLAG_MASK
443 * @arg @ref QEIV2_EVENT_CYCLE1_FLAG_MASK
444 * @arg @ref QEIV2_EVENT_PULSE0_FLAG_MASK
445 * @arg @ref QEIV2_EVENT_PULSE1_FLAG_MASK
446 * @arg @ref QEIV2_EVENT_HOME2_FLAG_MASK
447 * @arg @ref QEIV2_EVENT_FAULT_FLAG_MASK
448 */
qeiv2_disable_trig_out_trigger_event(QEIV2_Type * qeiv2_x,uint32_t event_mask)449 static inline void qeiv2_disable_trig_out_trigger_event(QEIV2_Type *qeiv2_x, uint32_t event_mask)
450 {
451 qeiv2_x->TRGOEN &= ~event_mask;
452 }
453
454 /**
455 * @brief enable load read trigger event
456 *
457 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
458 * @param[in] event_mask
459 * @arg @ref QEIV2_EVENT_WDOG_FLAG_MASK
460 * @arg @ref QEIV2_EVENT_HOME_FLAG_MASK
461 * @arg @ref QEIV2_EVENT_POSITION_COMPARE_FLAG_MASK
462 * @arg @ref QEIV2_EVENT_Z_PHASE_FLAG_MASK
463 * @arg @ref QEIV2_EVENT_Z_MISS_FLAG_MASK
464 * @arg @ref QEIV2_EVENT_WIDTH_TIME_FLAG_MASK
465 * @arg @ref QEIV2_EVENT_POSITION2_COMPARE_FLAG_MASK
466 * @arg @ref QEIV2_EVENT_DIR_CHG_FLAG_MASK
467 * @arg @ref QEIV2_EVENT_CYCLE0_FLAG_MASK
468 * @arg @ref QEIV2_EVENT_CYCLE1_FLAG_MASK
469 * @arg @ref QEIV2_EVENT_PULSE0_FLAG_MASK
470 * @arg @ref QEIV2_EVENT_PULSE1_FLAG_MASK
471 * @arg @ref QEIV2_EVENT_HOME2_FLAG_MASK
472 * @arg @ref QEIV2_EVENT_FAULT_FLAG_MASK
473 */
qeiv2_enable_load_read_trigger_event(QEIV2_Type * qeiv2_x,uint32_t event_mask)474 static inline void qeiv2_enable_load_read_trigger_event(QEIV2_Type *qeiv2_x, uint32_t event_mask)
475 {
476 qeiv2_x->READEN |= event_mask;
477 }
478
479 /**
480 * @brief disable load read trigger event
481 *
482 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
483 * @param[in] event_mask
484 * @arg @ref QEIV2_EVENT_WDOG_FLAG_MASK
485 * @arg @ref QEIV2_EVENT_HOME_FLAG_MASK
486 * @arg @ref QEIV2_EVENT_POSITION_COMPARE_FLAG_MASK
487 * @arg @ref QEIV2_EVENT_Z_PHASE_FLAG_MASK
488 * @arg @ref QEIV2_EVENT_Z_MISS_FLAG_MASK
489 * @arg @ref QEIV2_EVENT_WIDTH_TIME_FLAG_MASK
490 * @arg @ref QEIV2_EVENT_POSITION2_COMPARE_FLAG_MASK
491 * @arg @ref QEIV2_EVENT_DIR_CHG_FLAG_MASK
492 * @arg @ref QEIV2_EVENT_CYCLE0_FLAG_MASK
493 * @arg @ref QEIV2_EVENT_CYCLE1_FLAG_MASK
494 * @arg @ref QEIV2_EVENT_PULSE0_FLAG_MASK
495 * @arg @ref QEIV2_EVENT_PULSE1_FLAG_MASK
496 * @arg @ref QEIV2_EVENT_HOME2_FLAG_MASK
497 * @arg @ref QEIV2_EVENT_FAULT_FLAG_MASK
498 */
qeiv2_disable_load_read_trigger_event(QEIV2_Type * qeiv2_x,uint32_t event_mask)499 static inline void qeiv2_disable_load_read_trigger_event(QEIV2_Type *qeiv2_x, uint32_t event_mask)
500 {
501 qeiv2_x->READEN &= ~event_mask;
502 }
503
504 /**
505 * @brief enable dma request
506 *
507 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
508 * @param[in] mask
509 * @arg @ref QEIV2_EVENT_WDOG_FLAG_MASK
510 * @arg @ref QEIV2_EVENT_HOME_FLAG_MASK
511 * @arg @ref QEIV2_EVENT_POSITION_COMPARE_FLAG_MASK
512 * @arg @ref QEIV2_EVENT_Z_PHASE_FLAG_MASK
513 * @arg @ref QEIV2_EVENT_Z_MISS_FLAG_MASK
514 * @arg @ref QEIV2_EVENT_WIDTH_TIME_FLAG_MASK
515 * @arg @ref QEIV2_EVENT_POSITION2_COMPARE_FLAG_MASK
516 * @arg @ref QEIV2_EVENT_DIR_CHG_FLAG_MASK
517 * @arg @ref QEIV2_EVENT_CYCLE0_FLAG_MASK
518 * @arg @ref QEIV2_EVENT_CYCLE1_FLAG_MASK
519 * @arg @ref QEIV2_EVENT_PULSE0_FLAG_MASK
520 * @arg @ref QEIV2_EVENT_PULSE1_FLAG_MASK
521 * @arg @ref QEIV2_EVENT_HOME2_FLAG_MASK
522 * @arg @ref QEIV2_EVENT_FAULT_FLAG_MASK
523 */
qeiv2_enable_dma_request(QEIV2_Type * qeiv2_x,uint32_t mask)524 static inline void qeiv2_enable_dma_request(QEIV2_Type *qeiv2_x, uint32_t mask)
525 {
526 qeiv2_x->DMAEN |= mask;
527 }
528
529 /**
530 * @brief disable qeiv2 dma
531 *
532 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
533 * @param[in] mask
534 * @arg @ref QEIV2_EVENT_WDOG_FLAG_MASK
535 * @arg @ref QEIV2_EVENT_HOME_FLAG_MASK
536 * @arg @ref QEIV2_EVENT_POSITION_COMPARE_FLAG_MASK
537 * @arg @ref QEIV2_EVENT_Z_PHASE_FLAG_MASK
538 * @arg @ref QEIV2_EVENT_Z_MISS_FLAG_MASK
539 * @arg @ref QEIV2_EVENT_WIDTH_TIME_FLAG_MASK
540 * @arg @ref QEIV2_EVENT_POSITION2_COMPARE_FLAG_MASK
541 * @arg @ref QEIV2_EVENT_DIR_CHG_FLAG_MASK
542 * @arg @ref QEIV2_EVENT_CYCLE0_FLAG_MASK
543 * @arg @ref QEIV2_EVENT_CYCLE1_FLAG_MASK
544 * @arg @ref QEIV2_EVENT_PULSE0_FLAG_MASK
545 * @arg @ref QEIV2_EVENT_PULSE1_FLAG_MASK
546 * @arg @ref QEIV2_EVENT_HOME2_FLAG_MASK
547 * @arg @ref QEIV2_EVENT_FAULT_FLAG_MASK
548 */
qeiv2_disable_dma_request(QEIV2_Type * qeiv2_x,uint32_t mask)549 static inline void qeiv2_disable_dma_request(QEIV2_Type *qeiv2_x, uint32_t mask)
550 {
551 qeiv2_x->DMAEN &= ~mask;
552 }
553
554 /**
555 * @brief clear qeiv2 status register
556 *
557 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
558 * @param[in] mask
559 * @arg @ref QEIV2_EVENT_WDOG_FLAG_MASK
560 * @arg @ref QEIV2_EVENT_HOME_FLAG_MASK
561 * @arg @ref QEIV2_EVENT_POSITION_COMPARE_FLAG_MASK
562 * @arg @ref QEIV2_EVENT_Z_PHASE_FLAG_MASK
563 * @arg @ref QEIV2_EVENT_Z_MISS_FLAG_MASK
564 * @arg @ref QEIV2_EVENT_WIDTH_TIME_FLAG_MASK
565 * @arg @ref QEIV2_EVENT_POSITION2_COMPARE_FLAG_MASK
566 * @arg @ref QEIV2_EVENT_DIR_CHG_FLAG_MASK
567 * @arg @ref QEIV2_EVENT_CYCLE0_FLAG_MASK
568 * @arg @ref QEIV2_EVENT_CYCLE1_FLAG_MASK
569 * @arg @ref QEIV2_EVENT_PULSE0_FLAG_MASK
570 * @arg @ref QEIV2_EVENT_PULSE1_FLAG_MASK
571 * @arg @ref QEIV2_EVENT_HOME2_FLAG_MASK
572 * @arg @ref QEIV2_EVENT_FAULT_FLAG_MASK
573 */
qeiv2_clear_status(QEIV2_Type * qeiv2_x,uint32_t mask)574 static inline void qeiv2_clear_status(QEIV2_Type *qeiv2_x, uint32_t mask)
575 {
576 qeiv2_x->SR = mask;
577 }
578
579 /**
580 * @brief get qeiv2 status
581 *
582 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
583 * @retval qeiv2 status:
584 * @arg @ref QEIV2_EVENT_WDOG_FLAG_MASK
585 * @arg @ref QEIV2_EVENT_HOME_FLAG_MASK
586 * @arg @ref QEIV2_EVENT_POSITION_COMPARE_FLAG_MASK
587 * @arg @ref QEIV2_EVENT_Z_PHASE_FLAG_MASK
588 * @arg @ref QEIV2_EVENT_Z_MISS_FLAG_MASK
589 * @arg @ref QEIV2_EVENT_WIDTH_TIME_FLAG_MASK
590 * @arg @ref QEIV2_EVENT_POSITION2_COMPARE_FLAG_MASK
591 * @arg @ref QEIV2_EVENT_DIR_CHG_FLAG_MASK
592 * @arg @ref QEIV2_EVENT_CYCLE0_FLAG_MASK
593 * @arg @ref QEIV2_EVENT_CYCLE1_FLAG_MASK
594 * @arg @ref QEIV2_EVENT_PULSE0_FLAG_MASK
595 * @arg @ref QEIV2_EVENT_PULSE1_FLAG_MASK
596 * @arg @ref QEIV2_EVENT_HOME2_FLAG_MASK
597 * @arg @ref QEIV2_EVENT_FAULT_FLAG_MASK
598 */
qeiv2_get_status(QEIV2_Type * qeiv2_x)599 static inline uint32_t qeiv2_get_status(QEIV2_Type *qeiv2_x)
600 {
601 return qeiv2_x->SR;
602 }
603
604 /**
605 * @brief get qeiv2 bit status
606 *
607 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
608 * @param[in] mask
609 * @arg @ref QEIV2_EVENT_WDOG_FLAG_MASK
610 * @arg @ref QEIV2_EVENT_HOME_FLAG_MASK
611 * @arg @ref QEIV2_EVENT_POSITION_COMPARE_FLAG_MASK
612 * @arg @ref QEIV2_EVENT_Z_PHASE_FLAG_MASK
613 * @arg @ref QEIV2_EVENT_Z_MISS_FLAG_MASK
614 * @arg @ref QEIV2_EVENT_WIDTH_TIME_FLAG_MASK
615 * @arg @ref QEIV2_EVENT_POSITION2_COMPARE_FLAG_MASK
616 * @arg @ref QEIV2_EVENT_DIR_CHG_FLAG_MASK
617 * @arg @ref QEIV2_EVENT_CYCLE0_FLAG_MASK
618 * @arg @ref QEIV2_EVENT_CYCLE1_FLAG_MASK
619 * @arg @ref QEIV2_EVENT_PULSE0_FLAG_MASK
620 * @arg @ref QEIV2_EVENT_PULSE1_FLAG_MASK
621 * @arg @ref QEIV2_EVENT_HOME2_FLAG_MASK
622 * @arg @ref QEIV2_EVENT_FAULT_FLAG_MASK
623 * @retval true or false
624 */
qeiv2_get_bit_status(QEIV2_Type * qeiv2_x,uint32_t mask)625 static inline bool qeiv2_get_bit_status(QEIV2_Type *qeiv2_x, uint32_t mask)
626 {
627 return ((qeiv2_x->SR & mask) == mask) ? true : false;
628 }
629
630 /**
631 * @brief enable qeiv2 irq
632 *
633 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
634 * @param[in] mask
635 * @arg @ref QEIV2_EVENT_WDOG_FLAG_MASK
636 * @arg @ref QEIV2_EVENT_HOME_FLAG_MASK
637 * @arg @ref QEIV2_EVENT_POSITION_COMPARE_FLAG_MASK
638 * @arg @ref QEIV2_EVENT_Z_PHASE_FLAG_MASK
639 * @arg @ref QEIV2_EVENT_Z_MISS_FLAG_MASK
640 * @arg @ref QEIV2_EVENT_WIDTH_TIME_FLAG_MASK
641 * @arg @ref QEIV2_EVENT_POSITION2_COMPARE_FLAG_MASK
642 * @arg @ref QEIV2_EVENT_DIR_CHG_FLAG_MASK
643 * @arg @ref QEIV2_EVENT_CYCLE0_FLAG_MASK
644 * @arg @ref QEIV2_EVENT_CYCLE1_FLAG_MASK
645 * @arg @ref QEIV2_EVENT_PULSE0_FLAG_MASK
646 * @arg @ref QEIV2_EVENT_PULSE1_FLAG_MASK
647 * @arg @ref QEIV2_EVENT_HOME2_FLAG_MASK
648 * @arg @ref QEIV2_EVENT_FAULT_FLAG_MASK
649 */
qeiv2_enable_irq(QEIV2_Type * qeiv2_x,uint32_t mask)650 static inline void qeiv2_enable_irq(QEIV2_Type *qeiv2_x, uint32_t mask)
651 {
652 qeiv2_x->IRQEN |= mask;
653 }
654
655 /**
656 * @brief disable qeiv2 irq
657 *
658 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
659 * @param[in] mask
660 * @arg @ref QEIV2_EVENT_WDOG_FLAG_MASK
661 * @arg @ref QEIV2_EVENT_HOME_FLAG_MASK
662 * @arg @ref QEIV2_EVENT_POSITION_COMPARE_FLAG_MASK
663 * @arg @ref QEIV2_EVENT_Z_PHASE_FLAG_MASK
664 * @arg @ref QEIV2_EVENT_Z_MISS_FLAG_MASK
665 * @arg @ref QEIV2_EVENT_WIDTH_TIME_FLAG_MASK
666 * @arg @ref QEIV2_EVENT_POSITION2_COMPARE_FLAG_MASK
667 * @arg @ref QEIV2_EVENT_DIR_CHG_FLAG_MASK
668 * @arg @ref QEIV2_EVENT_CYCLE0_FLAG_MASK
669 * @arg @ref QEIV2_EVENT_CYCLE1_FLAG_MASK
670 * @arg @ref QEIV2_EVENT_PULSE0_FLAG_MASK
671 * @arg @ref QEIV2_EVENT_PULSE1_FLAG_MASK
672 * @arg @ref QEIV2_EVENT_HOME2_FLAG_MASK
673 * @arg @ref QEIV2_EVENT_FAULT_FLAG_MASK
674 */
qeiv2_disable_irq(QEIV2_Type * qeiv2_x,uint32_t mask)675 static inline void qeiv2_disable_irq(QEIV2_Type *qeiv2_x, uint32_t mask)
676 {
677 qeiv2_x->IRQEN &= ~mask;
678 }
679
680 /**
681 * @brief get current counter value
682 *
683 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
684 * @param[in] type @ref qeiv2_counter_type_t
685 * @retval counter value
686 */
qeiv2_get_current_count(QEIV2_Type * qeiv2_x,qeiv2_counter_type_t type)687 static inline uint32_t qeiv2_get_current_count(QEIV2_Type *qeiv2_x, qeiv2_counter_type_t type)
688 {
689 return *(&qeiv2_x->COUNT[QEIV2_COUNT_CURRENT].Z + type);
690 }
691
692 /**
693 * @brief get current phcnt value
694 *
695 * @param qeiv2_x QEI base address, HPM_QEIx(x=0...n)
696 * @return phcnt value
697 */
qeiv2_get_current_phase_phcnt(QEIV2_Type * qeiv2_x)698 static inline uint32_t qeiv2_get_current_phase_phcnt(QEIV2_Type *qeiv2_x)
699 {
700 return QEIV2_COUNT_PH_PHCNT_GET(qeiv2_get_current_count(qeiv2_x, qeiv2_counter_type_phase));
701 }
702
703 /**
704 * @brief get current a phase level
705 *
706 * @param qeiv2_x QEI base address, HPM_QEIx(x=0...n)
707 * @return a phase level
708 */
qeiv2_get_current_phase_a_level(QEIV2_Type * qeiv2_x)709 static inline bool qeiv2_get_current_phase_a_level(QEIV2_Type *qeiv2_x)
710 {
711 return QEIV2_COUNT_PH_ASTAT_GET(qeiv2_get_current_count(qeiv2_x, qeiv2_counter_type_phase));
712 }
713
714 /**
715 * @brief get current b phase level
716 *
717 * @param qeiv2_x QEI base address, HPM_QEIx(x=0...n)
718 * @return b phase level
719 */
qeiv2_get_current_phase_b_level(QEIV2_Type * qeiv2_x)720 static inline bool qeiv2_get_current_phase_b_level(QEIV2_Type *qeiv2_x)
721 {
722 return QEIV2_COUNT_PH_BSTAT_GET(qeiv2_get_current_count(qeiv2_x, qeiv2_counter_type_phase));
723 }
724
725 /**
726 * @brief get current phase dir
727 *
728 * @param qeiv2_x QEI base address, HPM_QEIx(x=0...n)
729 * @return dir
730 */
qeiv2_get_current_phase_dir(QEIV2_Type * qeiv2_x)731 static inline bool qeiv2_get_current_phase_dir(QEIV2_Type *qeiv2_x)
732 {
733 return QEIV2_COUNT_PH_DIR_GET(qeiv2_get_current_count(qeiv2_x, qeiv2_counter_type_phase));
734 }
735
736
737 /**
738 * @brief get read event count value
739 *
740 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
741 * @param[in] type @ref qeiv2_counter_type_t
742 * @retval counter value
743 */
qeiv2_get_count_on_read_event(QEIV2_Type * qeiv2_x,qeiv2_counter_type_t type)744 static inline uint32_t qeiv2_get_count_on_read_event(QEIV2_Type *qeiv2_x, qeiv2_counter_type_t type)
745 {
746 return *(&(qeiv2_x->COUNT[QEIV2_COUNT_READ].Z) + type);
747 }
748
749 /**
750 * @brief read the value of each phase snapshot 0 counter
751 *
752 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
753 * @param[in] type @ref qeiv2_counter_type_t
754 * @retval counter value
755 */
qeiv2_get_count_on_snap0_event(QEIV2_Type * qeiv2_x,qeiv2_counter_type_t type)756 static inline uint32_t qeiv2_get_count_on_snap0_event(QEIV2_Type *qeiv2_x, qeiv2_counter_type_t type)
757 {
758 return *(&qeiv2_x->COUNT[QEIV2_COUNT_SNAP0].Z + type);
759 }
760
761 /**
762 * @brief read the value of each phase snapshot 1 counter
763 *
764 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
765 * @param[in] type @ref qeiv2_counter_type_t
766 * @retval counter value
767 */
qeiv2_get_count_on_snap1_event(QEIV2_Type * qeiv2_x,qeiv2_counter_type_t type)768 static inline uint32_t qeiv2_get_count_on_snap1_event(QEIV2_Type *qeiv2_x, qeiv2_counter_type_t type)
769 {
770 return *(&qeiv2_x->COUNT[QEIV2_COUNT_SNAP1].Z + type);
771 }
772
773 /**
774 * @brief set zcnt compare value
775 *
776 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
777 * @param[in] cmp zcnt compare value
778 */
qeiv2_set_z_cmp_value(QEIV2_Type * qeiv2_x,uint32_t cmp)779 static inline void qeiv2_set_z_cmp_value(QEIV2_Type *qeiv2_x, uint32_t cmp)
780 {
781 qeiv2_x->ZCMP = QEIV2_ZCMP_ZCMP_SET(cmp);
782 }
783
784 /**
785 * @brief set phcnt compare value
786 *
787 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
788 * @param[in] cmp phcnt compare value
789 */
qeiv2_set_phcnt_cmp_value(QEIV2_Type * qeiv2_x,uint32_t cmp)790 static inline void qeiv2_set_phcnt_cmp_value(QEIV2_Type *qeiv2_x, uint32_t cmp)
791 {
792 qeiv2_x->PHCMP = QEIV2_PHCMP_PHCMP_SET(cmp);
793 }
794
795 /**
796 * @brief set spdcnt or position compare value. It's selected by CR register rd_sel bit.
797 *
798 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
799 * @param[in] cmp spdcnt or position compare value
800 * when set @ref qeiv2_spd_tmr_as_spd_tm, this is spdcmp value. (ABZ encoder)
801 * when set @ref qeiv2_spd_tmr_as_pos_angle, this is poscmp value. (sin or sincos encoder)
802 */
qeiv2_set_spd_pos_cmp_value(QEIV2_Type * qeiv2_x,uint32_t cmp)803 static inline void qeiv2_set_spd_pos_cmp_value(QEIV2_Type *qeiv2_x, uint32_t cmp)
804 {
805 qeiv2_x->SPDCMP = QEIV2_SPDCMP_SPDCMP_SET(cmp);
806 }
807
808 /**
809 * @brief set compare match options
810 *
811 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
812 * @param[in] ignore_zcmp ignore zcmp
813 * @param[in] ignore_phcmp ignore phcmp
814 * @param[in] ignore_spdposcmp ignore spdposcmp
815 * when set @ref qeiv2_spd_tmr_as_spd_tm, this is spdcmp value. (ABZ encoder)
816 * when set @ref qeiv2_spd_tmr_as_pos_angle, this is poscmp value. (sin or sincos encoder)
817 * @param[in] ignore_rotate_dir ignore encoder rotation direction. (ABZ encoder)
818 * @param[in] rotate_dir when don't ignore rotation direction, match rotation direction. @ref qeiv2_rotate_dir_t. (ABZ encoder)
819 * @param[in] ignore_pos_dir ignore position increase or decrease direction. (sin or sincos encoder)
820 * @param[in] pos_dir when don't ignore position direction, match position direction. @ref qeiv2_position_dir_t. (sin or sincos encoder)
821 */
qeiv2_set_cmp_match_option(QEIV2_Type * qeiv2_x,bool ignore_zcmp,bool ignore_phcmp,bool ignore_spdposcmp,bool ignore_rotate_dir,qeiv2_rotate_dir_t rotate_dir,bool ignore_pos_dir,qeiv2_position_dir_t pos_dir)822 static inline void qeiv2_set_cmp_match_option(QEIV2_Type *qeiv2_x, bool ignore_zcmp, bool ignore_phcmp, bool ignore_spdposcmp,
823 bool ignore_rotate_dir, qeiv2_rotate_dir_t rotate_dir, bool ignore_pos_dir, qeiv2_position_dir_t pos_dir)
824 {
825 qeiv2_x->MATCH_CFG = (qeiv2_x->MATCH_CFG & (~(QEIV2_MATCH_CFG_ZCMPDIS_MASK | QEIV2_MATCH_CFG_PHASE_MATCH_DIS_MASK | QEIV2_MATCH_CFG_SPDCMPDIS_MASK
826 | QEIV2_MATCH_CFG_DIRCMPDIS_MASK | QEIV2_MATCH_CFG_DIRCMP_MASK
827 | QEIV2_MATCH_CFG_POS_MATCH_OPT_MASK | QEIV2_MATCH_CFG_POS_MATCH_DIR_MASK)))
828 | QEIV2_MATCH_CFG_ZCMPDIS_SET(ignore_zcmp) | QEIV2_MATCH_CFG_PHASE_MATCH_DIS_SET(ignore_phcmp)
829 | QEIV2_MATCH_CFG_SPDCMPDIS_SET(ignore_spdposcmp)
830 | QEIV2_MATCH_CFG_DIRCMPDIS_SET(ignore_rotate_dir) | QEIV2_MATCH_CFG_DIRCMP_SET(rotate_dir)
831 | QEIV2_MATCH_CFG_POS_MATCH_OPT_SET(!ignore_pos_dir) | QEIV2_MATCH_CFG_POS_MATCH_DIR_SET(pos_dir);
832 }
833
834 /**
835 * @brief set zcnt compare2 value
836 *
837 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
838 * @param[in] cmp zcnt compare2 value
839 */
qeiv2_set_z_cmp2_value(QEIV2_Type * qeiv2_x,uint32_t cmp)840 static inline void qeiv2_set_z_cmp2_value(QEIV2_Type *qeiv2_x, uint32_t cmp)
841 {
842 qeiv2_x->ZCMP2 = QEIV2_ZCMP2_ZCMP2_SET(cmp);
843 }
844
845 /**
846 * @brief set phcnt compare2 value
847 *
848 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
849 * @param[in] cmp phcnt compare2 value
850 */
qeiv2_set_phcnt_cmp2_value(QEIV2_Type * qeiv2_x,uint32_t cmp)851 static inline void qeiv2_set_phcnt_cmp2_value(QEIV2_Type *qeiv2_x, uint32_t cmp)
852 {
853 qeiv2_x->PHCMP2 = QEIV2_PHCMP2_PHCMP2_SET(cmp);
854 }
855
856 /**
857 * @brief set spdcnt or position compare2 value. It's selected by CR register rd_sel bit.
858 *
859 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
860 * @param[in] cmp spdcnt or position compare2 value
861 */
qeiv2_set_spd_pos_cmp2_value(QEIV2_Type * qeiv2_x,uint32_t cmp)862 static inline void qeiv2_set_spd_pos_cmp2_value(QEIV2_Type *qeiv2_x, uint32_t cmp)
863 {
864 qeiv2_x->SPDCMP2 = QEIV2_SPDCMP2_SPDCMP2_SET(cmp);
865 }
866
867 /**
868 * @brief set compare2 match options
869 *
870 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
871 * @param[in] ignore_zcmp ignore zcmp
872 * @param[in] ignore_phcmp ignore phcmp
873 * @param[in] ignore_spdposcmp ignore spdposcmp.
874 * when set @ref qeiv2_spd_tmr_as_spd_tm, this is spdcmp value. (ABZ encoder)
875 * when set @ref qeiv2_spd_tmr_as_pos_angle, this is poscmp value. (sin or sincos encoder)
876 * @param[in] ignore_rotate_dir ignore encoder rotation direction. (ABZ encoder)
877 * @param[in] rotate_dir when don't ignore rotation direction, match rotation direction. @ref qeiv2_rotate_dir_t. (ABZ encoder)
878 * @param[in] ignore_pos_dir ignore position increase or decrease direction. (sin or sincos encoder)
879 * @param[in] pos_dir when don't ignore position direction, match position direction. @ref qeiv2_position_dir_t. (sin or sincos encoder)
880 */
qeiv2_set_cmp2_match_option(QEIV2_Type * qeiv2_x,bool ignore_zcmp,bool ignore_phcmp,bool ignore_spdposcmp,bool ignore_rotate_dir,qeiv2_rotate_dir_t rotate_dir,bool ignore_pos_dir,qeiv2_position_dir_t pos_dir)881 static inline void qeiv2_set_cmp2_match_option(QEIV2_Type *qeiv2_x, bool ignore_zcmp, bool ignore_phcmp, bool ignore_spdposcmp,
882 bool ignore_rotate_dir, qeiv2_rotate_dir_t rotate_dir, bool ignore_pos_dir, qeiv2_position_dir_t pos_dir)
883 {
884 qeiv2_x->MATCH_CFG = (qeiv2_x->MATCH_CFG & ~(QEIV2_MATCH_CFG_ZCMP2DIS_MASK | QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_MASK | QEIV2_MATCH_CFG_SPDCMP2DIS_MASK
885 | QEIV2_MATCH_CFG_DIRCMP2DIS_MASK | QEIV2_MATCH_CFG_DIRCMP2_MASK
886 | QEIV2_MATCH_CFG_POS_MATCH2_OPT_MASK | QEIV2_MATCH_CFG_POS_MATCH2_DIR_MASK))
887 | QEIV2_MATCH_CFG_ZCMP2DIS_SET(ignore_zcmp) | QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_SET(ignore_phcmp)
888 | QEIV2_MATCH_CFG_SPDCMP2DIS_SET(ignore_spdposcmp)
889 | QEIV2_MATCH_CFG_DIRCMP2DIS_SET(ignore_rotate_dir) | QEIV2_MATCH_CFG_DIRCMP2_SET(rotate_dir)
890 | QEIV2_MATCH_CFG_POS_MATCH2_OPT_SET(!ignore_pos_dir) | QEIV2_MATCH_CFG_POS_MATCH2_DIR_SET(pos_dir);
891 }
892
893 /**
894 * @brief config signal enablement and edge
895 *
896 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
897 * @param[in] siga_en enable signal A/U
898 * @param[in] sigb_en enable signal B/V
899 * @param[in] sigz_en enable signal Z/W
900 * @param[in] posedge_en enable rise edge
901 * @param[in] negedge_en enable fall edge
902 */
qeiv2_config_abz_uvw_signal_edge(QEIV2_Type * qeiv2_x,bool siga_en,bool sigb_en,bool sigz_en,bool posedge_en,bool negedge_en)903 static inline void qeiv2_config_abz_uvw_signal_edge(QEIV2_Type *qeiv2_x, bool siga_en, bool sigb_en, bool sigz_en, bool posedge_en, bool negedge_en)
904 {
905 qeiv2_x->QEI_CFG = (qeiv2_x->QEI_CFG & ~(QEIV2_QEI_CFG_SIGA_EN_MASK | QEIV2_QEI_CFG_SIGB_EN_MASK | QEIV2_QEI_CFG_SIGZ_EN_MASK
906 | QEIV2_QEI_CFG_POSIDGE_EN_MASK | QEIV2_QEI_CFG_NEGEDGE_EN_MASK))
907 | (QEIV2_QEI_CFG_SIGA_EN_SET(siga_en) | QEIV2_QEI_CFG_SIGB_EN_SET(sigb_en) | QEIV2_QEI_CFG_SIGZ_EN_SET(sigz_en)
908 | QEIV2_QEI_CFG_POSIDGE_EN_SET(posedge_en) | QEIV2_QEI_CFG_NEGEDGE_EN_SET(negedge_en));
909 }
910
911 /**
912 * @brief set pulse0 value
913 *
914 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
915 * @param[in] pulse_num for speed detection, will count the cycle number for configed pulse_num
916 */
qeiv2_set_pulse0_num(QEIV2_Type * qeiv2_x,uint32_t pulse_num)917 static inline void qeiv2_set_pulse0_num(QEIV2_Type *qeiv2_x, uint32_t pulse_num)
918 {
919 qeiv2_x->PULSE0_NUM = QEIV2_PULSE0_NUM_PULSE0_NUM_SET(pulse_num);
920 }
921
922 /**
923 * @brief get cycle0 snap0 value
924 *
925 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
926 * @retval cycle0 snap0 value
927 */
qeiv2_get_pulse0_cycle_snap0(QEIV2_Type * qeiv2_x)928 static inline uint32_t qeiv2_get_pulse0_cycle_snap0(QEIV2_Type *qeiv2_x)
929 {
930 return qeiv2_x->CYCLE0_SNAP0;
931 }
932
933 /**
934 * @brief get cycle0 snap1 value
935 *
936 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
937 * @retval cycle0 snap1 value
938 */
qeiv2_get_pulse0_cycle_snap1(QEIV2_Type * qeiv2_x)939 static inline uint32_t qeiv2_get_pulse0_cycle_snap1(QEIV2_Type *qeiv2_x)
940 {
941 return qeiv2_x->CYCLE0_SNAP1;
942 }
943
944 /**
945 * @brief set pulse1 value
946 *
947 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
948 * @param[in] pulse_num for speed detection, will count the cycle number for configed pulse_num
949 */
qeiv2_set_pulse1_num(QEIV2_Type * qeiv2_x,uint32_t pulse_num)950 static inline void qeiv2_set_pulse1_num(QEIV2_Type *qeiv2_x, uint32_t pulse_num)
951 {
952 qeiv2_x->PULSE1_NUM = QEIV2_PULSE1_NUM_PULSE1_NUM_SET(pulse_num);
953 }
954
955 /**
956 * @brief get cycle1 snap0 value
957 *
958 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
959 * @retval cycle1 snap0 value
960 */
qeiv2_get_pulse1_cycle_snap0(QEIV2_Type * qeiv2_x)961 static inline uint32_t qeiv2_get_pulse1_cycle_snap0(QEIV2_Type *qeiv2_x)
962 {
963 return qeiv2_x->CYCLE1_SNAP0;
964 }
965
966 /**
967 * @brief get cycle1 snap1 value
968 *
969 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
970 * @retval cycle1 snap1 value
971 */
qeiv2_get_pulse1_cycle_snap1(QEIV2_Type * qeiv2_x)972 static inline uint32_t qeiv2_get_pulse1_cycle_snap1(QEIV2_Type *qeiv2_x)
973 {
974 return qeiv2_x->CYCLE1_SNAP1;
975 }
976
977 /**
978 * @brief set cycle0 value
979 *
980 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
981 * @param[in] cycle_num for speed detection, will count the pulse number for configed cycle_num
982 */
qeiv2_set_cycle0_num(QEIV2_Type * qeiv2_x,uint32_t cycle_num)983 static inline void qeiv2_set_cycle0_num(QEIV2_Type *qeiv2_x, uint32_t cycle_num)
984 {
985 qeiv2_x->CYCLE0_NUM = QEIV2_CYCLE0_NUM_CYCLE0_NUM_SET(cycle_num);
986 }
987
988 /**
989 * @brief get pulse0 snap0 value
990 *
991 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
992 * @retval pulse0 snap0 value
993 */
qeiv2_get_cycle0_pulse_snap0(QEIV2_Type * qeiv2_x)994 static inline uint32_t qeiv2_get_cycle0_pulse_snap0(QEIV2_Type *qeiv2_x)
995 {
996 return qeiv2_x->PULSE0_SNAP0;
997 }
998
999 /**
1000 * @brief get pulse0 snap1 value
1001 *
1002 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1003 * @retval pulse0 snap1 value
1004 */
qeiv2_get_cycle0_pulse_snap1(QEIV2_Type * qeiv2_x)1005 static inline uint32_t qeiv2_get_cycle0_pulse_snap1(QEIV2_Type *qeiv2_x)
1006 {
1007 return qeiv2_x->PULSE0_SNAP1;
1008 }
1009
1010 /**
1011 * @brief get pulse0cycle snap0 value
1012 *
1013 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1014 * @retval pulse0cycle snap0 value
1015 */
qeiv2_get_cycle0_pulse0cycle_snap0(QEIV2_Type * qeiv2_x)1016 static inline uint32_t qeiv2_get_cycle0_pulse0cycle_snap0(QEIV2_Type *qeiv2_x)
1017 {
1018 return qeiv2_x->PULSE0CYCLE_SNAP0;
1019 }
1020
1021 /**
1022 * @brief get pulse0cycle snap1 value
1023 *
1024 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1025 * @retval pulse0cycle snap1 value
1026 */
qeiv2_get_cycle0_pulse0cycle_snap1(QEIV2_Type * qeiv2_x)1027 static inline uint32_t qeiv2_get_cycle0_pulse0cycle_snap1(QEIV2_Type *qeiv2_x)
1028 {
1029 return qeiv2_x->PULSE0CYCLE_SNAP1;
1030 }
1031
1032 /**
1033 * @brief set cycle1 value
1034 *
1035 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1036 * @param[in] cycle_num for speed detection, will count the pulse number for configed cycle_num
1037 */
qeiv2_set_cycle1_num(QEIV2_Type * qeiv2_x,uint32_t cycle_num)1038 static inline void qeiv2_set_cycle1_num(QEIV2_Type *qeiv2_x, uint32_t cycle_num)
1039 {
1040 qeiv2_x->CYCLE1_NUM = QEIV2_CYCLE1_NUM_CYCLE1_NUM_SET(cycle_num);
1041 }
1042
1043 #if defined(HPM_IP_FEATURE_QEIV2_ONESHOT_MODE) && HPM_IP_FEATURE_QEIV2_ONESHOT_MODE
1044 /**
1045 * @brief disable cycle0 oneshot mode
1046 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1047 */
qeiv2_disable_cycle0_oneshot_mode(QEIV2_Type * qeiv2_x)1048 static inline void qeiv2_disable_cycle0_oneshot_mode(QEIV2_Type *qeiv2_x)
1049 {
1050 qeiv2_x->QEI_CFG &= ~QEIV2_QEI_CFG_CYCLE0_ONESHOT_MASK;
1051 }
1052
1053 /**
1054 * @brief enable cycle0 oneshot mode
1055 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1056 */
qeiv2_enable_cycle0_oneshot_mode(QEIV2_Type * qeiv2_x)1057 static inline void qeiv2_enable_cycle0_oneshot_mode(QEIV2_Type *qeiv2_x)
1058 {
1059 qeiv2_x->QEI_CFG |= QEIV2_QEI_CFG_CYCLE0_ONESHOT_MASK;
1060 }
1061
1062 /**
1063 * @brief disable cycle1 oneshot mode
1064 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1065 */
qeiv2_disable_cycle1_oneshot_mode(QEIV2_Type * qeiv2_x)1066 static inline void qeiv2_disable_cycle1_oneshot_mode(QEIV2_Type *qeiv2_x)
1067 {
1068 qeiv2_x->QEI_CFG &= ~QEIV2_QEI_CFG_CYCLE1_ONESHOT_MASK;
1069 }
1070
1071 /**
1072 * @brief enable cycle1 oneshot mode
1073 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1074 */
qeiv2_enable_cycle1_oneshot_mode(QEIV2_Type * qeiv2_x)1075 static inline void qeiv2_enable_cycle1_oneshot_mode(QEIV2_Type *qeiv2_x)
1076 {
1077 qeiv2_x->QEI_CFG |= QEIV2_QEI_CFG_CYCLE1_ONESHOT_MASK;
1078 }
1079
1080 /**
1081 * @brief disable pulse0 oneshot mode
1082 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1083 */
qeiv2_disable_pulse0_oneshot_mode(QEIV2_Type * qeiv2_x)1084 static inline void qeiv2_disable_pulse0_oneshot_mode(QEIV2_Type *qeiv2_x)
1085 {
1086 qeiv2_x->QEI_CFG &= ~QEIV2_QEI_CFG_PULSE0_ONESHOT_MASK;
1087 }
1088
1089 /**
1090 * @brief enable pulse0 oneshot mode
1091 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1092 */
qeiv2_enable_pulse0_oneshot_mode(QEIV2_Type * qeiv2_x)1093 static inline void qeiv2_enable_pulse0_oneshot_mode(QEIV2_Type *qeiv2_x)
1094 {
1095 qeiv2_x->QEI_CFG |= QEIV2_QEI_CFG_PULSE0_ONESHOT_MASK;
1096 }
1097
1098 /**
1099 * @brief disable pulse1 oneshot mode
1100 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1101 */
qeiv2_disable_pulse1_oneshot_mode(QEIV2_Type * qeiv2_x)1102 static inline void qeiv2_disable_pulse1_oneshot_mode(QEIV2_Type *qeiv2_x)
1103 {
1104 qeiv2_x->QEI_CFG &= ~QEIV2_QEI_CFG_PULSE1_ONESHOT_MASK;
1105 }
1106
1107 /**
1108 * @brief enable pulse1 oneshot mode
1109 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1110 */
qeiv2_enable_pulse1_oneshot_mode(QEIV2_Type * qeiv2_x)1111 static inline void qeiv2_enable_pulse1_oneshot_mode(QEIV2_Type *qeiv2_x)
1112 {
1113 qeiv2_x->QEI_CFG |= QEIV2_QEI_CFG_PULSE1_ONESHOT_MASK;
1114 }
1115 #endif
1116
1117 #if defined(HPM_IP_FEATURE_QEIV2_SW_RESTART_TRG) && HPM_IP_FEATURE_QEIV2_SW_RESTART_TRG
1118 /**
1119 * @brief disable trigger cycle0
1120 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1121 */
qeiv2_disable_trig_cycle0(QEIV2_Type * qeiv2_x)1122 static inline void qeiv2_disable_trig_cycle0(QEIV2_Type *qeiv2_x)
1123 {
1124 qeiv2_x->QEI_CFG &= ~QEIV2_QEI_CFG_TRIG_CYCLE0_EN_MASK;
1125 }
1126
1127 /**
1128 * @brief enable trigger cycle0
1129 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1130 */
qeiv2_enable_trig_cycle0(QEIV2_Type * qeiv2_x)1131 static inline void qeiv2_enable_trig_cycle0(QEIV2_Type *qeiv2_x)
1132 {
1133 qeiv2_x->QEI_CFG |= QEIV2_QEI_CFG_TRIG_CYCLE0_EN_MASK;
1134 }
1135
1136 /**
1137 * @brief disable trigger cycle1
1138 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1139 */
qeiv2_disable_trig_cycle1(QEIV2_Type * qeiv2_x)1140 static inline void qeiv2_disable_trig_cycle1(QEIV2_Type *qeiv2_x)
1141 {
1142 qeiv2_x->QEI_CFG &= ~QEIV2_QEI_CFG_TRIG_CYCLE1_EN_MASK;
1143 }
1144
1145 /**
1146 * @brief enable trigger cycle1
1147 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1148 */
qeiv2_enable_trig_cycle1(QEIV2_Type * qeiv2_x)1149 static inline void qeiv2_enable_trig_cycle1(QEIV2_Type *qeiv2_x)
1150 {
1151 qeiv2_x->QEI_CFG |= QEIV2_QEI_CFG_TRIG_CYCLE1_EN_MASK;
1152 }
1153
1154 /**
1155 * @brief disable trigger pulse0
1156 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1157 */
qeiv2_disable_trig_pulse0(QEIV2_Type * qeiv2_x)1158 static inline void qeiv2_disable_trig_pulse0(QEIV2_Type *qeiv2_x)
1159 {
1160 qeiv2_x->QEI_CFG &= ~QEIV2_QEI_CFG_TRIG_PULSE0_EN_MASK;
1161 }
1162
1163 /**
1164 * @brief enable trigger pulse0
1165 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1166 */
qeiv2_enable_trig_pulse0(QEIV2_Type * qeiv2_x)1167 static inline void qeiv2_enable_trig_pulse0(QEIV2_Type *qeiv2_x)
1168 {
1169 qeiv2_x->QEI_CFG |= QEIV2_QEI_CFG_TRIG_PULSE0_EN_MASK;
1170 }
1171
1172 /**
1173 * @brief disable trigger pulse1
1174 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1175 */
qeiv2_disable_trig_pulse1(QEIV2_Type * qeiv2_x)1176 static inline void qeiv2_disable_trig_pulse1(QEIV2_Type *qeiv2_x)
1177 {
1178 qeiv2_x->QEI_CFG &= ~QEIV2_QEI_CFG_TRIG_PULSE1_EN_MASK;
1179 }
1180
1181 /**
1182 * @brief enable trigger pulse1
1183 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1184 */
qeiv2_enable_trig_pulse1(QEIV2_Type * qeiv2_x)1185 static inline void qeiv2_enable_trig_pulse1(QEIV2_Type *qeiv2_x)
1186 {
1187 qeiv2_x->QEI_CFG |= QEIV2_QEI_CFG_TRIG_PULSE1_EN_MASK;
1188 }
1189
1190 /**
1191 * @brief software restart cycle0
1192 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1193 */
qeiv2_sw_restart_cycle0(QEIV2_Type * qeiv2_x)1194 static inline void qeiv2_sw_restart_cycle0(QEIV2_Type *qeiv2_x)
1195 {
1196 qeiv2_x->QEI_CFG |= QEIV2_QEI_CFG_SW_PULSE0_RESTART_MASK;
1197 }
1198
1199 /**
1200 * @brief software restart cycle1
1201 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1202 */
qeiv2_sw_restart_cycle1(QEIV2_Type * qeiv2_x)1203 static inline void qeiv2_sw_restart_cycle1(QEIV2_Type *qeiv2_x)
1204 {
1205 qeiv2_x->QEI_CFG |= QEIV2_QEI_CFG_SW_PULSE1_RESTART_MASK;
1206 }
1207
1208 /**
1209 * @brief software restart pulse0
1210 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1211 */
qeiv2_sw_restart_pulse0(QEIV2_Type * qeiv2_x)1212 static inline void qeiv2_sw_restart_pulse0(QEIV2_Type *qeiv2_x)
1213 {
1214 qeiv2_x->QEI_CFG |= QEIV2_QEI_CFG_SW_CYCLE0_RESTART_MASK;
1215 }
1216
1217 /**
1218 * @brief software restart pulse1
1219 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1220 */
qeiv2_sw_restart_pulse1(QEIV2_Type * qeiv2_x)1221 static inline void qeiv2_sw_restart_pulse1(QEIV2_Type *qeiv2_x)
1222 {
1223 qeiv2_x->QEI_CFG |= QEIV2_QEI_CFG_SW_CYCLE1_RESTART_MASK;
1224 }
1225 #endif
1226
1227 /**
1228 * @brief get pulse1 snap0 value
1229 *
1230 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1231 * @retval pulse1 snap0 value
1232 */
qeiv2_get_cycle1_pulse_snap0(QEIV2_Type * qeiv2_x)1233 static inline uint32_t qeiv2_get_cycle1_pulse_snap0(QEIV2_Type *qeiv2_x)
1234 {
1235 return qeiv2_x->PULSE1_SNAP0;
1236 }
1237
1238 /**
1239 * @brief get pulse1 snap1 value
1240 *
1241 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1242 * @retval pulse1 snap1 value
1243 */
qeiv2_get_cycle1_pulse_snap1(QEIV2_Type * qeiv2_x)1244 static inline uint32_t qeiv2_get_cycle1_pulse_snap1(QEIV2_Type *qeiv2_x)
1245 {
1246 return qeiv2_x->PULSE1_SNAP1;
1247 }
1248
1249 /**
1250 * @brief get pulse1cycle snap0 value
1251 *
1252 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1253 * @retval pulse1cycle snap0 value
1254 */
qeiv2_get_cycle1_pulse1cycle_snap0(QEIV2_Type * qeiv2_x)1255 static inline uint32_t qeiv2_get_cycle1_pulse1cycle_snap0(QEIV2_Type *qeiv2_x)
1256 {
1257 return qeiv2_x->PULSE1CYCLE_SNAP0;
1258 }
1259
1260 /**
1261 * @brief get pulse1cycle snap1 value
1262 *
1263 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1264 * @retval pulse01cycle snap1 value
1265 */
qeiv2_get_cycle1_pulse1cycle_snap1(QEIV2_Type * qeiv2_x)1266 static inline uint32_t qeiv2_get_cycle1_pulse1cycle_snap1(QEIV2_Type *qeiv2_x)
1267 {
1268 return qeiv2_x->PULSE1CYCLE_SNAP1;
1269 }
1270
1271 /**
1272 * @brief enable or disable clear counter if detect direction change
1273 *
1274 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1275 * @param[in] enable enable or disable clear counter if detect direction change
1276 */
qeiv2_clear_counter_when_dir_chg(QEIV2_Type * qeiv2_x,bool enable)1277 static inline void qeiv2_clear_counter_when_dir_chg(QEIV2_Type *qeiv2_x, bool enable)
1278 {
1279 if (enable) {
1280 qeiv2_x->QEI_CFG |= QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_MASK;
1281 } else {
1282 qeiv2_x->QEI_CFG &= ~QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_MASK;
1283 }
1284 }
1285
1286 /**
1287 * @brief adcx config
1288 *
1289 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1290 * @param[in] config qeiv2_adc_config_t
1291 * @param[in] enable enable or disable adcx
1292 */
qeiv2_config_adcx(QEIV2_Type * qeiv2_x,qeiv2_adc_config_t * config,bool enable)1293 static inline void qeiv2_config_adcx(QEIV2_Type *qeiv2_x, qeiv2_adc_config_t *config, bool enable)
1294 {
1295 uint32_t tmp;
1296 tmp = QEIV2_ADCX_CFG0_X_ADCSEL_SET(config->adc_select) | QEIV2_ADCX_CFG0_X_CHAN_SET(config->adc_channel);
1297 qeiv2_x->ADCX_CFG1 = QEIV2_ADCX_CFG1_X_PARAM1_SET(config->param1) | QEIV2_ADCX_CFG1_X_PARAM0_SET(config->param0);
1298 qeiv2_x->ADCX_CFG2 = QEIV2_ADCX_CFG2_X_OFFSET_SET(config->offset);
1299 if (enable) {
1300 tmp |= QEIV2_ADCX_CFG0_X_ADC_ENABLE_MASK;
1301 } else {
1302 tmp &= ~QEIV2_ADCX_CFG0_X_ADC_ENABLE_MASK;
1303 }
1304 qeiv2_x->ADCX_CFG0 = tmp;
1305 }
1306
1307 /**
1308 * @brief adcy config
1309 *
1310 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1311 * @param[in] config qeiv2_adc_config_t
1312 * @param[in] enable enable or disable adcy
1313 */
qeiv2_config_adcy(QEIV2_Type * qeiv2_x,qeiv2_adc_config_t * config,bool enable)1314 static inline void qeiv2_config_adcy(QEIV2_Type *qeiv2_x, qeiv2_adc_config_t *config, bool enable)
1315 {
1316 uint32_t tmp;
1317 tmp = QEIV2_ADCY_CFG0_Y_ADCSEL_SET(config->adc_select) | QEIV2_ADCY_CFG0_Y_CHAN_SET(config->adc_channel);
1318 qeiv2_x->ADCY_CFG1 = QEIV2_ADCY_CFG1_Y_PARAM1_SET(config->param1) | QEIV2_ADCY_CFG1_Y_PARAM0_SET(config->param0);
1319 qeiv2_x->ADCY_CFG2 = QEIV2_ADCY_CFG2_Y_OFFSET_SET(config->offset);
1320 if (enable) {
1321 tmp |= QEIV2_ADCY_CFG0_Y_ADC_ENABLE_MASK;
1322 } else {
1323 tmp &= ~QEIV2_ADCY_CFG0_Y_ADC_ENABLE_MASK;
1324 }
1325 qeiv2_x->ADCY_CFG0 = tmp;
1326 }
1327
1328 /**
1329 * @brief set adcx and adcy delay
1330 *
1331 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1332 * @param[in] delay x/y delay, default 1.25us@200MHz, max 80ms
1333 */
qeiv2_set_adc_xy_delay(QEIV2_Type * qeiv2_x,uint32_t delay)1334 static inline void qeiv2_set_adc_xy_delay(QEIV2_Type *qeiv2_x, uint32_t delay)
1335 {
1336 qeiv2_x->CAL_CFG = QEIV2_CAL_CFG_XY_DELAY_SET(delay);
1337 }
1338
1339 /**
1340 * @brief set position threshold
1341 *
1342 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1343 * @param[in] threshold Position change threshold. When two position changes exceed this value,
1344 * it will be considered as an invalid position and no valid signal will be output.
1345 */
qeiv2_set_position_threshold(QEIV2_Type * qeiv2_x,uint32_t threshold)1346 static inline void qeiv2_set_position_threshold(QEIV2_Type *qeiv2_x, uint32_t threshold)
1347 {
1348 qeiv2_x->POS_THRESHOLD = QEIV2_POS_THRESHOLD_POS_THRESHOLD_SET(threshold);
1349 }
1350
1351 /**
1352 * @brief set uvw position option
1353 *
1354 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1355 * @param[in] opt qeiv2_uvw_pos_opt_t
1356 */
qeiv2_set_uvw_position_opt(QEIV2_Type * qeiv2_x,qeiv2_uvw_pos_opt_t opt)1357 static inline void qeiv2_set_uvw_position_opt(QEIV2_Type *qeiv2_x, qeiv2_uvw_pos_opt_t opt)
1358 {
1359 qeiv2_x->QEI_CFG = (qeiv2_x->QEI_CFG & ~QEIV2_QEI_CFG_UVW_POS_OPT0_MASK) | QEIV2_QEI_CFG_UVW_POS_OPT0_SET(opt);
1360 }
1361
1362 /**
1363 * @brief set config uvw position
1364 *
1365 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1366 * @param[in] idx uvw position config index
1367 * @arg @ref qeiv2_uvw_pos_idx_t
1368 * @param[in] u_pos_sel U position selection based by uvw position option
1369 * @arg @ref QEIV2_UVW_POS_OPT_CUR_SEL_LOW
1370 * @arg @ref QEIV2_UVW_POS_OPT_CUR_SEL_HIGH
1371 * @arg @ref QEIV2_UVW_POS_OPT_CUR_SEL_EDGE
1372 * @arg @ref QEIV2_UVW_POS_OPT_NEX_SEL_LOW
1373 * @arg @ref QEIV2_UVW_POS_OPT_NEX_SEL_HIGH
1374 * @param[in] v_pos_sel V position selection based by uvw position option
1375 * @arg @ref QEIV2_UVW_POS_OPT_CUR_SEL_LOW
1376 * @arg @ref QEIV2_UVW_POS_OPT_CUR_SEL_HIGH
1377 * @arg @ref QEIV2_UVW_POS_OPT_CUR_SEL_EDGE
1378 * @arg @ref QEIV2_UVW_POS_OPT_NEX_SEL_LOW
1379 * @arg @ref QEIV2_UVW_POS_OPT_NEX_SEL_HIGH
1380 * @param[in] w_pos_sel W position selection based by uvw position option
1381 * @arg @ref QEIV2_UVW_POS_OPT_CUR_SEL_LOW
1382 * @arg @ref QEIV2_UVW_POS_OPT_CUR_SEL_HIGH
1383 * @arg @ref QEIV2_UVW_POS_OPT_CUR_SEL_EDGE
1384 * @arg @ref QEIV2_UVW_POS_OPT_NEX_SEL_LOW
1385 * @arg @ref QEIV2_UVW_POS_OPT_NEX_SEL_HIGH
1386 * @param[in] enable enable this uvw config
1387 */
qeiv2_set_uvw_position_sel(QEIV2_Type * qeiv2_x,qeiv2_uvw_pos_idx_t idx,uint8_t u_pos_sel,uint8_t v_pos_sel,uint8_t w_pos_sel,bool enable)1388 static inline void qeiv2_set_uvw_position_sel(QEIV2_Type *qeiv2_x, qeiv2_uvw_pos_idx_t idx, uint8_t u_pos_sel, uint8_t v_pos_sel,
1389 uint8_t w_pos_sel, bool enable)
1390 {
1391 uint32_t tmp;
1392 tmp = QEIV2_UVW_POS_CFG_U_POS_SEL_SET(u_pos_sel)
1393 | QEIV2_UVW_POS_CFG_V_POS_SEL_SET(v_pos_sel)
1394 | QEIV2_UVW_POS_CFG_W_POS_SEL_SET(w_pos_sel);
1395 if (enable) {
1396 tmp |= QEIV2_UVW_POS_CFG_POS_EN_MASK;
1397 } else {
1398 tmp &= ~QEIV2_UVW_POS_CFG_POS_EN_MASK;
1399 }
1400 qeiv2_x->UVW_POS_CFG[idx] = tmp;
1401 }
1402
1403 /**
1404 * @brief set uvw position
1405 *
1406 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1407 * @param[in] idx uvw position config index
1408 * @arg @ref qeiv2_uvw_pos_idx_t
1409 * @param[in] pos angle corresponding to UVW signal position
1410 */
qeiv2_set_uvw_position(QEIV2_Type * qeiv2_x,qeiv2_uvw_pos_idx_t idx,uint32_t pos)1411 static inline void qeiv2_set_uvw_position(QEIV2_Type *qeiv2_x, qeiv2_uvw_pos_idx_t idx, uint32_t pos)
1412 {
1413 qeiv2_x->UVW_POS[idx] = pos;
1414 }
1415
1416 /**
1417 * @brief set z phase counter value
1418 *
1419 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1420 * @param[in] cnt z phase counter value
1421 */
qeiv2_set_z_phase(QEIV2_Type * qeiv2_x,uint32_t cnt)1422 static inline void qeiv2_set_z_phase(QEIV2_Type *qeiv2_x, uint32_t cnt)
1423 {
1424 qeiv2_x->COUNT[QEIV2_COUNT_CURRENT].Z = cnt;
1425 }
1426
1427 /**
1428 * @brief set phase counter value
1429 *
1430 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1431 * @param[in] cnt phase counter value
1432 */
qeiv2_set_phase_cnt(QEIV2_Type * qeiv2_x,uint32_t cnt)1433 static inline void qeiv2_set_phase_cnt(QEIV2_Type *qeiv2_x, uint32_t cnt)
1434 {
1435 qeiv2_x->PHASE_CNT = cnt;
1436 }
1437
1438 /**
1439 * @brief get phase counter value
1440 *
1441 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1442 * @retval phase counter value
1443 */
qeiv2_get_phase_cnt(QEIV2_Type * qeiv2_x)1444 static inline uint32_t qeiv2_get_phase_cnt(QEIV2_Type *qeiv2_x)
1445 {
1446 return qeiv2_x->PHASE_CNT;
1447 }
1448
1449 /**
1450 * @brief update phase counter value
1451 *
1452 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1453 * @param[in] inc set to add value to phase_cnt
1454 * @param[in] dec set to minus value to phase_cnt (set inc and dec same time willl act inc)
1455 * @param[in] value value to be added or minus from phase_cnt. only valid when inc or dec is set in one 32bit write operation.
1456 */
qeiv2_update_phase_cnt(QEIV2_Type * qeiv2_x,bool inc,bool dec,uint32_t value)1457 static inline void qeiv2_update_phase_cnt(QEIV2_Type *qeiv2_x, bool inc, bool dec, uint32_t value)
1458 {
1459 qeiv2_x->PHASE_UPDATE = QEIV2_PHASE_UPDATE_INC_SET(inc) | QEIV2_PHASE_UPDATE_DEC_SET(dec) | QEIV2_PHASE_UPDATE_VALUE_SET(value);
1460 }
1461
1462 /**
1463 * @brief set position value
1464 *
1465 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1466 * @param[in] pos position
1467 */
qeiv2_set_position(QEIV2_Type * qeiv2_x,uint32_t pos)1468 static inline void qeiv2_set_position(QEIV2_Type *qeiv2_x, uint32_t pos)
1469 {
1470 qeiv2_x->POSITION = pos;
1471 }
1472
1473 /**
1474 * @brief get position value
1475 *
1476 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1477 * @retval position value
1478 */
qeiv2_get_postion(QEIV2_Type * qeiv2_x)1479 static inline uint32_t qeiv2_get_postion(QEIV2_Type *qeiv2_x)
1480 {
1481 return qeiv2_x->POSITION;
1482 }
1483
1484 /**
1485 * @brief update position value
1486 *
1487 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1488 * @param[in] inc set to add value to position
1489 * @param[in] dec set to minus cnt value to position (set inc and dec same time willl act inc)
1490 * @param[in] value value to be added or minus from position. only valid when inc or dec is set in one 32bit write operation.
1491 */
qeiv2_update_position(QEIV2_Type * qeiv2_x,bool inc,bool dec,uint32_t value)1492 static inline void qeiv2_update_position(QEIV2_Type *qeiv2_x, bool inc, bool dec, uint32_t value)
1493 {
1494 qeiv2_x->POSITION_UPDATE = QEIV2_POSITION_UPDATE_INC_SET(inc) | QEIV2_POSITION_UPDATE_DEC_SET(dec) | QEIV2_POSITION_UPDATE_VALUE_SET(value);
1495 }
1496
1497 /**
1498 * @brief get angle value
1499 *
1500 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1501 * @retval angle value
1502 */
qeiv2_get_angle(QEIV2_Type * qeiv2_x)1503 static inline uint32_t qeiv2_get_angle(QEIV2_Type *qeiv2_x)
1504 {
1505 return qeiv2_x->ANGLE;
1506 }
1507
1508 /**
1509 * @brief config position timeout for mmc module
1510 *
1511 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1512 * @param[in] tm postion timeout value
1513 * @param[in] enable enable position timeout feature. If timeout, send valid again.
1514 */
qeiv2_config_position_timeout(QEIV2_Type * qeiv2_x,uint32_t tm,bool enable)1515 static inline void qeiv2_config_position_timeout(QEIV2_Type *qeiv2_x, uint32_t tm, bool enable)
1516 {
1517 uint32_t tmp;
1518 tmp = QEIV2_POS_TIMEOUT_TIMEOUT_SET(tm);
1519 if (enable) {
1520 tmp |= QEIV2_POS_TIMEOUT_ENABLE_MASK;
1521 } else {
1522 tmp &= ~QEIV2_POS_TIMEOUT_ENABLE_MASK;
1523 }
1524 qeiv2_x->POS_TIMEOUT = tmp;
1525 }
1526
1527 /**
1528 * @brief config phcnt compare match condition
1529 *
1530 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1531 * @param[in] config @ref qeiv2_phcnt_cmp_match_config_t
1532 * @return status_invalid_argument or status_success
1533 */
1534 hpm_stat_t qeiv2_config_phcnt_cmp_match_condition(QEIV2_Type *qeiv2_x, qeiv2_phcnt_cmp_match_config_t *config);
1535
1536 /**
1537 * @brief config position compare match condition
1538 *
1539 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1540 * @param[in] config @ref qeiv2_pos_cmp_match_config_t
1541 * @return status_invalid_argument or status_success
1542 */
1543 hpm_stat_t qeiv2_config_position_cmp_match_condition(QEIV2_Type *qeiv2_x, qeiv2_pos_cmp_match_config_t *config);
1544
1545 /**
1546 * @brief config phcnt compare2 match condition
1547 *
1548 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1549 * @param[in] config @ref qeiv2_phcnt_cmp_match_config_t
1550 * @return status_invalid_argument or status_success
1551 */
1552 hpm_stat_t qeiv2_config_phcnt_cmp2_match_condition(QEIV2_Type *qeiv2_x, qeiv2_phcnt_cmp_match_config_t *config);
1553
1554 /**
1555 * @brief config position compare2 match condition
1556 *
1557 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1558 * @param[in] config @ref qeiv2_pos_cmp_match_config_t
1559 * @return status_invalid_argument or status_success
1560 */
1561 hpm_stat_t qeiv2_config_position_cmp2_match_condition(QEIV2_Type *qeiv2_x, qeiv2_pos_cmp_match_config_t *config);
1562
1563 /**
1564 * @brief get uvw position default config
1565 *
1566 * @param[out] config uvw position default config structure pointer
1567 */
1568 void qeiv2_get_uvw_position_defconfig(qeiv2_uvw_config_t *config);
1569
1570 /**
1571 * @brief config uvw position
1572 *
1573 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1574 * @param[in] config uvw position config structure pointer
1575 * @return status_invalid_argument or status_success
1576 */
1577 hpm_stat_t qeiv2_config_uvw_position(QEIV2_Type *qeiv2_x, qeiv2_uvw_config_t *config);
1578
1579 /**
1580 * @brief config signal filter
1581 *
1582 * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n)
1583 * @param[in] phase filter phase
1584 * @arg @ref qeiv2_filter_phase_t
1585 * @param[in] outinv Filter will invert the output
1586 * @param[in] mode qeiv2_filter_mode_t
1587 * @param[in] sync set to enable sychronization input signal with TRGM clock
1588 * @param[in] filtlen defines the filter counter length.
1589 */
1590 void qeiv2_config_filter(QEIV2_Type *qeiv2_x, qeiv2_filter_phase_t phase, bool outinv, qeiv2_filter_mode_t mode, bool sync, uint32_t filtlen);
1591
1592 #ifdef __cplusplus
1593 }
1594 #endif
1595 /**
1596 * @}
1597 */
1598 #endif /* HPM_QEIV2_DRV_H */
1599